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authorShiraz Hashim <shiraz.hashim@st.com>2012-08-03 06:03:10 -0400
committerViresh Kumar <viresh.kumar@linaro.org>2012-11-26 06:25:32 -0500
commit80515a5a2e3c35e2994105f19af27650e8a16c51 (patch)
treeb117ab7aa811d0da139fc03aa4f906cbc5b560cb /arch/arm/mach-spear3xx/spear320.c
parent300a6856324a56955ab909e1dca93dabb8464c8a (diff)
ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT
SPEAr3xx architecture includes shared/multiplexed irqs for certain set of devices. The multiplexor provides a single interrupt to parent interrupt controller (VIC) on behalf of a group of devices. There can be multiple groups available on SPEAr3xx variants but not exceeding 4. The number of devices in a group can differ, further they may share same set of status/mask registers spanning across different bit masks. Also in some cases the group may not have enable or other registers. This makes software little complex. Present implementation was non-DT and had few complex data structures to decipher banks, number of irqs supported, mask and registers involved. This patch simplifies the overall design and convert it in to DT. It also removes all registration from individual SoC files and bring them in to common shirq.c. Also updated the corresponding documentation for DT binding of shirq. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/mach-spear3xx/spear320.c')
-rw-r--r--arch/arm/mach-spear3xx/spear320.c204
1 files changed, 0 insertions, 204 deletions
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fd823c624575..707504b84e0e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -19,7 +19,6 @@
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h> 20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <plat/shirq.h>
23#include <mach/generic.h> 22#include <mach/generic.h>
24#include <mach/spear.h> 23#include <mach/spear.h>
25 24
@@ -28,184 +27,6 @@
28#define SPEAR320_SSP0_BASE UL(0xA5000000) 27#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000) 28#define SPEAR320_SSP1_BASE UL(0xA6000000)
30 29
31/* Interrupt registers offsets and masks */
32#define SPEAR320_INT_STS_MASK_REG 0x04
33#define SPEAR320_INT_CLR_MASK_REG 0x04
34#define SPEAR320_INT_ENB_MASK_REG 0x08
35#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38#define SPEAR320_EMI_IRQ_MASK (1 << 7)
39#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40#define SPEAR320_SPP_IRQ_MASK (1 << 9)
41#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44#define SPEAR320_UART1_IRQ_MASK (1 << 13)
45#define SPEAR320_UART2_IRQ_MASK (1 << 14)
46#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
53
54#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
57
58/* SPEAr320 Virtual irq definitions */
59/* IRQs sharing IRQ_GEN_RAS_1 */
60#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
63
64/* IRQs sharing IRQ_GEN_RAS_2 */
65#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
71
72/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
84
85/* spear3xx shared irq */
86static struct shirq_dev_config shirq_ras1_config[] = {
87 {
88 .virq = SPEAR320_VIRQ_EMI,
89 .status_mask = SPEAR320_EMI_IRQ_MASK,
90 .clear_mask = SPEAR320_EMI_IRQ_MASK,
91 }, {
92 .virq = SPEAR320_VIRQ_CLCD,
93 .status_mask = SPEAR320_CLCD_IRQ_MASK,
94 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
95 }, {
96 .virq = SPEAR320_VIRQ_SPP,
97 .status_mask = SPEAR320_SPP_IRQ_MASK,
98 .clear_mask = SPEAR320_SPP_IRQ_MASK,
99 },
100};
101
102static struct spear_shirq shirq_ras1 = {
103 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
104 .dev_config = shirq_ras1_config,
105 .dev_count = ARRAY_SIZE(shirq_ras1_config),
106 .regs = {
107 .enb_reg = -1,
108 .status_reg = SPEAR320_INT_STS_MASK_REG,
109 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
110 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
111 .reset_to_clear = 1,
112 },
113};
114
115static struct shirq_dev_config shirq_ras3_config[] = {
116 {
117 .virq = SPEAR320_VIRQ_PLGPIO,
118 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
119 .status_mask = SPEAR320_GPIO_IRQ_MASK,
120 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
121 }, {
122 .virq = SPEAR320_VIRQ_I2S_PLAY,
123 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
124 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
125 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
126 }, {
127 .virq = SPEAR320_VIRQ_I2S_REC,
128 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
129 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
130 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
131 },
132};
133
134static struct spear_shirq shirq_ras3 = {
135 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
136 .dev_config = shirq_ras3_config,
137 .dev_count = ARRAY_SIZE(shirq_ras3_config),
138 .regs = {
139 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
140 .reset_to_enb = 1,
141 .status_reg = SPEAR320_INT_STS_MASK_REG,
142 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
143 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
144 .reset_to_clear = 1,
145 },
146};
147
148static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
149 {
150 .virq = SPEAR320_VIRQ_CANU,
151 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
152 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
153 }, {
154 .virq = SPEAR320_VIRQ_CANL,
155 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
156 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
157 }, {
158 .virq = SPEAR320_VIRQ_UART1,
159 .status_mask = SPEAR320_UART1_IRQ_MASK,
160 .clear_mask = SPEAR320_UART1_IRQ_MASK,
161 }, {
162 .virq = SPEAR320_VIRQ_UART2,
163 .status_mask = SPEAR320_UART2_IRQ_MASK,
164 .clear_mask = SPEAR320_UART2_IRQ_MASK,
165 }, {
166 .virq = SPEAR320_VIRQ_SSP1,
167 .status_mask = SPEAR320_SSP1_IRQ_MASK,
168 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
169 }, {
170 .virq = SPEAR320_VIRQ_SSP2,
171 .status_mask = SPEAR320_SSP2_IRQ_MASK,
172 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
173 }, {
174 .virq = SPEAR320_VIRQ_SMII0,
175 .status_mask = SPEAR320_SMII0_IRQ_MASK,
176 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
177 }, {
178 .virq = SPEAR320_VIRQ_MII1_SMII1,
179 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
180 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
181 }, {
182 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
183 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
184 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
185 }, {
186 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
187 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
188 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
189 }, {
190 .virq = SPEAR320_VIRQ_I2C1,
191 .status_mask = SPEAR320_I2C1_IRQ_MASK,
192 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
193 },
194};
195
196static struct spear_shirq shirq_intrcomm_ras = {
197 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
198 .dev_config = shirq_intrcomm_ras_config,
199 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
200 .regs = {
201 .enb_reg = -1,
202 .status_reg = SPEAR320_INT_STS_MASK_REG,
203 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
204 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
205 .reset_to_clear = 1,
206 },
207};
208
209/* DMAC platform data's slave info */ 30/* DMAC platform data's slave info */
210struct pl08x_channel_data spear320_dma_info[] = { 31struct pl08x_channel_data spear320_dma_info[] = {
211 { 32 {
@@ -416,36 +237,11 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
416 237
417static void __init spear320_dt_init(void) 238static void __init spear320_dt_init(void)
418{ 239{
419 void __iomem *base;
420 int ret;
421
422 pl080_plat_data.slave_channels = spear320_dma_info; 240 pl080_plat_data.slave_channels = spear320_dma_info;
423 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 241 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
424 242
425 of_platform_populate(NULL, of_default_bus_match_table, 243 of_platform_populate(NULL, of_default_bus_match_table,
426 spear320_auxdata_lookup, NULL); 244 spear320_auxdata_lookup, NULL);
427
428 /* shared irq registration */
429 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
430 if (base) {
431 /* shirq 1 */
432 shirq_ras1.regs.base = base;
433 ret = spear_shirq_register(&shirq_ras1);
434 if (ret)
435 pr_err("Error registering Shared IRQ 1\n");
436
437 /* shirq 3 */
438 shirq_ras3.regs.base = base;
439 ret = spear_shirq_register(&shirq_ras3);
440 if (ret)
441 pr_err("Error registering Shared IRQ 3\n");
442
443 /* shirq 4 */
444 shirq_intrcomm_ras.regs.base = base;
445 ret = spear_shirq_register(&shirq_intrcomm_ras);
446 if (ret)
447 pr_err("Error registering Shared IRQ 4\n");
448 }
449} 245}
450 246
451static const char * const spear320_dt_board_compat[] = { 247static const char * const spear320_dt_board_compat[] = {
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