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authorViresh Kumar <viresh.kumar@st.com>2012-04-03 07:57:10 -0400
committerArnd Bergmann <arnd@arndb.de>2012-04-22 16:49:26 -0400
commit8076dd1b7deeaeb5c6f0b58be95c0a13164e1a99 (patch)
tree96e3741dec72d84de577b23c9e821a27bf371f63 /arch/arm/mach-spear3xx/spear320.c
parent52130b6033c580c27d968f64cd73209c9609e4e0 (diff)
SPEAr: Remove existing padmux support for SPEAr
We must use pinctrl framework instead of defining per SoC pinmux drivers. This patch removes existing padmux support present for SPEAr platform. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Diffstat (limited to 'arch/arm/mach-spear3xx/spear320.c')
-rw-r--r--arch/arm/mach-spear3xx/spear320.c403
1 files changed, 1 insertions, 402 deletions
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 1e74031e1213..4812c692ca35 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -23,373 +23,6 @@
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25 25
26/* pad multiplexing support */
27/* muxing registers */
28#define PAD_MUX_CONFIG_REG 0x0C
29#define MODE_CONFIG_REG 0x10
30
31/* modes */
32#define AUTO_NET_SMII_MODE (1 << 0)
33#define AUTO_NET_MII_MODE (1 << 1)
34#define AUTO_EXP_MODE (1 << 2)
35#define SMALL_PRINTERS_MODE (1 << 3)
36#define ALL_MODES 0xF
37
38struct pmx_mode spear320_auto_net_smii_mode = {
39 .id = AUTO_NET_SMII_MODE,
40 .name = "Automation Networking SMII Mode",
41 .mask = 0x00,
42};
43
44struct pmx_mode spear320_auto_net_mii_mode = {
45 .id = AUTO_NET_MII_MODE,
46 .name = "Automation Networking MII Mode",
47 .mask = 0x01,
48};
49
50struct pmx_mode spear320_auto_exp_mode = {
51 .id = AUTO_EXP_MODE,
52 .name = "Automation Expanded Mode",
53 .mask = 0x02,
54};
55
56struct pmx_mode spear320_small_printers_mode = {
57 .id = SMALL_PRINTERS_MODE,
58 .name = "Small Printers Mode",
59 .mask = 0x03,
60};
61
62/* devices */
63static struct pmx_dev_mode pmx_clcd_modes[] = {
64 {
65 .ids = AUTO_NET_SMII_MODE,
66 .mask = 0x0,
67 },
68};
69
70struct pmx_dev spear320_pmx_clcd = {
71 .name = "clcd",
72 .modes = pmx_clcd_modes,
73 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
74 .enb_on_reset = 1,
75};
76
77static struct pmx_dev_mode pmx_emi_modes[] = {
78 {
79 .ids = AUTO_EXP_MODE,
80 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
81 },
82};
83
84struct pmx_dev spear320_pmx_emi = {
85 .name = "emi",
86 .modes = pmx_emi_modes,
87 .mode_count = ARRAY_SIZE(pmx_emi_modes),
88 .enb_on_reset = 1,
89};
90
91static struct pmx_dev_mode pmx_fsmc_modes[] = {
92 {
93 .ids = ALL_MODES,
94 .mask = 0x0,
95 },
96};
97
98struct pmx_dev spear320_pmx_fsmc = {
99 .name = "fsmc",
100 .modes = pmx_fsmc_modes,
101 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
102 .enb_on_reset = 1,
103};
104
105static struct pmx_dev_mode pmx_spp_modes[] = {
106 {
107 .ids = SMALL_PRINTERS_MODE,
108 .mask = 0x0,
109 },
110};
111
112struct pmx_dev spear320_pmx_spp = {
113 .name = "spp",
114 .modes = pmx_spp_modes,
115 .mode_count = ARRAY_SIZE(pmx_spp_modes),
116 .enb_on_reset = 1,
117};
118
119static struct pmx_dev_mode pmx_sdhci_modes[] = {
120 {
121 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
122 SMALL_PRINTERS_MODE,
123 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
124 },
125};
126
127struct pmx_dev spear320_pmx_sdhci = {
128 .name = "sdhci",
129 .modes = pmx_sdhci_modes,
130 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
131 .enb_on_reset = 1,
132};
133
134static struct pmx_dev_mode pmx_i2s_modes[] = {
135 {
136 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
137 .mask = PMX_UART0_MODEM_MASK,
138 },
139};
140
141struct pmx_dev spear320_pmx_i2s = {
142 .name = "i2s",
143 .modes = pmx_i2s_modes,
144 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
145 .enb_on_reset = 1,
146};
147
148static struct pmx_dev_mode pmx_uart1_modes[] = {
149 {
150 .ids = ALL_MODES,
151 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
152 },
153};
154
155struct pmx_dev spear320_pmx_uart1 = {
156 .name = "uart1",
157 .modes = pmx_uart1_modes,
158 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
159 .enb_on_reset = 1,
160};
161
162static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
163 {
164 .ids = AUTO_EXP_MODE,
165 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
166 PMX_SSP_CS_MASK,
167 }, {
168 .ids = SMALL_PRINTERS_MODE,
169 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
170 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
171 },
172};
173
174struct pmx_dev spear320_pmx_uart1_modem = {
175 .name = "uart1_modem",
176 .modes = pmx_uart1_modem_modes,
177 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
178 .enb_on_reset = 1,
179};
180
181static struct pmx_dev_mode pmx_uart2_modes[] = {
182 {
183 .ids = ALL_MODES,
184 .mask = PMX_FIRDA_MASK,
185 },
186};
187
188struct pmx_dev spear320_pmx_uart2 = {
189 .name = "uart2",
190 .modes = pmx_uart2_modes,
191 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
192 .enb_on_reset = 1,
193};
194
195static struct pmx_dev_mode pmx_touchscreen_modes[] = {
196 {
197 .ids = AUTO_NET_SMII_MODE,
198 .mask = PMX_SSP_CS_MASK,
199 },
200};
201
202struct pmx_dev spear320_pmx_touchscreen = {
203 .name = "touchscreen",
204 .modes = pmx_touchscreen_modes,
205 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
206 .enb_on_reset = 1,
207};
208
209static struct pmx_dev_mode pmx_can_modes[] = {
210 {
211 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
212 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
213 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
214 },
215};
216
217struct pmx_dev spear320_pmx_can = {
218 .name = "can",
219 .modes = pmx_can_modes,
220 .mode_count = ARRAY_SIZE(pmx_can_modes),
221 .enb_on_reset = 1,
222};
223
224static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
225 {
226 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
227 .mask = PMX_SSP_CS_MASK,
228 },
229};
230
231struct pmx_dev spear320_pmx_sdhci_led = {
232 .name = "sdhci_led",
233 .modes = pmx_sdhci_led_modes,
234 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
235 .enb_on_reset = 1,
236};
237
238static struct pmx_dev_mode pmx_pwm0_modes[] = {
239 {
240 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
241 .mask = PMX_UART0_MODEM_MASK,
242 }, {
243 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
244 .mask = PMX_MII_MASK,
245 },
246};
247
248struct pmx_dev spear320_pmx_pwm0 = {
249 .name = "pwm0",
250 .modes = pmx_pwm0_modes,
251 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_pwm1_modes[] = {
256 {
257 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
258 .mask = PMX_UART0_MODEM_MASK,
259 }, {
260 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
261 .mask = PMX_MII_MASK,
262 },
263};
264
265struct pmx_dev spear320_pmx_pwm1 = {
266 .name = "pwm1",
267 .modes = pmx_pwm1_modes,
268 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
269 .enb_on_reset = 1,
270};
271
272static struct pmx_dev_mode pmx_pwm2_modes[] = {
273 {
274 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
275 .mask = PMX_SSP_CS_MASK,
276 }, {
277 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
278 .mask = PMX_MII_MASK,
279 },
280};
281
282struct pmx_dev spear320_pmx_pwm2 = {
283 .name = "pwm2",
284 .modes = pmx_pwm2_modes,
285 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
286 .enb_on_reset = 1,
287};
288
289static struct pmx_dev_mode pmx_pwm3_modes[] = {
290 {
291 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
292 .mask = PMX_MII_MASK,
293 },
294};
295
296struct pmx_dev spear320_pmx_pwm3 = {
297 .name = "pwm3",
298 .modes = pmx_pwm3_modes,
299 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
300 .enb_on_reset = 1,
301};
302
303static struct pmx_dev_mode pmx_ssp1_modes[] = {
304 {
305 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
306 .mask = PMX_MII_MASK,
307 },
308};
309
310struct pmx_dev spear320_pmx_ssp1 = {
311 .name = "ssp1",
312 .modes = pmx_ssp1_modes,
313 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
314 .enb_on_reset = 1,
315};
316
317static struct pmx_dev_mode pmx_ssp2_modes[] = {
318 {
319 .ids = AUTO_NET_SMII_MODE,
320 .mask = PMX_MII_MASK,
321 },
322};
323
324struct pmx_dev spear320_pmx_ssp2 = {
325 .name = "ssp2",
326 .modes = pmx_ssp2_modes,
327 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
328 .enb_on_reset = 1,
329};
330
331static struct pmx_dev_mode pmx_mii1_modes[] = {
332 {
333 .ids = AUTO_NET_MII_MODE,
334 .mask = 0x0,
335 },
336};
337
338struct pmx_dev spear320_pmx_mii1 = {
339 .name = "mii1",
340 .modes = pmx_mii1_modes,
341 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
342 .enb_on_reset = 1,
343};
344
345static struct pmx_dev_mode pmx_smii0_modes[] = {
346 {
347 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
348 .mask = PMX_MII_MASK,
349 },
350};
351
352struct pmx_dev spear320_pmx_smii0 = {
353 .name = "smii0",
354 .modes = pmx_smii0_modes,
355 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
356 .enb_on_reset = 1,
357};
358
359static struct pmx_dev_mode pmx_smii1_modes[] = {
360 {
361 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
362 .mask = PMX_MII_MASK,
363 },
364};
365
366struct pmx_dev spear320_pmx_smii1 = {
367 .name = "smii1",
368 .modes = pmx_smii1_modes,
369 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
370 .enb_on_reset = 1,
371};
372
373static struct pmx_dev_mode pmx_i2c1_modes[] = {
374 {
375 .ids = AUTO_EXP_MODE,
376 .mask = 0x0,
377 },
378};
379
380struct pmx_dev spear320_pmx_i2c1 = {
381 .name = "i2c1",
382 .modes = pmx_i2c1_modes,
383 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
384 .enb_on_reset = 1,
385};
386
387/* pmx driver structure */
388static struct pmx_driver pmx_driver = {
389 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
390 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
391};
392
393/* spear3xx shared irq */ 26/* spear3xx shared irq */
394static struct shirq_dev_config shirq_ras1_config[] = { 27static struct shirq_dev_config shirq_ras1_config[] = {
395 { 28 {
@@ -514,27 +147,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
514 }, 147 },
515}; 148};
516 149
517/* padmux devices to enable */
518static struct pmx_dev *spear320_evb_pmx_devs[] = {
519 /* spear3xx specific devices */
520 &spear3xx_pmx_i2c,
521 &spear3xx_pmx_ssp,
522 &spear3xx_pmx_mii,
523 &spear3xx_pmx_uart0,
524
525 /* spear320 specific devices */
526 &spear320_pmx_fsmc,
527 &spear320_pmx_sdhci,
528 &spear320_pmx_i2s,
529 &spear320_pmx_uart1,
530 &spear320_pmx_uart2,
531 &spear320_pmx_can,
532 &spear320_pmx_pwm0,
533 &spear320_pmx_pwm1,
534 &spear320_pmx_pwm2,
535 &spear320_pmx_mii1,
536};
537
538/* DMAC platform data's slave info */ 150/* DMAC platform data's slave info */
539struct pl08x_channel_data spear320_dma_info[] = { 151struct pl08x_channel_data spear320_dma_info[] = {
540 { 152 {
@@ -772,7 +384,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
772static void __init spear320_dt_init(void) 384static void __init spear320_dt_init(void)
773{ 385{
774 void __iomem *base; 386 void __iomem *base;
775 int ret = 0; 387 int ret;
776 388
777 pl080_plat_data.slave_channels = spear320_dma_info; 389 pl080_plat_data.slave_channels = spear320_dma_info;
778 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 390 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
@@ -801,19 +413,6 @@ static void __init spear320_dt_init(void)
801 if (ret) 413 if (ret)
802 pr_err("Error registering Shared IRQ 4\n"); 414 pr_err("Error registering Shared IRQ 4\n");
803 } 415 }
804
805 if (of_machine_is_compatible("st,spear320-evb")) {
806 /* pmx initialization */
807 pmx_driver.base = base;
808 pmx_driver.mode = &spear320_auto_net_mii_mode;
809 pmx_driver.devs = spear320_evb_pmx_devs;
810 pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
811
812 ret = pmx_register(&pmx_driver);
813 if (ret)
814 pr_err("padmux: registration failed. err no: %d\n",
815 ret);
816 }
817} 416}
818 417
819static const char * const spear320_dt_board_compat[] = { 418static const char * const spear320_dt_board_compat[] = {
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