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authorArnd Bergmann <arnd@arndb.de>2011-09-08 08:15:22 -0400
committerArnd Bergmann <arnd@arndb.de>2012-09-14 05:15:00 -0400
commit2d8b21d95f44989e09fd9b36ca9f061ad5bc567e (patch)
treea869e842cea511480f5cd8ecdedb109aa8c16072 /arch/arm/mach-spear13xx/platsmp.c
parente4f2d97920f2256e5af035281e8ac35030493bf8 (diff)
ARM: SoC: convert spear13xx to SMP operations
Convert the spear13xx platform to use struct smp_operations to provide its SMP and CPU hotplug operations. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: spear-devel@list.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-spear13xx/platsmp.c')
-rw-r--r--arch/arm/mach-spear13xx/platsmp.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index f5d07f2663d7..806343c7b5d8 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -19,6 +19,7 @@
19#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
20#include <asm/smp_scu.h> 20#include <asm/smp_scu.h>
21#include <mach/spear.h> 21#include <mach/spear.h>
22#include <mach/generic.h>
22 23
23/* 24/*
24 * control for which core is the next to come out of the secondary 25 * control for which core is the next to come out of the secondary
@@ -28,9 +29,8 @@ volatile int __cpuinitdata pen_release = -1;
28static DEFINE_SPINLOCK(boot_lock); 29static DEFINE_SPINLOCK(boot_lock);
29 30
30static void __iomem *scu_base = IOMEM(VA_SCU_BASE); 31static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
31extern void spear13xx_secondary_startup(void);
32 32
33void __cpuinit platform_secondary_init(unsigned int cpu) 33static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
34{ 34{
35 /* 35 /*
36 * if any interrupts are already enabled for the primary 36 * if any interrupts are already enabled for the primary
@@ -53,7 +53,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
53 spin_unlock(&boot_lock); 53 spin_unlock(&boot_lock);
54} 54}
55 55
56int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 56static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
57{ 57{
58 unsigned long timeout; 58 unsigned long timeout;
59 59
@@ -97,7 +97,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
97 * Initialise the CPU possible map early - this describes the CPUs 97 * Initialise the CPU possible map early - this describes the CPUs
98 * which may be present or become present in the system. 98 * which may be present or become present in the system.
99 */ 99 */
100void __init smp_init_cpus(void) 100static void __init spear13xx_smp_init_cpus(void)
101{ 101{
102 unsigned int i, ncores = scu_get_core_count(scu_base); 102 unsigned int i, ncores = scu_get_core_count(scu_base);
103 103
@@ -113,7 +113,7 @@ void __init smp_init_cpus(void)
113 set_smp_cross_call(gic_raise_softirq); 113 set_smp_cross_call(gic_raise_softirq);
114} 114}
115 115
116void __init platform_smp_prepare_cpus(unsigned int max_cpus) 116static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
117{ 117{
118 118
119 scu_enable(scu_base); 119 scu_enable(scu_base);
@@ -125,3 +125,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
125 */ 125 */
126 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); 126 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
127} 127}
128
129struct smp_operations spear13xx_smp_ops __initdata = {
130 .smp_init_cpus = spear13xx_smp_init_cpus,
131 .smp_prepare_cpus = spear13xx_smp_prepare_cpus,
132 .smp_secondary_init = spear13xx_secondary_init,
133 .smp_boot_secondary = spear13xx_boot_secondary,
134#ifdef CONFIG_HOTPLUG_CPU
135 .cpu_die = spear13xx_cpu_die,
136#endif
137};