diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-12-02 09:12:47 -0500 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2013-03-12 12:39:47 -0400 |
commit | a7ed099ffc8edf2a6dccd8a22469347f5cdcfa57 (patch) | |
tree | b56901430602574233ad23008cfd7c23babd20c3 /arch/arm/mach-spear/platsmp.c | |
parent | 0ec05c3e4ac6548fcab4b6a74254a22ef251e1fd (diff) |
ARM: spear: move all files to mach-spear
There are no conflicting files between the three mach-spear* directories
and plat-spear any more, so we can now move all file to a common
mach-spear directory.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/mach-spear/platsmp.c')
-rw-r--r-- | arch/arm/mach-spear/platsmp.c | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c new file mode 100644 index 000000000000..af4ade61cd95 --- /dev/null +++ b/arch/arm/mach-spear/platsmp.c | |||
@@ -0,0 +1,130 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/platsmp.c | ||
3 | * | ||
4 | * based upon linux/arch/arm/mach-realview/platsmp.c | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics Ltd. | ||
7 | * Shiraz Hashim <shiraz.hashim@st.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/delay.h> | ||
15 | #include <linux/jiffies.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/smp.h> | ||
18 | #include <linux/irqchip/arm-gic.h> | ||
19 | #include <asm/cacheflush.h> | ||
20 | #include <asm/smp_scu.h> | ||
21 | #include <mach/spear.h> | ||
22 | #include <mach/generic.h> | ||
23 | |||
24 | static DEFINE_SPINLOCK(boot_lock); | ||
25 | |||
26 | static void __iomem *scu_base = IOMEM(VA_SCU_BASE); | ||
27 | |||
28 | static void __cpuinit spear13xx_secondary_init(unsigned int cpu) | ||
29 | { | ||
30 | /* | ||
31 | * if any interrupts are already enabled for the primary | ||
32 | * core (e.g. timer irq), then they will not have been enabled | ||
33 | * for us: do so | ||
34 | */ | ||
35 | gic_secondary_init(0); | ||
36 | |||
37 | /* | ||
38 | * let the primary processor know we're out of the | ||
39 | * pen, then head off into the C entry point | ||
40 | */ | ||
41 | pen_release = -1; | ||
42 | smp_wmb(); | ||
43 | |||
44 | /* | ||
45 | * Synchronise with the boot thread. | ||
46 | */ | ||
47 | spin_lock(&boot_lock); | ||
48 | spin_unlock(&boot_lock); | ||
49 | } | ||
50 | |||
51 | static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
52 | { | ||
53 | unsigned long timeout; | ||
54 | |||
55 | /* | ||
56 | * set synchronisation state between this boot processor | ||
57 | * and the secondary one | ||
58 | */ | ||
59 | spin_lock(&boot_lock); | ||
60 | |||
61 | /* | ||
62 | * The secondary processor is waiting to be released from | ||
63 | * the holding pen - release it, then wait for it to flag | ||
64 | * that it has been released by resetting pen_release. | ||
65 | * | ||
66 | * Note that "pen_release" is the hardware CPU ID, whereas | ||
67 | * "cpu" is Linux's internal ID. | ||
68 | */ | ||
69 | pen_release = cpu; | ||
70 | flush_cache_all(); | ||
71 | outer_flush_all(); | ||
72 | |||
73 | timeout = jiffies + (1 * HZ); | ||
74 | while (time_before(jiffies, timeout)) { | ||
75 | smp_rmb(); | ||
76 | if (pen_release == -1) | ||
77 | break; | ||
78 | |||
79 | udelay(10); | ||
80 | } | ||
81 | |||
82 | /* | ||
83 | * now the secondary core is starting up let it run its | ||
84 | * calibrations, then wait for it to finish | ||
85 | */ | ||
86 | spin_unlock(&boot_lock); | ||
87 | |||
88 | return pen_release != -1 ? -ENOSYS : 0; | ||
89 | } | ||
90 | |||
91 | /* | ||
92 | * Initialise the CPU possible map early - this describes the CPUs | ||
93 | * which may be present or become present in the system. | ||
94 | */ | ||
95 | static void __init spear13xx_smp_init_cpus(void) | ||
96 | { | ||
97 | unsigned int i, ncores = scu_get_core_count(scu_base); | ||
98 | |||
99 | if (ncores > nr_cpu_ids) { | ||
100 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | ||
101 | ncores, nr_cpu_ids); | ||
102 | ncores = nr_cpu_ids; | ||
103 | } | ||
104 | |||
105 | for (i = 0; i < ncores; i++) | ||
106 | set_cpu_possible(i, true); | ||
107 | } | ||
108 | |||
109 | static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus) | ||
110 | { | ||
111 | |||
112 | scu_enable(scu_base); | ||
113 | |||
114 | /* | ||
115 | * Write the address of secondary startup into the system-wide location | ||
116 | * (presently it is in SRAM). The BootMonitor waits until it receives a | ||
117 | * soft interrupt, and then the secondary CPU branches to this address. | ||
118 | */ | ||
119 | __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); | ||
120 | } | ||
121 | |||
122 | struct smp_operations spear13xx_smp_ops __initdata = { | ||
123 | .smp_init_cpus = spear13xx_smp_init_cpus, | ||
124 | .smp_prepare_cpus = spear13xx_smp_prepare_cpus, | ||
125 | .smp_secondary_init = spear13xx_secondary_init, | ||
126 | .smp_boot_secondary = spear13xx_boot_secondary, | ||
127 | #ifdef CONFIG_HOTPLUG_CPU | ||
128 | .cpu_die = spear13xx_cpu_die, | ||
129 | #endif | ||
130 | }; | ||