arm: socfpga: Add SMP support for actual socfpga harware

Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 10 insertions, 7 deletions

diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 68dd1b69512a..248196809202 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -47,16 +47,19 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
 {
         int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
 
-        memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+        if (cpu1start_addr) {
+                memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-        __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+                __raw_writel(virt_to_phys(socfpga_secondary_startup),
+                        (sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
 
-        flush_cache_all();
-        smp_wmb();
-        outer_clean_range(0, trampoline_size);
+                flush_cache_all();
+                smp_wmb();
+                outer_clean_range(0, trampoline_size);
 
-        /* This will release CPU #1 out of reset.*/
-        __raw_writel(0, rst_manager_base_addr + 0x10);
+                /* This will release CPU #1 out of reset.*/
+                __raw_writel(0, rst_manager_base_addr + 0x10);
+        }
 
         return 0;
 }