Merge branch 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman <horms@verge.net.au>:
  This series is based on the renesas/soc branch of the arm-soc tree.
  There will be a subquent 'SoC2' pull request which is based on this
  pull-request and a pull-request for boards.

* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: add fsi external clock sh7372
  ARM: shmobile: add fsi external clock on r8a7740
  ARM: shmobile: r8a7740: add FSI-DVI clocks
  ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks
  ARM: shmobile: sh7372: sh7372_fsidivX_clk become non-global
  sh: clkfwk: add sh_clk_fsidiv_register()
  ARM: shmobile: r8a7779: add USB OHCI clock support
  ARM: shmobile: r8a7779: add USB EHCI clock support
  ARM: shmobile: r8a7740: add USB24 clock explain
  ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

8 files changed, 64 insertions, 95 deletions

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 790dc68c4312..cefdd030361d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -728,7 +728,7 @@ fsia_ick_out:
 static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
 {
         struct clk *fsib_clk;
-        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
         long fsib_rate = 0;
         long fdiv_rate = 0;
         int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 0c27c810cf99..c826d77ab8a6 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
 static int fsi_b_set_rate(struct device *dev, int rate, int enable)
 {
         struct clk *fsib_clk;
-        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
         long fsib_rate = 0;
         long fdiv_rate = 0;
         int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 6729e0032180..eac49d59782f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -65,6 +65,9 @@
 #define SMSTPCR3        IOMEM(0xe615013c)
 #define SMSTPCR4        IOMEM(0xe6150140)
 
+#define FSIDIVA         IOMEM(0xFE1F8000)
+#define FSIDIVB         IOMEM(0xFE1F8008)
+
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
         .rate   = 32768,
@@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = {
 };
 
 /* USB clock */
+/*
+ * USBCKCR is controlling usb24 clock
+ * bit[7] : parent clock
+ * bit[6] : clock divide rate
+ * And this bit[7] is used as a "usb24s" from other devices.
+ * (Video clock / Sub clock / SPU clock)
+ * You can controll this clock as a below.
+ *
+ * struct clk *usb24    = clk_get(dev,  "usb24");
+ * struct clk *usb24s   = clk_get(NULL, "usb24s");
+ * struct clk *system   = clk_get(NULL, "system_clk");
+ * int rate = clk_get_rate(system);
+ *
+ * clk_set_parent(usb24s, system);  // for bit[7]
+ * clk_set_rate(usb24, rate / 2);   // for bit[6]
+ */
 static struct clk *usb24s_parents[] = {
         [0] = &system_clk,
         [1] = &extal2_clk
@@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = {
         &hdmi2_clk,
 };
 
+/* FSI DIV */
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
+
+static struct clk fsidivs[] = {
+        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
+};
+
 /* MSTP */
 enum {
         DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
@@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = {
 
         CLKDEV_ICK_ID("icka", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIA]),
         CLKDEV_ICK_ID("ickb", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIB]),
+        CLKDEV_ICK_ID("diva", "sh_fsi2",        &fsidivs[FSIDIV_A]),
+        CLKDEV_ICK_ID("divb", "sh_fsi2",        &fsidivs[FSIDIV_B]),
+        CLKDEV_ICK_ID("xcka", "sh_fsi2",        &fsiack_clk),
+        CLKDEV_ICK_ID("xckb", "sh_fsi2",        &fsibck_clk),
 };
 
 void __init r8a7740_clock_init(u8 md_ck)
@@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck)
         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
                 ret = clk_register(late_main_clks[k]);
 
+        if (!ret)
+                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index e48509b938cf..c019609da660 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
+        MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
@@ -98,6 +99,8 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
+        [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
         [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
         [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
         [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
@@ -153,6 +156,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+        CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
+        CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+        CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
         CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 430a90ffa120..4d57e342537b 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 };
 
 /* FSI DIV */
-static unsigned long fsidiv_recalc(struct clk *clk)
-{
-        unsigned long value;
-
-        value = __raw_readl(clk->mapping->base);
-
-        value >>= 16;
-        if (value < 2)
-                return 0;
-
-        return clk->parent->rate / value;
-}
-
-static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk_rate_div_range_round(clk, 2, 0xffff, rate);
-}
-
-static void fsidiv_disable(struct clk *clk)
-{
-        __raw_writel(0, clk->mapping->base);
-}
-
-static int fsidiv_enable(struct clk *clk)
-{
-        unsigned long value;
-
-        value  = __raw_readl(clk->mapping->base) >> 16;
-        if (value < 2)
-                return -EIO;
-
-        __raw_writel((value << 16) | 0x3, clk->mapping->base);
-
-        return 0;
-}
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
 
-static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
-{
-        int idx;
-
-        idx = (clk->parent->rate / rate) & 0xffff;
-        if (idx < 2)
-                return -EINVAL;
-
-        __raw_writel(idx << 16, clk->mapping->base);
-        return 0;
-}
-
-static struct sh_clk_ops fsidiv_clk_ops = {
-        .recalc         = fsidiv_recalc,
-        .round_rate     = fsidiv_round_rate,
-        .set_rate       = fsidiv_set_rate,
-        .enable         = fsidiv_enable,
-        .disable        = fsidiv_disable,
-};
-
-static struct clk_mapping fsidiva_clk_mapping = {
-        .phys   = FSIDIVA,
-        .len    = 8,
-};
-
-struct clk sh7372_fsidiva_clk = {
-        .ops            = &fsidiv_clk_ops,
-        .parent         = &div6_reparent_clks[DIV6_FSIA], /* late install */
-        .mapping        = &fsidiva_clk_mapping,
-};
-
-static struct clk_mapping fsidivb_clk_mapping = {
-        .phys   = FSIDIVB,
-        .len    = 8,
-};
-
-struct clk sh7372_fsidivb_clk = {
-        .ops            = &fsidiv_clk_ops,
-        .parent         = &div6_reparent_clks[DIV6_FSIB],  /* late install */
-        .mapping        = &fsidivb_clk_mapping,
-};
-
-static struct clk *late_main_clks[] = {
-        &sh7372_fsidiva_clk,
-        &sh7372_fsidivb_clk,
+static struct clk fsidivs[] = {
+        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
 };
 
 enum { MSTP001, MSTP000,
@@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
         CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
         CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
+        CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
+        CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),
 
         /* DIV4 clocks */
         CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
         CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
         CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
+        CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
+        CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
+        CLKDEV_ICK_ID("xcka", "sh_fsi2", &sh7372_fsiack_clk),
+        CLKDEV_ICK_ID("xckb", "sh_fsi2", &sh7372_fsibck_clk),
 };
 
 void __init sh7372_clock_init(void)
@@ -706,8 +636,8 @@ void __init sh7372_clock_init(void)
         if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
-        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
-                ret = clk_register(late_main_clks[k]);
+        if (!ret)
+                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 499f52d2a4a1..8ab0cd6ad6b0 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
         GPIO_FN_A19,
 
         /* IPSR0 */
-        GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+        GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
         GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
         GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
         GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index d65fbbe84678..26cd1016fad8 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -479,8 +479,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
 extern struct clk sh7372_pllc2_clk;
 extern struct clk sh7372_fsiack_clk;
 extern struct clk sh7372_fsibck_clk;
-extern struct clk sh7372_fsidiva_clk;
-extern struct clk sh7372_fsidivb_clk;
 
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index cbc26ba2a0a2..9513234d322b 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -140,7 +140,7 @@ enum {
         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-        FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+        FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 
         /* GPSR5 */
@@ -176,7 +176,7 @@ enum {
         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-        FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+        FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
         FN_SCIF_CLK, FN_TCLK0_C,
 
         /* IPSR1 */
@@ -447,7 +447,7 @@ enum {
         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-        PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+        USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
         SCIF_CLK_MARK, TCLK0_C_MARK,
 
         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(A18_MARK, FN_A18),
         PINMUX_DATA(A19_MARK, FN_A19),
 
-        PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+        PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(A19),
 
         /* IPSR0 */
-        GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+        GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
         GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
         GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
         GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 GP_4_30_FN, FN_IP8_18,
                 GP_4_29_FN, FN_IP8_17_16,
                 GP_4_28_FN, FN_IP0_2_0,
-                GP_4_27_FN, FN_PENC1,
-                GP_4_26_FN, FN_PENC0,
+                GP_4_27_FN, FN_USB_PENC1,
+                GP_4_26_FN, FN_USB_PENC0,
                 GP_4_25_FN, FN_IP8_15_12,
                 GP_4_24_FN, FN_IP8_11_8,
                 GP_4_23_FN, FN_IP8_7_4,
@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
                 /* IP0_2_0 [3] */
-                FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+                FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
         },
         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,