Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework

Conflicts:
	arch/sh/kernel/cpu/sh2/setup-sh7619.c
	arch/sh/kernel/cpu/sh2a/setup-mxg.c
	arch/sh/kernel/cpu/sh2a/setup-sh7201.c
	arch/sh/kernel/cpu/sh2a/setup-sh7203.c
	arch/sh/kernel/cpu/sh2a/setup-sh7206.c
	arch/sh/kernel/cpu/sh3/setup-sh7705.c
	arch/sh/kernel/cpu/sh3/setup-sh770x.c
	arch/sh/kernel/cpu/sh3/setup-sh7710.c
	arch/sh/kernel/cpu/sh3/setup-sh7720.c
	arch/sh/kernel/cpu/sh4/setup-sh4-202.c
	arch/sh/kernel/cpu/sh4/setup-sh7750.c
	arch/sh/kernel/cpu/sh4/setup-sh7760.c
	arch/sh/kernel/cpu/sh4a/setup-sh7343.c
	arch/sh/kernel/cpu/sh4a/setup-sh7366.c
	arch/sh/kernel/cpu/sh4a/setup-sh7722.c
	arch/sh/kernel/cpu/sh4a/setup-sh7723.c
	arch/sh/kernel/cpu/sh4a/setup-sh7724.c
	arch/sh/kernel/cpu/sh4a/setup-sh7763.c
	arch/sh/kernel/cpu/sh4a/setup-sh7770.c
	arch/sh/kernel/cpu/sh4a/setup-sh7780.c
	arch/sh/kernel/cpu/sh4a/setup-sh7785.c
	arch/sh/kernel/cpu/sh4a/setup-sh7786.c
	arch/sh/kernel/cpu/sh4a/setup-shx3.c
	arch/sh/kernel/cpu/sh5/setup-sh5.c
	drivers/serial/sh-sci.c
	drivers/serial/sh-sci.h
	include/linux/serial_sci.h

57 files changed, 19829 insertions, 0 deletions

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
new file mode 100644
index 000000000000..4d1b4c5c9389
--- /dev/null
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -0,0 +1,132 @@
+if ARCH_SHMOBILE
+
+comment "SH-Mobile System Type"
+
+config ARCH_SH7367
+        bool "SH-Mobile G3 (SH7367)"
+        select CPU_V6
+        select SH_CLK_CPG
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config ARCH_SH7377
+        bool "SH-Mobile G4 (SH7377)"
+        select CPU_V7
+        select SH_CLK_CPG
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config ARCH_SH7372
+        bool "SH-Mobile AP4 (SH7372)"
+        select CPU_V7
+        select SH_CLK_CPG
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config ARCH_SH73A0
+        bool "SH-Mobile AG5 (R8A73A00)"
+        select CPU_V7
+        select SH_CLK_CPG
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_GIC
+
+comment "SH-Mobile Board Type"
+
+config MACH_G3EVM
+        bool "G3EVM board"
+        depends on ARCH_SH7367
+        select ARCH_REQUIRE_GPIOLIB
+
+config MACH_G4EVM
+        bool "G4EVM board"
+        depends on ARCH_SH7377
+        select ARCH_REQUIRE_GPIOLIB
+
+config MACH_AP4EVB
+        bool "AP4EVB board"
+        depends on ARCH_SH7372
+        select ARCH_REQUIRE_GPIOLIB
+        select SH_LCD_MIPI_DSI
+
+choice
+        prompt "AP4EVB LCD panel selection"
+        default AP4EVB_QHD
+        depends on MACH_AP4EVB
+
+config AP4EVB_QHD
+        bool "MIPI-DSI QHD (960x540)"
+
+config AP4EVB_WVGA
+        bool "Parallel WVGA (800x480)"
+
+endchoice
+
+config MACH_AG5EVM
+        bool "AG5EVM board"
+        depends on ARCH_SH73A0
+
+config MACH_MACKEREL
+        bool "mackerel board"
+        depends on ARCH_SH7372
+        select ARCH_REQUIRE_GPIOLIB
+
+comment "SH-Mobile System Configuration"
+
+menu "Memory configuration"
+
+config MEMORY_START
+        hex "Physical memory start address"
+        default "0x50000000" if MACH_G3EVM
+        default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
+                                MACH_MACKEREL
+        default "0x00000000"
+        ---help---
+          Tweak this only when porting to a new machine which does not
+          already have a defconfig. Changing it from the known correct
+          value on any of the known systems will only lead to disaster.
+
+config MEMORY_SIZE
+        hex "Physical memory size"
+        default "0x08000000" if MACH_G3EVM
+        default "0x08000000" if MACH_G4EVM
+        default "0x20000000" if MACH_AG5EVM
+        default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
+        default "0x04000000"
+        help
+          This sets the default memory size assumed by your kernel. It can
+          be overridden as normal by the 'mem=' argument on the kernel command
+          line.
+
+endmenu
+
+menu "Timer and clock configuration"
+
+config SHMOBILE_TIMER_HZ
+        int "Kernel HZ (jiffies per second)"
+        range 32 1024
+        default "128"
+        help
+          Allows the configuration of the timer frequency. It is customary
+          to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
+          case of low timer frequencies other values may be more suitable.
+          SH-Mobile systems using a 32768 Hz RCLK for clock events may want
+          to select a HZ value such as 128 that can evenly divide RCLK.
+          A HZ value that does not divide evenly may cause timer drift.
+
+config SH_TIMER_CMT
+        bool "CMT timer driver"
+        default y
+        help
+          This enables build of the CMT timer driver.
+
+config SH_TIMER_TMU
+        bool "TMU timer driver"
+        default y
+        help
+          This enables build of the TMU timer driver.
+
+endmenu
+
+config SH_CLK_CPG
+        bool
+
+source "drivers/sh/Kconfig"
+
+endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
new file mode 100644
index 000000000000..e2507f66f9d5
--- /dev/null
+++ b/arch/arm/mach-shmobile/Makefile
@@ -0,0 +1,42 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common objects
+obj-y                           := timer.o console.o clock.o pm_runtime.o
+
+# CPU objects
+obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
+obj-$(CONFIG_ARCH_SH7377)       += setup-sh7377.o clock-sh7377.o intc-sh7377.o
+obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o clock-sh7372.o intc-sh7372.o
+obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
+
+# SMP objects
+smp-y                           := platsmp.o headsmp.o
+smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+smp-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
+
+# Pinmux setup
+pfc-y                           :=
+pfc-$(CONFIG_ARCH_SH7367)       += pfc-sh7367.o
+pfc-$(CONFIG_ARCH_SH7377)       += pfc-sh7377.o
+pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
+pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
+
+# IRQ objects
+obj-$(CONFIG_ARCH_SH7367)       += entry-intc.o
+obj-$(CONFIG_ARCH_SH7377)       += entry-intc.o
+obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
+obj-$(CONFIG_ARCH_SH73A0)       += entry-gic.o
+
+# Board objects
+obj-$(CONFIG_MACH_G3EVM)        += board-g3evm.o
+obj-$(CONFIG_MACH_G4EVM)        += board-g4evm.o
+obj-$(CONFIG_MACH_AP4EVB)       += board-ap4evb.o
+obj-$(CONFIG_MACH_AG5EVM)       += board-ag5evm.o
+obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
+
+# Framework support
+obj-$(CONFIG_SMP)               += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)      += $(pfc-y)
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
new file mode 100644
index 000000000000..1c08ee9de86a
--- /dev/null
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -0,0 +1,9 @@
+__ZRELADDR      := $(shell /bin/bash -c 'printf "0x%08x" \
+                     $$[$(CONFIG_MEMORY_START) + 0x8000]')
+
+   zreladdr-y   := $(__ZRELADDR)
+
+# Unsupported legacy stuff
+#
+#params_phys-y (Instead: Pass atags pointer in r2)
+#initrd_phys-y (Instead: Use compiled-in initramfs)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
new file mode 100644
index 000000000000..c18a740a4159
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -0,0 +1,315 @@
+/*
+ * arch/arm/mach-shmobile/board-ag5evm.c
+ *
+ * Copyright (C) 2010  Takashi Yoshii <yoshii.takashi.zj@renesas.com>
+ * Copyright (C) 2009  Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_sci.h>
+#include <linux/smsc911x.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/input/sh_keysc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+
+#include <sound/sh_fsi.h>
+
+#include <mach/hardware.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/traps.h>
+
+static struct resource smsc9220_resources[] = {
+        [0] = {
+                .start          = 0x14000000,
+                .end            = 0x14000000 + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = gic_spi(33), /* PINT1 */
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc9220_platdata = {
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device eth_device = {
+        .name           = "smsc911x",
+        .id             = 0,
+        .dev  = {
+                .platform_data = &smsc9220_platdata,
+        },
+        .resource       = smsc9220_resources,
+        .num_resources  = ARRAY_SIZE(smsc9220_resources),
+};
+
+static struct sh_keysc_info keysc_platdata = {
+        .mode           = SH_KEYSC_MODE_6,
+        .scan_timing    = 3,
+        .delay          = 100,
+        .keycodes       = {
+                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
+                KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
+                KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
+                KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
+                KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \
+                KEY_COFFEE,
+                KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP,
+                KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \
+                KEY_COMPUTER,
+        },
+};
+
+static struct resource keysc_resources[] = {
+        [0] = {
+                .name   = "KEYSC",
+                .start  = 0xe61b0000,
+                .end    = 0xe61b0098 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(71),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device keysc_device = {
+        .name           = "sh_keysc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(keysc_resources),
+        .resource       = keysc_resources,
+        .dev            = {
+                .platform_data  = &keysc_platdata,
+        },
+};
+
+/* FSI A */
+static struct sh_fsi_platform_info fsi_info = {
+        .porta_flags = SH_FSI_OUT_SLAVE_MODE    |
+                       SH_FSI_IN_SLAVE_MODE     |
+                       SH_FSI_OFMT(I2S)         |
+                       SH_FSI_IFMT(I2S),
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xEC230000,
+                .end    = 0xEC230400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(146),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xe6bd0000,
+                .end    = 0xe6bd00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(141),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = gic_spi(140),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_platdata = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195,
+        .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+};
+
+static struct platform_device mmc_device = {
+        .name           = "sh_mmcif",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh_mmcif_platdata,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+
+static struct platform_device *ag5evm_devices[] __initdata = {
+        &eth_device,
+        &keysc_device,
+        &fsi_device,
+        &mmc_device,
+};
+
+static struct map_desc ag5evm_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init ag5evm_map_io(void)
+{
+        iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
+
+        /* setup early devices and console here as well */
+        sh73a0_add_early_devices();
+        shmobile_setup_console();
+}
+
+#define PINTC_ADDR      0xe6900000
+#define PINTER0A        (PINTC_ADDR + 0xa0)
+#define PINTCR0A        (PINTC_ADDR + 0xb0)
+
+void __init ag5evm_init_irq(void)
+{
+        sh73a0_init_irq();
+
+        /* setup PINT: enable PINTA2 as active low */
+        __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
+        __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
+}
+
+static void __init ag5evm_init(void)
+{
+        sh73a0_pinmux_init();
+
+        /* enable SCIFA2 */
+        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
+        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
+        gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
+        gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
+
+        /* enable KEYSC */
+        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN1_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN2_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN3_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN4_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN5_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN6_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN7_PU, NULL);
+        gpio_request(GPIO_FN_KEYOUT0, NULL);
+        gpio_request(GPIO_FN_KEYOUT1, NULL);
+        gpio_request(GPIO_FN_KEYOUT2, NULL);
+        gpio_request(GPIO_FN_KEYOUT3, NULL);
+        gpio_request(GPIO_FN_KEYOUT4, NULL);
+        gpio_request(GPIO_FN_KEYOUT5, NULL);
+        gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
+        gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
+        gpio_request(GPIO_FN_KEYOUT8, NULL);
+        gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
+
+        /* enable I2C channel 2 and 3 */
+        gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
+        gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+        gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
+        gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
+
+        /* enable MMCIF */
+        gpio_request(GPIO_FN_MMCCLK0, NULL);
+        gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+        gpio_request(GPIO_FN_MMCD0_0, NULL);
+        gpio_request(GPIO_FN_MMCD0_1, NULL);
+        gpio_request(GPIO_FN_MMCD0_2, NULL);
+        gpio_request(GPIO_FN_MMCD0_3, NULL);
+        gpio_request(GPIO_FN_MMCD0_4, NULL);
+        gpio_request(GPIO_FN_MMCD0_5, NULL);
+        gpio_request(GPIO_FN_MMCD0_6, NULL);
+        gpio_request(GPIO_FN_MMCD0_7, NULL);
+        gpio_request(GPIO_PORT208, NULL); /* Reset */
+        gpio_direction_output(GPIO_PORT208, 1);
+
+        /* enable SMSC911X */
+        gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
+        gpio_direction_input(GPIO_PORT144);
+        gpio_request(GPIO_PORT145, NULL); /* RESET */
+        gpio_direction_output(GPIO_PORT145, 1);
+
+        /* FSI A */
+        gpio_request(GPIO_FN_FSIACK, NULL);
+        gpio_request(GPIO_FN_FSIAILR, NULL);
+        gpio_request(GPIO_FN_FSIAIBT, NULL);
+        gpio_request(GPIO_FN_FSIAISLD, NULL);
+        gpio_request(GPIO_FN_FSIAOSLD, NULL);
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Shared attribute override enable, 64K*8way */
+        l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
+#endif
+        sh73a0_add_standard_devices();
+        platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
+}
+
+static void __init ag5evm_timer_init(void)
+{
+        sh73a0_clock_init();
+        shmobile_timer.init();
+        return;
+}
+
+struct sys_timer ag5evm_timer = {
+        .init   = ag5evm_timer_init,
+};
+
+MACHINE_START(AG5EVM, "ag5evm")
+        .map_io         = ag5evm_map_io,
+        .init_irq       = ag5evm_init_irq,
+        .handle_irq     = shmobile_handle_irq_gic,
+        .init_machine   = ag5evm_init,
+        .timer          = &ag5evm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
new file mode 100644
index 000000000000..cd79d7c1ba0d
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -0,0 +1,1367 @@
+/*
+ * AP4EVB board support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/io.h>
+#include <linux/smsc911x.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_clk.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/input/sh_keysc.h>
+#include <linux/usb/r8a66597.h>
+
+#include <media/sh_mobile_ceu.h>
+#include <media/sh_mobile_csi2.h>
+#include <media/soc_camera.h>
+
+#include <sound/sh_fsi.h>
+
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
+#include <video/sh_mipi_dsi.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/sh7372.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/setup.h>
+
+/*
+ * Address      Interface               BusWidth        note
+ * ------------------------------------------------------------------
+ * 0x0000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
+ * 0x0800_0000  user area               -
+ * 0x1000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
+ * 0x1400_0000  Ether (LAN9220)         16bit
+ * 0x1600_0000  user area               -               cannot use with NAND
+ * 0x1800_0000  user area               -
+ * 0x1A00_0000  -
+ * 0x4000_0000  LPDDR2-SDRAM (POP)      32bit
+ */
+
+/*
+ * NOR Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NOR Flash ROM
+ *  bit1 | bit1  bit2 | bit1 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    Area 0
+ *  OFF  | ON     OFF | OFF  |    Area 4
+ */
+
+/*
+ * NAND Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NAND Flash ROM
+ *  bit1 | bit1  bit2 | bit2 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    FCE 0
+ *  OFF  | ON     OFF | OFF  |    FCE 1
+ */
+
+/*
+ * SMSC 9220
+ *
+ *  SW1         SMSC 9220
+ * -----------------------
+ *  ON          access disable
+ *  OFF         access enable
+ */
+
+/*
+ * LCD / IRQ / KEYSC / IrDA
+ *
+ * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
+ * LCD = 2nd LCDC (WVGA)
+ *
+ *              |               SW43                    |
+ * SW3          |       ON              |       OFF     |
+ * -------------+-----------------------+---------------+
+ * ON           | KEY / IrDA            | LCD           |
+ * OFF          | KEY / IrDA / IRQ      | IRQ           |
+ *
+ *
+ * QHD / WVGA display
+ *
+ * You can choice display type on menuconfig.
+ * Then, check above dip-switch.
+ */
+
+/*
+ * USB
+ *
+ * J7 : 1-2  MAX3355E VBUS
+ *      2-3  DC 5.0V
+ *
+ * S39: bit2: off
+ */
+
+/*
+ * FSI/FSMI
+ *
+ * SW41 :  ON : SH-Mobile AP4 Audio Mode
+ *      : OFF : Bluetooth Audio Mode
+ */
+
+/*
+ * MMC0/SDHI1 (CN7)
+ *
+ * J22 : select card voltage
+ *       1-2 pin : 1.8v
+ *       2-3 pin : 3.3v
+ *
+ *        SW1  |             SW33
+ *             | bit1 | bit2 | bit3 | bit4
+ * ------------+------+------+------+-------
+ * MMC0   OFF  |  OFF |  ON  |  ON  |  X
+ * SDHI1  OFF  |  ON  |   X  |  OFF | ON
+ *
+ * voltage lebel
+ * CN7 : 1.8v
+ * CN12: 3.3v
+ */
+
+/* MTD */
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel_ro",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x08000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+/* SMSC 9220 */
+static struct resource smc911x_resources[] = {
+        {
+                .start  = 0x14000000,
+                .end    = 0x16000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = evt2irq(0x02c0) /* IRQ6A */,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_info = {
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device smc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc911x_resources),
+        .resource       = smc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_info,
+        },
+};
+
+/*
+ * The card detect pin of the top SD/MMC slot (CN7) is active low and is
+ * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ */
+static int slot_cn7_get_cd(struct platform_device *pdev)
+{
+        if (gpio_is_valid(GPIO_PORT41))
+                return !gpio_get_value(GPIO_PORT41);
+        else
+                return -ENXIO;
+}
+
+/* SH_MMCIF */
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xE6BD0000,
+                .end    = 0xE6BD00FF,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* MMC ERR */
+                .start  = evt2irq(0x1ac0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* MMC NOR */
+                .start  = evt2irq(0x1ae0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mmcif_dma sh_mmcif_dma = {
+        .chan_priv_rx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+        },
+        .chan_priv_tx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+        },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .caps           = MMC_CAP_4_BIT_DATA |
+                          MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
+        .dma            = &sh_mmcif_dma,
+};
+
+static struct platform_device sh_mmcif_device = {
+        .name           = "sh_mmcif",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh_mmcif_plat,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+};
+
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "SDHI0",
+                .start  = 0xe6850000,
+                .end    = 0xe68501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e00) /* SDHI0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &sdhi0_info,
+        },
+};
+
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+        .tmio_ocr_mask  = MMC_VDD_165_195,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
+};
+
+static struct resource sdhi1_resources[] = {
+        [0] = {
+                .name   = "SDHI1",
+                .start  = 0xe6860000,
+                .end    = 0xe68601ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e80),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi1_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi1_resources),
+        .resource       = sdhi1_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &sdhi1_info,
+        },
+};
+
+/* USB1 */
+static void usb1_host_port_power(int port, int power)
+{
+        if (!power) /* only power-on supported for now */
+                return;
+
+        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
+        __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+}
+
+static struct r8a66597_platdata usb1_host_data = {
+        .on_chip        = 1,
+        .port_power     = usb1_host_port_power,
+};
+
+static struct resource usb1_host_resources[] = {
+        [0] = {
+                .name   = "USBHS",
+                .start  = 0xE68B0000,
+                .end    = 0xE68B00E6 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb1_host_device = {
+        .name   = "r8a66597_hcd",
+        .id     = 1,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usb1_host_data,
+        },
+        .num_resources  = ARRAY_SIZE(usb1_host_resources),
+        .resource       = usb1_host_resources,
+};
+
+const static struct fb_videomode ap4evb_lcdc_modes[] = {
+        {
+#ifdef CONFIG_AP4EVB_QHD
+                .name           = "R63302(QHD)",
+                .xres           = 544,
+                .yres           = 961,
+                .left_margin    = 72,
+                .right_margin   = 600,
+                .hsync_len      = 16,
+                .upper_margin   = 8,
+                .lower_margin   = 8,
+                .vsync_len      = 2,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+#else
+                .name           = "WVGA Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0,
+#endif
+        },
+};
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .lcd_cfg = ap4evb_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
+        }
+};
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000, /* P4-only space */
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev    = {
+                .platform_data  = &lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+/*
+ * QHD display
+ */
+#ifdef CONFIG_AP4EVB_QHD
+
+/* KEYSC (Needs SW43 set to ON) */
+static struct sh_keysc_info keysc_info = {
+        .mode           = SH_KEYSC_MODE_1,
+        .scan_timing    = 3,
+        .delay          = 2500,
+        .keycodes = {
+                KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
+                KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
+                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
+                KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
+                KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
+        },
+};
+
+static struct resource keysc_resources[] = {
+        [0] = {
+                .name   = "KEYSC",
+                .start  = 0xe61b0000,
+                .end    = 0xe61b0063,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0be0), /* KEYSC_KEY */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device keysc_device = {
+        .name           = "sh_keysc",
+        .id             = 0, /* "keysc0" clock */
+        .num_resources  = ARRAY_SIZE(keysc_resources),
+        .resource       = keysc_resources,
+        .dev    = {
+                .platform_data  = &keysc_info,
+        },
+};
+
+/* MIPI-DSI */
+static struct resource mipidsi0_resources[] = {
+        [0] = {
+                .start  = 0xffc60000,
+                .end    = 0xffc63073,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffc68000,
+                .end    = 0xffc680ef,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct sh_mipi_dsi_info mipidsi0_info = {
+        .data_format    = MIPI_RGB888,
+        .lcd_chan       = &lcdc_info.ch[0],
+        .vsynw_offset   = 17,
+};
+
+static struct platform_device mipidsi0_device = {
+        .name           = "sh-mipi-dsi",
+        .num_resources  = ARRAY_SIZE(mipidsi0_resources),
+        .resource       = mipidsi0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &mipidsi0_info,
+        },
+};
+
+static struct platform_device *qhd_devices[] __initdata = {
+        &mipidsi0_device,
+        &keysc_device,
+};
+#endif /* CONFIG_AP4EVB_QHD */
+
+/* FSI */
+#define IRQ_FSI         evt2irq(0x1840)
+static int __fsi_set_rate(struct clk *clk, long rate, int enable)
+{
+        int ret = 0;
+
+        if (rate <= 0)
+                return ret;
+
+        if (enable) {
+                ret = clk_set_rate(clk, rate);
+                if (0 == ret)
+                        ret = clk_enable(clk);
+        } else {
+                clk_disable(clk);
+        }
+
+        return ret;
+}
+
+static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
+{
+        return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
+}
+
+static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
+{
+        struct clk *fsia_ick;
+        struct clk *fsiack;
+        int ret = -EIO;
+
+        fsia_ick = clk_get(dev, "icka");
+        if (IS_ERR(fsia_ick))
+                return PTR_ERR(fsia_ick);
+
+        /*
+         * FSIACK is connected to AK4642,
+         * and use external clock pin from it.
+         * it is parent of fsia_ick now.
+         */
+        fsiack = clk_get_parent(fsia_ick);
+        if (!fsiack)
+                goto fsia_ick_out;
+
+        /*
+         * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
+         *
+         ** FIXME **
+         * Because the freq_table of external clk (fsiack) are all 0,
+         * the return value of clk_round_rate became 0.
+         * So, it use __fsi_set_rate here.
+         */
+        ret = __fsi_set_rate(fsiack, rate, enable);
+        if (ret < 0)
+                goto fsiack_out;
+
+        ret = __fsi_set_round_rate(fsia_ick, rate, enable);
+        if ((ret < 0) && enable)
+                __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
+
+fsiack_out:
+        clk_put(fsiack);
+
+fsia_ick_out:
+        clk_put(fsia_ick);
+
+        return 0;
+}
+
+static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
+{
+        struct clk *fsib_clk;
+        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        long fsib_rate = 0;
+        long fdiv_rate = 0;
+        int ackmd_bpfmd;
+        int ret;
+
+        switch (rate) {
+        case 44100:
+                fsib_rate       = rate * 256;
+                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        case 48000:
+                fsib_rate       = 85428000; /* around 48kHz x 256 x 7 */
+                fdiv_rate       = rate * 256;
+                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        default:
+                pr_err("unsupported rate in FSI2 port B\n");
+                return -EINVAL;
+        }
+
+        /* FSI B setting */
+        fsib_clk = clk_get(dev, "ickb");
+        if (IS_ERR(fsib_clk))
+                return -EIO;
+
+        ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
+        if (ret < 0)
+                goto fsi_set_rate_end;
+
+        /* FSI DIV setting */
+        ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
+        if (ret < 0) {
+                /* disable FSI B */
+                if (enable)
+                        __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
+                goto fsi_set_rate_end;
+        }
+
+        ret = ackmd_bpfmd;
+
+fsi_set_rate_end:
+        clk_put(fsib_clk);
+        return ret;
+}
+
+static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
+{
+        int ret;
+
+        if (is_porta)
+                ret = fsi_ak4642_set_rate(dev, rate, enable);
+        else
+                ret = fsi_hdmi_set_rate(dev, rate, enable);
+
+        return ret;
+}
+
+static struct sh_fsi_platform_info fsi_info = {
+        .porta_flags = SH_FSI_BRS_INV |
+                       SH_FSI_OUT_SLAVE_MODE |
+                       SH_FSI_IN_SLAVE_MODE |
+                       SH_FSI_OFMT(PCM) |
+                       SH_FSI_IFMT(PCM),
+
+        .portb_flags = SH_FSI_BRS_INV |
+                       SH_FSI_BRM_INV |
+                       SH_FSI_LRS_INV |
+                       SH_FSI_OFMT(SPDIF),
+        .set_rate = fsi_set_rate,
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xFE3C0000,
+                .end    = 0xFE3C0400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FSI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
+        .clock_source = LCDC_CLK_EXTERNAL,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .interface_type = RGB24,
+                .clock_divider = 1,
+                .flags = LCDC_FLAGS_DWPOL,
+        }
+};
+
+static struct resource lcdc1_resources[] = {
+        [0] = {
+                .name   = "LCDC1",
+                .start  = 0xfe944000,
+                .end    = 0xfe947fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x1780),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc1_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc1_resources),
+        .resource       = lcdc1_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &sh_mobile_lcdc1_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+                                unsigned long *parent_freq);
+
+
+static struct sh_mobile_hdmi_info hdmi_info = {
+        .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
+        .lcd_dev = &lcdc1_device.dev,
+        .flags = HDMI_SND_SRC_SPDIF,
+        .clk_optimize_parent = ap4evb_clk_optimize,
+};
+
+static struct resource hdmi_resources[] = {
+        [0] = {
+                .name   = "HDMI",
+                .start  = 0xe6be0000,
+                .end    = 0xe6be00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
+                .start  = evt2irq(0x17e0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_device = {
+        .name           = "sh-mobile-hdmi",
+        .num_resources  = ARRAY_SIZE(hdmi_resources),
+        .resource       = hdmi_resources,
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &hdmi_info,
+        },
+};
+
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+                                unsigned long *parent_freq)
+{
+        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+        long error;
+
+        if (IS_ERR(hdmi_ick)) {
+                int ret = PTR_ERR(hdmi_ick);
+                pr_err("Cannot get HDMI ICK: %d\n", ret);
+                return ret;
+        }
+
+        error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
+
+        clk_put(hdmi_ick);
+
+        return error;
+}
+
+static struct gpio_led ap4evb_leds[] = {
+        {
+                .name                   = "led4",
+                .gpio                   = GPIO_PORT185,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name                   = "led2",
+                .gpio                   = GPIO_PORT186,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name                   = "led3",
+                .gpio                   = GPIO_PORT187,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name                   = "led1",
+                .gpio                   = GPIO_PORT188,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }
+};
+
+static struct gpio_led_platform_data ap4evb_leds_pdata = {
+        .num_leds = ARRAY_SIZE(ap4evb_leds),
+        .leds = ap4evb_leds,
+};
+
+static struct platform_device leds_device = {
+        .name = "leds-gpio",
+        .id = 0,
+        .dev = {
+                .platform_data  = &ap4evb_leds_pdata,
+        },
+};
+
+static struct i2c_board_info imx074_info = {
+        I2C_BOARD_INFO("imx074", 0x1a),
+};
+
+struct soc_camera_link imx074_link = {
+        .bus_id         = 0,
+        .board_info     = &imx074_info,
+        .i2c_adapter_id = 0,
+        .module_name    = "imx074",
+};
+
+static struct platform_device ap4evb_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &imx074_link,
+        },
+};
+
+static struct sh_csi2_client_config csi2_clients[] = {
+        {
+                .phy            = SH_CSI2_PHY_MAIN,
+                .lanes          = 3,
+                .channel        = 0,
+                .pdev           = &ap4evb_camera,
+        },
+};
+
+static struct sh_csi2_pdata csi2_info = {
+        .type           = SH_CSI2C,
+        .clients        = csi2_clients,
+        .num_clients    = ARRAY_SIZE(csi2_clients),
+        .flags          = SH_CSI2_ECC | SH_CSI2_CRC,
+};
+
+static struct resource csi2_resources[] = {
+        [0] = {
+                .name   = "CSI2",
+                .start  = 0xffc90000,
+                .end    = 0xffc90fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x17a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device csi2_device = {
+        .name   = "sh-mobile-csi2",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(csi2_resources),
+        .resource       = csi2_resources,
+        .dev    = {
+                .platform_data = &csi2_info,
+        },
+};
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+        .csi2_dev = &csi2_device.dev,
+};
+
+static struct resource ceu_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x880),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 0, /* "ceu0" clock */
+        .num_resources  = ARRAY_SIZE(ceu_resources),
+        .resource       = ceu_resources,
+        .dev    = {
+                .platform_data  = &sh_mobile_ceu_info,
+        },
+};
+
+static struct platform_device *ap4evb_devices[] __initdata = {
+        &leds_device,
+        &nor_flash_device,
+        &smc911x_device,
+        &sdhi0_device,
+        &sdhi1_device,
+        &usb1_host_device,
+        &fsi_device,
+        &sh_mmcif_device,
+        &lcdc1_device,
+        &lcdc_device,
+        &hdmi_device,
+        &csi2_device,
+        &ceu_device,
+        &ap4evb_camera,
+};
+
+static int __init hdmi_init_pm_clock(void)
+{
+        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+        int ret;
+        long rate;
+
+        if (IS_ERR(hdmi_ick)) {
+                ret = PTR_ERR(hdmi_ick);
+                pr_err("Cannot get HDMI ICK: %d\n", ret);
+                goto out;
+        }
+
+        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
+        if (ret < 0) {
+                pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
+                goto out;
+        }
+
+        pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
+
+        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
+        if (rate < 0) {
+                pr_err("Cannot get suitable rate: %ld\n", rate);
+                ret = rate;
+                goto out;
+        }
+
+        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
+        if (ret < 0) {
+                pr_err("Cannot set rate %ld: %d\n", rate, ret);
+                goto out;
+        }
+
+        ret = clk_enable(&sh7372_pllc2_clk);
+        if (ret < 0) {
+                pr_err("Cannot enable pllc2 clock\n");
+                goto out;
+        }
+        pr_debug("PLLC2 set frequency %lu\n", rate);
+
+        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
+        if (ret < 0) {
+                pr_err("Cannot set HDMI parent: %d\n", ret);
+                goto out;
+        }
+
+out:
+        if (!IS_ERR(hdmi_ick))
+                clk_put(hdmi_ick);
+        return ret;
+}
+
+device_initcall(hdmi_init_pm_clock);
+
+static int __init fsi_init_pm_clock(void)
+{
+        struct clk *fsia_ick;
+        int ret;
+
+        fsia_ick = clk_get(&fsi_device.dev, "icka");
+        if (IS_ERR(fsia_ick)) {
+                ret = PTR_ERR(fsia_ick);
+                pr_err("Cannot get FSI ICK: %d\n", ret);
+                return ret;
+        }
+
+        ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
+        if (ret < 0)
+                pr_err("Cannot set FSI-A parent: %d\n", ret);
+
+        clk_put(fsia_ick);
+
+        return ret;
+}
+device_initcall(fsi_init_pm_clock);
+
+/*
+ * FIXME !!
+ *
+ * gpio_no_direction
+ * are quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_no_direction(u32 addr)
+{
+        __raw_writeb(0x00, addr);
+}
+
+/* TouchScreen */
+#ifdef CONFIG_AP4EVB_QHD
+# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
+# define GPIO_TSC_PORT  GPIO_PORT123
+#else /* WVGA */
+# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
+# define GPIO_TSC_PORT  GPIO_PORT40
+#endif
+
+#define IRQ28   evt2irq(0x3380) /* IRQ28A */
+#define IRQ7    evt2irq(0x02e0) /* IRQ7A */
+static int ts_get_pendown_state(void)
+{
+        int val;
+
+        gpio_free(GPIO_TSC_IRQ);
+
+        gpio_request(GPIO_TSC_PORT, NULL);
+
+        gpio_direction_input(GPIO_TSC_PORT);
+
+        val = gpio_get_value(GPIO_TSC_PORT);
+
+        gpio_request(GPIO_TSC_IRQ, NULL);
+
+        return !val;
+}
+
+static int ts_init(void)
+{
+        gpio_request(GPIO_TSC_IRQ, NULL);
+
+        return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+        .model                  = 2007,
+        .x_plate_ohms           = 180,
+        .get_pendown_state      = ts_get_pendown_state,
+        .init_platform_hw       = ts_init,
+};
+
+static struct i2c_board_info tsc_device = {
+        I2C_BOARD_INFO("tsc2007", 0x48),
+        .type           = "tsc2007",
+        .platform_data  = &tsc2007_info,
+        /*.irq is selected on ap4evb_init */
+};
+
+/* I2C */
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("ak4643", 0x13),
+        },
+};
+
+static struct i2c_board_info i2c1_devices[] = {
+        {
+                I2C_BOARD_INFO("r2025sd", 0x32),
+        },
+};
+
+static struct map_desc ap4evb_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init ap4evb_map_io(void)
+{
+        iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
+
+        /* setup early devices and console here as well */
+        sh7372_add_early_devices();
+        shmobile_setup_console();
+}
+
+#define GPIO_PORT9CR    0xE6051009
+#define GPIO_PORT10CR   0xE605100A
+#define USCCR1          0xE6058144
+static void __init ap4evb_init(void)
+{
+        u32 srcr4;
+        struct clk *clk;
+
+        sh7372_pinmux_init();
+
+        /* enable SCIFA0 */
+        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
+        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
+
+        /* enable SMSC911X */
+        gpio_request(GPIO_FN_CS5A,      NULL);
+        gpio_request(GPIO_FN_IRQ6_39,   NULL);
+
+        /* enable Debug switch (S6) */
+        gpio_request(GPIO_PORT32, NULL);
+        gpio_request(GPIO_PORT33, NULL);
+        gpio_request(GPIO_PORT34, NULL);
+        gpio_request(GPIO_PORT35, NULL);
+        gpio_direction_input(GPIO_PORT32);
+        gpio_direction_input(GPIO_PORT33);
+        gpio_direction_input(GPIO_PORT34);
+        gpio_direction_input(GPIO_PORT35);
+        gpio_export(GPIO_PORT32, 0);
+        gpio_export(GPIO_PORT33, 0);
+        gpio_export(GPIO_PORT34, 0);
+        gpio_export(GPIO_PORT35, 0);
+
+        /* SDHI0 */
+        gpio_request(GPIO_FN_SDHICD0, NULL);
+        gpio_request(GPIO_FN_SDHIWP0, NULL);
+        gpio_request(GPIO_FN_SDHICMD0, NULL);
+        gpio_request(GPIO_FN_SDHICLK0, NULL);
+        gpio_request(GPIO_FN_SDHID0_3, NULL);
+        gpio_request(GPIO_FN_SDHID0_2, NULL);
+        gpio_request(GPIO_FN_SDHID0_1, NULL);
+        gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+        /* SDHI1 */
+        gpio_request(GPIO_FN_SDHICMD1, NULL);
+        gpio_request(GPIO_FN_SDHICLK1, NULL);
+        gpio_request(GPIO_FN_SDHID1_3, NULL);
+        gpio_request(GPIO_FN_SDHID1_2, NULL);
+        gpio_request(GPIO_FN_SDHID1_1, NULL);
+        gpio_request(GPIO_FN_SDHID1_0, NULL);
+
+        /* MMCIF */
+        gpio_request(GPIO_FN_MMCD0_0, NULL);
+        gpio_request(GPIO_FN_MMCD0_1, NULL);
+        gpio_request(GPIO_FN_MMCD0_2, NULL);
+        gpio_request(GPIO_FN_MMCD0_3, NULL);
+        gpio_request(GPIO_FN_MMCD0_4, NULL);
+        gpio_request(GPIO_FN_MMCD0_5, NULL);
+        gpio_request(GPIO_FN_MMCD0_6, NULL);
+        gpio_request(GPIO_FN_MMCD0_7, NULL);
+        gpio_request(GPIO_FN_MMCCMD0, NULL);
+        gpio_request(GPIO_FN_MMCCLK0, NULL);
+
+        /* USB enable */
+        gpio_request(GPIO_FN_VBUS0_1,    NULL);
+        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
+        gpio_request(GPIO_FN_PWEN_1_115, NULL);
+        gpio_request(GPIO_FN_OVCN_1_114, NULL);
+        gpio_request(GPIO_FN_EXTLP_1,    NULL);
+        gpio_request(GPIO_FN_OVCN2_1,    NULL);
+
+        /* setup USB phy */
+        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+
+        /* enable FSI2 port A (ak4643) */
+        gpio_request(GPIO_FN_FSIAIBT,   NULL);
+        gpio_request(GPIO_FN_FSIAILR,   NULL);
+        gpio_request(GPIO_FN_FSIAISLD,  NULL);
+        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        gpio_request(GPIO_PORT161,      NULL);
+        gpio_direction_output(GPIO_PORT161, 0); /* slave */
+
+        gpio_request(GPIO_PORT9, NULL);
+        gpio_request(GPIO_PORT10, NULL);
+        gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+        gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+
+        /* card detect pin for MMC slot (CN7) */
+        gpio_request(GPIO_PORT41, NULL);
+        gpio_direction_input(GPIO_PORT41);
+
+        /* setup FSI2 port B (HDMI) */
+        gpio_request(GPIO_FN_FSIBCK, NULL);
+        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
+
+        /* set SPU2 clock to 119.6 MHz */
+        clk = clk_get(NULL, "spu_clk");
+        if (!IS_ERR(clk)) {
+                clk_set_rate(clk, clk_round_rate(clk, 119600000));
+                clk_put(clk);
+        }
+
+        /*
+         * set irq priority, to avoid sound chopping
+         * when NFS rootfs is used
+         *  FSI(3) > SMSC911X(2)
+         */
+        intc_set_priority(IRQ_FSI, 3);
+
+        i2c_register_board_info(0, i2c0_devices,
+                                ARRAY_SIZE(i2c0_devices));
+
+        i2c_register_board_info(1, i2c1_devices,
+                                ARRAY_SIZE(i2c1_devices));
+
+#ifdef CONFIG_AP4EVB_QHD
+
+        /*
+         * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
+         * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
+         */
+
+        /* enable KEYSC */
+        gpio_request(GPIO_FN_KEYOUT0, NULL);
+        gpio_request(GPIO_FN_KEYOUT1, NULL);
+        gpio_request(GPIO_FN_KEYOUT2, NULL);
+        gpio_request(GPIO_FN_KEYOUT3, NULL);
+        gpio_request(GPIO_FN_KEYOUT4, NULL);
+        gpio_request(GPIO_FN_KEYIN0_136, NULL);
+        gpio_request(GPIO_FN_KEYIN1_135, NULL);
+        gpio_request(GPIO_FN_KEYIN2_134, NULL);
+        gpio_request(GPIO_FN_KEYIN3_133, NULL);
+        gpio_request(GPIO_FN_KEYIN4,     NULL);
+
+        /* enable TouchScreen */
+        set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
+
+        tsc_device.irq = IRQ28;
+        i2c_register_board_info(1, &tsc_device, 1);
+
+        /* LCDC0 */
+        lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
+        lcdc_info.ch[0].interface_type          = RGB24;
+        lcdc_info.ch[0].clock_divider           = 1;
+        lcdc_info.ch[0].flags                   = LCDC_FLAGS_DWPOL;
+        lcdc_info.ch[0].lcd_size_cfg.width      = 44;
+        lcdc_info.ch[0].lcd_size_cfg.height     = 79;
+
+        platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
+
+#else
+        /*
+         * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
+         * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
+         */
+
+        gpio_request(GPIO_FN_LCDD17,   NULL);
+        gpio_request(GPIO_FN_LCDD16,   NULL);
+        gpio_request(GPIO_FN_LCDD15,   NULL);
+        gpio_request(GPIO_FN_LCDD14,   NULL);
+        gpio_request(GPIO_FN_LCDD13,   NULL);
+        gpio_request(GPIO_FN_LCDD12,   NULL);
+        gpio_request(GPIO_FN_LCDD11,   NULL);
+        gpio_request(GPIO_FN_LCDD10,   NULL);
+        gpio_request(GPIO_FN_LCDD9,    NULL);
+        gpio_request(GPIO_FN_LCDD8,    NULL);
+        gpio_request(GPIO_FN_LCDD7,    NULL);
+        gpio_request(GPIO_FN_LCDD6,    NULL);
+        gpio_request(GPIO_FN_LCDD5,    NULL);
+        gpio_request(GPIO_FN_LCDD4,    NULL);
+        gpio_request(GPIO_FN_LCDD3,    NULL);
+        gpio_request(GPIO_FN_LCDD2,    NULL);
+        gpio_request(GPIO_FN_LCDD1,    NULL);
+        gpio_request(GPIO_FN_LCDD0,    NULL);
+        gpio_request(GPIO_FN_LCDDISP,  NULL);
+        gpio_request(GPIO_FN_LCDDCK,   NULL);
+
+        gpio_request(GPIO_PORT189, NULL); /* backlight */
+        gpio_direction_output(GPIO_PORT189, 1);
+
+        gpio_request(GPIO_PORT151, NULL); /* LCDDON */
+        gpio_direction_output(GPIO_PORT151, 1);
+
+        lcdc_info.clock_source                  = LCDC_CLK_BUS;
+        lcdc_info.ch[0].interface_type          = RGB18;
+        lcdc_info.ch[0].clock_divider           = 2;
+        lcdc_info.ch[0].flags                   = 0;
+        lcdc_info.ch[0].lcd_size_cfg.width      = 152;
+        lcdc_info.ch[0].lcd_size_cfg.height     = 91;
+
+        /* enable TouchScreen */
+        set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
+
+        tsc_device.irq = IRQ7;
+        i2c_register_board_info(0, &tsc_device, 1);
+#endif /* CONFIG_AP4EVB_QHD */
+
+        /* CEU */
+
+        /*
+         * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
+         * becomes available
+         */
+
+        /* MIPI-CSI stuff */
+        gpio_request(GPIO_FN_VIO_CKO, NULL);
+
+        clk = clk_get(NULL, "vck1_clk");
+        if (!IS_ERR(clk)) {
+                clk_set_rate(clk, clk_round_rate(clk, 13000000));
+                clk_enable(clk);
+                clk_put(clk);
+        }
+
+        sh7372_add_standard_devices();
+
+        /* HDMI */
+        gpio_request(GPIO_FN_HDMI_HPD, NULL);
+        gpio_request(GPIO_FN_HDMI_CEC, NULL);
+
+        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
+#define SRCR4 0xe61580bc
+        srcr4 = __raw_readl(SRCR4);
+        __raw_writel(srcr4 | (1 << 13), SRCR4);
+        udelay(50);
+        __raw_writel(srcr4 & ~(1 << 13), SRCR4);
+
+        platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
+}
+
+static void __init ap4evb_timer_init(void)
+{
+        sh7372_clock_init();
+        shmobile_timer.init();
+
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+}
+
+static struct sys_timer ap4evb_timer = {
+        .init           = ap4evb_timer_init,
+};
+
+MACHINE_START(AP4EVB, "ap4evb")
+        .map_io         = ap4evb_map_io,
+        .init_irq       = sh7372_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = ap4evb_init,
+        .timer          = &ap4evb_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
new file mode 100644
index 000000000000..686b304a7708
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -0,0 +1,373 @@
+/*
+ * G3EVM board support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/sh_flctl.h>
+#include <linux/usb/r8a66597.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/input/sh_keysc.h>
+#include <mach/sh7367.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+/*
+ * IrDA
+ *
+ * S67: 5bit : ON  power
+ *    : 6bit : ON  remote control
+ *             OFF IrDA
+ */
+
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "kernel_ro",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x08000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+/* USBHS */
+static void usb_host_port_power(int port, int power)
+{
+        if (!power) /* only power-on supported for now */
+                return;
+
+        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
+        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+}
+
+static struct r8a66597_platdata usb_host_data = {
+        .on_chip = 1,
+        .port_power = usb_host_port_power,
+};
+
+static struct resource usb_host_resources[] = {
+        [0] = {
+                .name   = "USBHS",
+                .start  = 0xe6890000,
+                .end    = 0xe68900e5,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0xa20), /* USBHS_USHI0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_host_device = {
+        .name           = "r8a66597_hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data          = &usb_host_data,
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(usb_host_resources),
+        .resource       = usb_host_resources,
+};
+
+/* KEYSC */
+static struct sh_keysc_info keysc_info = {
+        .mode           = SH_KEYSC_MODE_5,
+        .scan_timing    = 3,
+        .delay          = 100,
+        .keycodes = {
+                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
+                KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
+                KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
+                KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
+                KEY_WAKEUP, KEY_COFFEE, KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
+                KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, KEY_STOP, KEY_COMPUTER,
+        },
+};
+
+static struct resource keysc_resources[] = {
+        [0] = {
+                .name   = "KEYSC",
+                .start  = 0xe61b0000,
+                .end    = 0xe61b000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0xbe0), /* KEYSC_KEY */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device keysc_device = {
+        .name           = "sh_keysc",
+        .num_resources  = ARRAY_SIZE(keysc_resources),
+        .resource       = keysc_resources,
+        .dev    = {
+                .platform_data  = &keysc_info,
+        },
+};
+
+static struct mtd_partition nand_partition_info[] = {
+        {
+                .name   = "system",
+                .offset = 0,
+                .size   = 64 * 1024 * 1024,
+        },
+        {
+                .name   = "userdata",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = 128 * 1024 * 1024,
+        },
+        {
+                .name   = "cache",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = 64 * 1024 * 1024,
+        },
+};
+
+static struct resource nand_flash_resources[] = {
+        [0] = {
+                .start  = 0xe6a30000,
+                .end    = 0xe6a3009b,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct sh_flctl_platform_data nand_flash_data = {
+        .parts          = nand_partition_info,
+        .nr_parts       = ARRAY_SIZE(nand_partition_info),
+        .flcmncr_val    = QTSEL_E | FCKSEL_E | TYPESEL_SET | NANWF_E
+                        | SHBUSSEL | SEL_16BIT,
+};
+
+static struct platform_device nand_flash_device = {
+        .name           = "sh_flctl",
+        .resource       = nand_flash_resources,
+        .num_resources  = ARRAY_SIZE(nand_flash_resources),
+        .dev            = {
+                .platform_data = &nand_flash_data,
+        },
+};
+
+static struct resource irda_resources[] = {
+        [0] = {
+                .start  = 0xE6D00000,
+                .end    = 0xE6D01FD4 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x480), /* IRDA */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device irda_device = {
+        .name           = "sh_irda",
+        .id             = -1,
+        .resource       = irda_resources,
+        .num_resources  = ARRAY_SIZE(irda_resources),
+};
+
+static struct platform_device *g3evm_devices[] __initdata = {
+        &nor_flash_device,
+        &usb_host_device,
+        &keysc_device,
+        &nand_flash_device,
+        &irda_device,
+};
+
+static struct map_desc g3evm_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init g3evm_map_io(void)
+{
+        iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
+
+        /* setup early devices and console here as well */
+        sh7367_add_early_devices();
+        shmobile_setup_console();
+}
+
+static void __init g3evm_init(void)
+{
+        sh7367_pinmux_init();
+
+        /* Lit DS4 LED */
+        gpio_request(GPIO_PORT22, NULL);
+        gpio_direction_output(GPIO_PORT22, 1);
+        gpio_export(GPIO_PORT22, 0);
+
+        /* Lit DS8 LED */
+        gpio_request(GPIO_PORT23, NULL);
+        gpio_direction_output(GPIO_PORT23, 1);
+        gpio_export(GPIO_PORT23, 0);
+
+        /* Lit DS3 LED */
+        gpio_request(GPIO_PORT24, NULL);
+        gpio_direction_output(GPIO_PORT24, 1);
+        gpio_export(GPIO_PORT24, 0);
+
+        /* SCIFA1 */
+        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
+        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
+        gpio_request(GPIO_FN_SCIFA1_CTS, NULL);
+        gpio_request(GPIO_FN_SCIFA1_RTS, NULL);
+
+        /* USBHS */
+        gpio_request(GPIO_FN_VBUS0, NULL);
+        gpio_request(GPIO_FN_PWEN, NULL);
+        gpio_request(GPIO_FN_OVCN, NULL);
+        gpio_request(GPIO_FN_OVCN2, NULL);
+        gpio_request(GPIO_FN_EXTLP, NULL);
+        gpio_request(GPIO_FN_IDIN, NULL);
+
+        /* setup USB phy */
+        __raw_writew(0x0300, 0xe605810a);       /* USBCR1 */
+        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
+        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
+        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+
+        /* KEYSC @ CN7 */
+        gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
+        gpio_request(GPIO_FN_PORT43_KEYOUT1, NULL);
+        gpio_request(GPIO_FN_PORT44_KEYOUT2, NULL);
+        gpio_request(GPIO_FN_PORT45_KEYOUT3, NULL);
+        gpio_request(GPIO_FN_PORT46_KEYOUT4, NULL);
+        gpio_request(GPIO_FN_PORT47_KEYOUT5, NULL);
+        gpio_request(GPIO_FN_PORT48_KEYIN0_PU, NULL);
+        gpio_request(GPIO_FN_PORT49_KEYIN1_PU, NULL);
+        gpio_request(GPIO_FN_PORT50_KEYIN2_PU, NULL);
+        gpio_request(GPIO_FN_PORT55_KEYIN3_PU, NULL);
+        gpio_request(GPIO_FN_PORT56_KEYIN4_PU, NULL);
+        gpio_request(GPIO_FN_PORT57_KEYIN5_PU, NULL);
+        gpio_request(GPIO_FN_PORT58_KEYIN6_PU, NULL);
+
+        /* FLCTL */
+        gpio_request(GPIO_FN_FCE0, NULL);
+        gpio_request(GPIO_FN_D0_ED0_NAF0, NULL);
+        gpio_request(GPIO_FN_D1_ED1_NAF1, NULL);
+        gpio_request(GPIO_FN_D2_ED2_NAF2, NULL);
+        gpio_request(GPIO_FN_D3_ED3_NAF3, NULL);
+        gpio_request(GPIO_FN_D4_ED4_NAF4, NULL);
+        gpio_request(GPIO_FN_D5_ED5_NAF5, NULL);
+        gpio_request(GPIO_FN_D6_ED6_NAF6, NULL);
+        gpio_request(GPIO_FN_D7_ED7_NAF7, NULL);
+        gpio_request(GPIO_FN_D8_ED8_NAF8, NULL);
+        gpio_request(GPIO_FN_D9_ED9_NAF9, NULL);
+        gpio_request(GPIO_FN_D10_ED10_NAF10, NULL);
+        gpio_request(GPIO_FN_D11_ED11_NAF11, NULL);
+        gpio_request(GPIO_FN_D12_ED12_NAF12, NULL);
+        gpio_request(GPIO_FN_D13_ED13_NAF13, NULL);
+        gpio_request(GPIO_FN_D14_ED14_NAF14, NULL);
+        gpio_request(GPIO_FN_D15_ED15_NAF15, NULL);
+        gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
+        gpio_request(GPIO_FN_FRB, NULL);
+        /* FOE, FCDE, FSC on dedicated pins */
+        __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
+
+        /* IrDA */
+        gpio_request(GPIO_FN_IRDA_OUT, NULL);
+        gpio_request(GPIO_FN_IRDA_IN, NULL);
+        gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
+        set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
+
+        sh7367_add_standard_devices();
+
+        platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
+}
+
+static void __init g3evm_timer_init(void)
+{
+        sh7367_clock_init();
+        shmobile_timer.init();
+}
+
+static struct sys_timer g3evm_timer = {
+        .init           = g3evm_timer_init,
+};
+
+MACHINE_START(G3EVM, "g3evm")
+        .map_io         = g3evm_map_io,
+        .init_irq       = sh7367_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = g3evm_init,
+        .timer          = &g3evm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
new file mode 100644
index 000000000000..c13f01280b7e
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -0,0 +1,400 @@
+/*
+ * G4EVM board support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/usb/r8a66597.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <linux/input/sh_keysc.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/gpio.h>
+#include <mach/sh7377.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+/*
+ * SDHI
+ *
+ * SDHI0 : card detection is possible
+ * SDHI1 : card detection is impossible
+ *
+ * [G4-MAIN-BOARD]
+ * JP74 : short         # DBG_2V8A    for SDHI0
+ * JP75 : NC            # DBG_3V3A    for SDHI0
+ * JP76 : NC            # DBG_3V3A_SD for SDHI0
+ * JP77 : NC            # 3V3A_SDIO   for SDHI1
+ * JP78 : short         # DBG_2V8A    for SDHI1
+ * JP79 : NC            # DBG_3V3A    for SDHI1
+ * JP80 : NC            # DBG_3V3A_SD for SDHI1
+ *
+ * [G4-CORE-BOARD]
+ * S32 : all off        # to dissever from G3-CORE_DBG board
+ * S33 : all off        # to dissever from G3-CORE_DBG board
+ *
+ * [G3-CORE_DBG-BOARD]
+ * S1  : all off        # to dissever from G3-CORE_DBG board
+ * S3  : all off        # to dissever from G3-CORE_DBG board
+ * S4  : all off        # to dissever from G3-CORE_DBG board
+ */
+
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "kernel_ro",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x08000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+/* USBHS */
+static void usb_host_port_power(int port, int power)
+{
+        if (!power) /* only power-on supported for now */
+                return;
+
+        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
+        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+}
+
+static struct r8a66597_platdata usb_host_data = {
+        .on_chip = 1,
+        .port_power = usb_host_port_power,
+};
+
+static struct resource usb_host_resources[] = {
+        [0] = {
+                .name   = "USBHS",
+                .start  = 0xe6890000,
+                .end    = 0xe68900e5,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0a20), /* USBHS_USHI0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_host_device = {
+        .name           = "r8a66597_hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data          = &usb_host_data,
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(usb_host_resources),
+        .resource       = usb_host_resources,
+};
+
+/* KEYSC */
+static struct sh_keysc_info keysc_info = {
+        .mode           = SH_KEYSC_MODE_5,
+        .scan_timing    = 3,
+        .delay          = 100,
+        .keycodes = {
+                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
+                KEY_G, KEY_H, KEY_I, KEY_J, KEY_K, KEY_L,
+                KEY_M, KEY_N, KEY_U, KEY_P, KEY_Q, KEY_R,
+                KEY_S, KEY_T, KEY_U, KEY_V, KEY_W, KEY_X,
+                KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE,
+                KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
+                KEY_6, KEY_7, KEY_8, KEY_9, KEY_STOP, KEY_COMPUTER,
+        },
+};
+
+static struct resource keysc_resources[] = {
+        [0] = {
+                .name   = "KEYSC",
+                .start  = 0xe61b0000,
+                .end    = 0xe61b000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0be0), /* KEYSC_KEY */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device keysc_device = {
+        .name           = "sh_keysc",
+        .id             = 0, /* keysc0 clock */
+        .num_resources  = ARRAY_SIZE(keysc_resources),
+        .resource       = keysc_resources,
+        .dev    = {
+                .platform_data  = &keysc_info,
+        },
+};
+
+/* SDHI */
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "SDHI0",
+                .start  = 0xe6d50000,
+                .end    = 0xe6d501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e00), /* SDHI0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+        .id             = 0,
+};
+
+static struct resource sdhi1_resources[] = {
+        [0] = {
+                .name   = "SDHI1",
+                .start  = 0xe6d60000,
+                .end    = 0xe6d601ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e80), /* SDHI1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi1_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi1_resources),
+        .resource       = sdhi1_resources,
+        .id             = 1,
+};
+
+static struct platform_device *g4evm_devices[] __initdata = {
+        &nor_flash_device,
+        &usb_host_device,
+        &keysc_device,
+        &sdhi0_device,
+        &sdhi1_device,
+};
+
+static struct map_desc g4evm_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init g4evm_map_io(void)
+{
+        iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
+
+        /* setup early devices and console here as well */
+        sh7377_add_early_devices();
+        shmobile_setup_console();
+}
+
+#define GPIO_SDHID0_D0  0xe60520fc
+#define GPIO_SDHID0_D1  0xe60520fd
+#define GPIO_SDHID0_D2  0xe60520fe
+#define GPIO_SDHID0_D3  0xe60520ff
+#define GPIO_SDHICMD0   0xe6052100
+
+#define GPIO_SDHID1_D0  0xe6052103
+#define GPIO_SDHID1_D1  0xe6052104
+#define GPIO_SDHID1_D2  0xe6052105
+#define GPIO_SDHID1_D3  0xe6052106
+#define GPIO_SDHICMD1   0xe6052107
+
+/*
+ * FIXME !!
+ *
+ * gpio_pull_up is quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_pull_up(u32 addr)
+{
+        u8 data = __raw_readb(addr);
+
+        data &= 0x0F;
+        data |= 0xC0;
+        __raw_writeb(data, addr);
+}
+
+static void __init g4evm_init(void)
+{
+        sh7377_pinmux_init();
+
+        /* Lit DS14 LED */
+        gpio_request(GPIO_PORT109, NULL);
+        gpio_direction_output(GPIO_PORT109, 1);
+        gpio_export(GPIO_PORT109, 1);
+
+        /* Lit DS15 LED */
+        gpio_request(GPIO_PORT110, NULL);
+        gpio_direction_output(GPIO_PORT110, 1);
+        gpio_export(GPIO_PORT110, 1);
+
+        /* Lit DS16 LED */
+        gpio_request(GPIO_PORT112, NULL);
+        gpio_direction_output(GPIO_PORT112, 1);
+        gpio_export(GPIO_PORT112, 1);
+
+        /* Lit DS17 LED */
+        gpio_request(GPIO_PORT113, NULL);
+        gpio_direction_output(GPIO_PORT113, 1);
+        gpio_export(GPIO_PORT113, 1);
+
+        /* USBHS */
+        gpio_request(GPIO_FN_VBUS_0, NULL);
+        gpio_request(GPIO_FN_PWEN, NULL);
+        gpio_request(GPIO_FN_OVCN, NULL);
+        gpio_request(GPIO_FN_OVCN2, NULL);
+        gpio_request(GPIO_FN_EXTLP, NULL);
+        gpio_request(GPIO_FN_IDIN, NULL);
+
+        /* setup USB phy */
+        __raw_writew(0x0200, 0xe605810a);       /* USBCR1 */
+        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
+        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
+        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+
+        /* KEYSC @ CN31 */
+        gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
+        gpio_request(GPIO_FN_PORT61_KEYOUT4, NULL);
+        gpio_request(GPIO_FN_PORT62_KEYOUT3, NULL);
+        gpio_request(GPIO_FN_PORT63_KEYOUT2, NULL);
+        gpio_request(GPIO_FN_PORT64_KEYOUT1, NULL);
+        gpio_request(GPIO_FN_PORT65_KEYOUT0, NULL);
+        gpio_request(GPIO_FN_PORT66_KEYIN0_PU, NULL);
+        gpio_request(GPIO_FN_PORT67_KEYIN1_PU, NULL);
+        gpio_request(GPIO_FN_PORT68_KEYIN2_PU, NULL);
+        gpio_request(GPIO_FN_PORT69_KEYIN3_PU, NULL);
+        gpio_request(GPIO_FN_PORT70_KEYIN4_PU, NULL);
+        gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
+        gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
+
+        /* SDHI0 */
+        gpio_request(GPIO_FN_SDHICLK0, NULL);
+        gpio_request(GPIO_FN_SDHICD0, NULL);
+        gpio_request(GPIO_FN_SDHID0_0, NULL);
+        gpio_request(GPIO_FN_SDHID0_1, NULL);
+        gpio_request(GPIO_FN_SDHID0_2, NULL);
+        gpio_request(GPIO_FN_SDHID0_3, NULL);
+        gpio_request(GPIO_FN_SDHICMD0, NULL);
+        gpio_request(GPIO_FN_SDHIWP0, NULL);
+        gpio_pull_up(GPIO_SDHID0_D0);
+        gpio_pull_up(GPIO_SDHID0_D1);
+        gpio_pull_up(GPIO_SDHID0_D2);
+        gpio_pull_up(GPIO_SDHID0_D3);
+        gpio_pull_up(GPIO_SDHICMD0);
+
+        /* SDHI1 */
+        gpio_request(GPIO_FN_SDHICLK1, NULL);
+        gpio_request(GPIO_FN_SDHID1_0, NULL);
+        gpio_request(GPIO_FN_SDHID1_1, NULL);
+        gpio_request(GPIO_FN_SDHID1_2, NULL);
+        gpio_request(GPIO_FN_SDHID1_3, NULL);
+        gpio_request(GPIO_FN_SDHICMD1, NULL);
+        gpio_pull_up(GPIO_SDHID1_D0);
+        gpio_pull_up(GPIO_SDHID1_D1);
+        gpio_pull_up(GPIO_SDHID1_D2);
+        gpio_pull_up(GPIO_SDHID1_D3);
+        gpio_pull_up(GPIO_SDHICMD1);
+
+        sh7377_add_standard_devices();
+
+        platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
+}
+
+static void __init g4evm_timer_init(void)
+{
+        sh7377_clock_init();
+        shmobile_timer.init();
+}
+
+static struct sys_timer g4evm_timer = {
+        .init           = g4evm_timer_init,
+};
+
+MACHINE_START(G4EVM, "g4evm")
+        .map_io         = g4evm_map_io,
+        .init_irq       = sh7377_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = g4evm_init,
+        .timer          = &g4evm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
new file mode 100644
index 000000000000..5bcf5c1e1399
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -0,0 +1,1200 @@
+/*
+ * mackerel board support
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * based on ap4evb
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/smsc911x.h>
+#include <linux/sh_intc.h>
+#include <linux/tca6416_keypad.h>
+#include <linux/usb/r8a66597.h>
+
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
+#include <media/sh_mobile_ceu.h>
+#include <media/soc_camera.h>
+#include <media/soc_camera_platform.h>
+#include <sound/sh_fsi.h>
+
+#include <mach/common.h>
+#include <mach/sh7372.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+/*
+ * Address      Interface               BusWidth        note
+ * ------------------------------------------------------------------
+ * 0x0000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
+ * 0x0800_0000  user area               -
+ * 0x1000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
+ * 0x1400_0000  Ether (LAN9220)         16bit
+ * 0x1600_0000  user area               -               cannot use with NAND
+ * 0x1800_0000  user area               -
+ * 0x1A00_0000  -
+ * 0x4000_0000  LPDDR2-SDRAM (POP)      32bit
+ */
+
+/*
+ * CPU mode
+ *
+ * SW4                                     | Boot Area| Master   | Remarks
+ *  1  | 2   | 3   | 4   | 5   | 6   | 8   |          | Processor|
+ * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
+ * ON  | ON  | OFF | ON  | ON  | OFF | OFF | External | System   | External ROM
+ * ON  | ON  | ON  | ON  | ON  | OFF | OFF | External | System   | ROM Debug
+ * ON  | ON  | X   | ON  | OFF | OFF | OFF | Built-in | System   | ROM Debug
+ * X   | OFF | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
+ * OFF | X   | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
+ * X   | X   | X   | OFF | X   | X   | OFF | Built-in | System   | MaskROM
+ * OFF | ON  | OFF | X   | X   | OFF | ON  | External | System   | Standalone
+ * ON  | OFF | OFF | X   | X   | OFF | ON  | External | Realtime | Standalone
+*/
+
+/*
+ * NOR Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NOR Flash ROM
+ *  bit1 | bit1  bit2 | bit1 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    Area 0
+ *  OFF  | ON     OFF | OFF  |    Area 4
+ */
+
+/*
+ * SMSC 9220
+ *
+ *  SW1         SMSC 9220
+ * -----------------------
+ *  ON          access disable
+ *  OFF         access enable
+ */
+
+/*
+ * NAND Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NAND Flash ROM
+ *  bit1 | bit1  bit2 | bit2 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    FCE 0
+ *  OFF  | ON     OFF | OFF  |    FCE 1
+ */
+
+/*
+ * External interrupt pin settings
+ *
+ * IRQX  | pin setting        | device             | level
+ * ------+--------------------+--------------------+-------
+ * IRQ0  | ICR1A.IRQ0SA=0010  | SDHI2 card detect  | Low
+ * IRQ6  | ICR1A.IRQ6SA=0011  | Ether(LAN9220)     | High
+ * IRQ7  | ICR1A.IRQ7SA=0010  | LCD Tuch Panel     | Low
+ * IRQ8  | ICR2A.IRQ8SA=0010  | MMC/SD card detect | Low
+ * IRQ9  | ICR2A.IRQ9SA=0010  | KEY(TCA6408)       | Low
+ * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345)    | High
+ * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975)     | High
+ */
+
+/*
+ * USB
+ *
+ * USB0 : CN22 : Function
+ * USB1 : CN31 : Function/Host *1
+ *
+ * J30 (for CN31) *1
+ * ----------+---------------+-------------
+ * 1-2 short | VBUS 5V       | Host
+ * open      | external VBUS | Function
+ *
+ * *1
+ * CN31 is used as Host in Linux.
+ */
+
+/*
+ * SDHI0 (CN12)
+ *
+ * SW56 : OFF
+ *
+ */
+
+/* MMC /SDHI1 (CN7)
+ *
+ * I/O voltage : 1.8v
+ *
+ * Power voltage : 1.8v or 3.3v
+ *  J22 : select power voltage *1
+ *      1-2 pin : 1.8v
+ *      2-3 pin : 3.3v
+ *
+ * *1
+ * Please change J22 depends the card to be used.
+ * MMC's OCR field set to support either voltage for the card inserted.
+ *
+ *      SW1     |       SW33
+ *              | bit1 | bit2 | bit3 | bit4
+ * -------------+------+------+------+-------
+ * MMC0   OFF   |  OFF |  ON  |  ON  |  X
+ * MMC1   ON    |  OFF |  ON  |  X   | ON
+ * SDHI1  OFF   |  ON  |   X  |  OFF | ON
+ *
+ */
+
+/*
+ * SDHI2 (CN23)
+ *
+ * microSD card sloct
+ *
+ */
+
+/*
+ * FIXME !!
+ *
+ * gpio_no_direction
+ * are quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_no_direction(u32 addr)
+{
+        __raw_writeb(0x00, addr);
+}
+
+/* MTD */
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel_ro",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x08000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+/* SMSC */
+static struct resource smc911x_resources[] = {
+        {
+                .start  = 0x14000000,
+                .end    = 0x16000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = evt2irq(0x02c0) /* IRQ6A */,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_info = {
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device smc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc911x_resources),
+        .resource       = smc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_info,
+        },
+};
+
+/* LCDC */
+static struct fb_videomode mackerel_lcdc_modes[] = {
+        {
+                .name           = "WVGA Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0,
+        },
+};
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .clock_source = LCDC_CLK_BUS,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .lcd_cfg = mackerel_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
+                .interface_type         = RGB24,
+                .clock_divider          = 2,
+                .flags                  = 0,
+                .lcd_size_cfg.width     = 152,
+                .lcd_size_cfg.height    = 91,
+        }
+};
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000,
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev    = {
+                .platform_data  = &lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+/* HDMI */
+static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
+        .clock_source = LCDC_CLK_EXTERNAL,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .interface_type = RGB24,
+                .clock_divider = 1,
+                .flags = LCDC_FLAGS_DWPOL,
+        }
+};
+
+static struct resource hdmi_lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC1",
+                .start  = 0xfe944000,
+                .end    = 0xfe947fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x1780),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(hdmi_lcdc_resources),
+        .resource       = hdmi_lcdc_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &hdmi_lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+static struct sh_mobile_hdmi_info hdmi_info = {
+        .lcd_chan       = &hdmi_lcdc_info.ch[0],
+        .lcd_dev        = &hdmi_lcdc_device.dev,
+        .flags          = HDMI_SND_SRC_SPDIF,
+};
+
+static struct resource hdmi_resources[] = {
+        [0] = {
+                .name   = "HDMI",
+                .start  = 0xe6be0000,
+                .end    = 0xe6be00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
+                .start  = evt2irq(0x17e0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_device = {
+        .name           = "sh-mobile-hdmi",
+        .num_resources  = ARRAY_SIZE(hdmi_resources),
+        .resource       = hdmi_resources,
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &hdmi_info,
+        },
+};
+
+static int __init hdmi_init_pm_clock(void)
+{
+        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+        int ret;
+        long rate;
+
+        if (IS_ERR(hdmi_ick)) {
+                ret = PTR_ERR(hdmi_ick);
+                pr_err("Cannot get HDMI ICK: %d\n", ret);
+                goto out;
+        }
+
+        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
+        if (ret < 0) {
+                pr_err("Cannot set PLLC2 parent: %d, %d users\n",
+                       ret, sh7372_pllc2_clk.usecount);
+                goto out;
+        }
+
+        pr_debug("PLLC2 initial frequency %lu\n",
+                 clk_get_rate(&sh7372_pllc2_clk));
+
+        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
+        if (rate < 0) {
+                pr_err("Cannot get suitable rate: %ld\n", rate);
+                ret = rate;
+                goto out;
+        }
+
+        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
+        if (ret < 0) {
+                pr_err("Cannot set rate %ld: %d\n", rate, ret);
+                goto out;
+        }
+
+        ret = clk_enable(&sh7372_pllc2_clk);
+        if (ret < 0) {
+                pr_err("Cannot enable pllc2 clock\n");
+                goto out;
+        }
+
+        pr_debug("PLLC2 set frequency %lu\n", rate);
+
+        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
+        if (ret < 0) {
+                pr_err("Cannot set HDMI parent: %d\n", ret);
+                goto out;
+        }
+
+out:
+        if (!IS_ERR(hdmi_ick))
+                clk_put(hdmi_ick);
+        return ret;
+}
+device_initcall(hdmi_init_pm_clock);
+
+/* USB1 (Host) */
+static void usb1_host_port_power(int port, int power)
+{
+        if (!power) /* only power-on is supported for now */
+                return;
+
+        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
+        __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+}
+
+static struct r8a66597_platdata usb1_host_data = {
+        .on_chip        = 1,
+        .port_power     = usb1_host_port_power,
+};
+
+static struct resource usb1_host_resources[] = {
+        [0] = {
+                .name   = "USBHS",
+                .start  = 0xE68B0000,
+                .end    = 0xE68B00E6 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb1_host_device = {
+        .name   = "r8a66597_hcd",
+        .id     = 1,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usb1_host_data,
+        },
+        .num_resources  = ARRAY_SIZE(usb1_host_resources),
+        .resource       = usb1_host_resources,
+};
+
+/* LED */
+static struct gpio_led mackerel_leds[] = {
+        {
+                .name           = "led0",
+                .gpio           = GPIO_PORT0,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name           = "led1",
+                .gpio           = GPIO_PORT1,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name           = "led2",
+                .gpio           = GPIO_PORT2,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name           = "led3",
+                .gpio           = GPIO_PORT159,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }
+};
+
+static struct gpio_led_platform_data mackerel_leds_pdata = {
+        .leds = mackerel_leds,
+        .num_leds = ARRAY_SIZE(mackerel_leds),
+};
+
+static struct platform_device leds_device = {
+        .name = "leds-gpio",
+        .id = 0,
+        .dev = {
+                .platform_data  = &mackerel_leds_pdata,
+        },
+};
+
+/* FSI */
+#define IRQ_FSI evt2irq(0x1840)
+static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
+{
+        int ret;
+
+        if (rate <= 0)
+                return 0;
+
+        if (!enable) {
+                clk_disable(clk);
+                return 0;
+        }
+
+        ret = clk_set_rate(clk, clk_round_rate(clk, rate));
+        if (ret < 0)
+                return ret;
+
+        return clk_enable(clk);
+}
+
+static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
+{
+        struct clk *fsib_clk;
+        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        long fsib_rate = 0;
+        long fdiv_rate = 0;
+        int ackmd_bpfmd;
+        int ret;
+
+        /* FSIA is slave mode. nothing to do here */
+        if (is_porta)
+                return 0;
+
+        /* clock start */
+        switch (rate) {
+        case 44100:
+                fsib_rate       = rate * 256;
+                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        case 48000:
+                fsib_rate       = 85428000; /* around 48kHz x 256 x 7 */
+                fdiv_rate       = rate * 256;
+                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        default:
+                pr_err("unsupported rate in FSI2 port B\n");
+                return -EINVAL;
+        }
+
+        /* FSI B setting */
+        fsib_clk = clk_get(dev, "ickb");
+        if (IS_ERR(fsib_clk))
+                return -EIO;
+
+        /* fsib */
+        ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
+        if (ret < 0)
+                goto fsi_set_rate_end;
+
+        /* FSI DIV */
+        ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
+        if (ret < 0) {
+                /* disable FSI B */
+                if (enable)
+                        __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
+                goto fsi_set_rate_end;
+        }
+
+        ret = ackmd_bpfmd;
+
+fsi_set_rate_end:
+        clk_put(fsib_clk);
+        return ret;
+}
+
+static struct sh_fsi_platform_info fsi_info = {
+        .porta_flags =  SH_FSI_BRS_INV          |
+                        SH_FSI_OUT_SLAVE_MODE   |
+                        SH_FSI_IN_SLAVE_MODE    |
+                        SH_FSI_OFMT(PCM)        |
+                        SH_FSI_IFMT(PCM),
+
+        .portb_flags =  SH_FSI_BRS_INV  |
+                        SH_FSI_BRM_INV  |
+                        SH_FSI_LRS_INV  |
+                        SH_FSI_OFMT(SPDIF),
+
+        .set_rate = fsi_set_rate,
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xFE3C0000,
+                .end    = 0xFE3C0400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FSI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+static struct platform_device fsi_ak4643_device = {
+        .name           = "sh_fsi2_a_ak4643",
+};
+
+/*
+ * The card detect pin of the top SD/MMC slot (CN7) is active low and is
+ * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ */
+static int slot_cn7_get_cd(struct platform_device *pdev)
+{
+        if (gpio_is_valid(GPIO_PORT41))
+                return !gpio_get_value(GPIO_PORT41);
+        else
+                return -ENXIO;
+}
+
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "SDHI0",
+                .start  = 0xe6850000,
+                .end    = 0xe68501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e00) /* SDHI0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &sdhi0_info,
+        },
+};
+
+#if !defined(CONFIG_MMC_SH_MMCIF)
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+        .tmio_ocr_mask  = MMC_VDD_165_195,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED |
+                          MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
+};
+
+static struct resource sdhi1_resources[] = {
+        [0] = {
+                .name   = "SDHI1",
+                .start  = 0xe6860000,
+                .end    = 0xe68601ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e80),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi1_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi1_resources),
+        .resource       = sdhi1_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &sdhi1_info,
+        },
+};
+#endif
+
+/* SDHI2 */
+static struct sh_mobile_sdhi_info sdhi2_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI2_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI2_RX,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED |
+                          MMC_CAP_NEEDS_POLL,
+};
+
+static struct resource sdhi2_resources[] = {
+        [0] = {
+                .name   = "SDHI2",
+                .start  = 0xe6870000,
+                .end    = 0xe68701ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1200),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi2_device = {
+        .name   = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi2_resources),
+        .resource       = sdhi2_resources,
+        .id             = 2,
+        .dev    = {
+                .platform_data  = &sdhi2_info,
+        },
+};
+
+/* SH_MMCIF */
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xE6BD0000,
+                .end    = 0xE6BD00FF,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* MMC ERR */
+                .start  = evt2irq(0x1ac0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* MMC NOR */
+                .start  = evt2irq(0x1ae0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .caps           = MMC_CAP_4_BIT_DATA |
+                          MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
+};
+
+static struct platform_device sh_mmcif_device = {
+        .name           = "sh_mmcif",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh_mmcif_plat,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+
+
+static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev);
+static void mackerel_camera_del(struct soc_camera_link *icl);
+
+static int camera_set_capture(struct soc_camera_platform_info *info,
+                              int enable)
+{
+        return 0; /* camera sensor always enabled */
+}
+
+static struct soc_camera_platform_info camera_info = {
+        .format_name = "UYVY",
+        .format_depth = 16,
+        .format = {
+                .code = V4L2_MBUS_FMT_UYVY8_2X8,
+                .colorspace = V4L2_COLORSPACE_SMPTE170M,
+                .field = V4L2_FIELD_NONE,
+                .width = 640,
+                .height = 480,
+        },
+        .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
+        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
+        SOCAM_DATA_ACTIVE_HIGH,
+        .set_capture = camera_set_capture,
+};
+
+static struct soc_camera_link camera_link = {
+        .bus_id         = 0,
+        .add_device     = mackerel_camera_add,
+        .del_device     = mackerel_camera_del,
+        .module_name    = "soc_camera_platform",
+        .priv           = &camera_info,
+};
+
+static void dummy_release(struct device *dev)
+{
+}
+
+static struct platform_device camera_device = {
+        .name           = "soc_camera_platform",
+        .dev            = {
+                .platform_data  = &camera_info,
+                .release        = dummy_release,
+        },
+};
+
+static int mackerel_camera_add(struct soc_camera_link *icl,
+                               struct device *dev)
+{
+        if (icl != &camera_link)
+                return -ENODEV;
+
+        camera_info.dev = dev;
+
+        return platform_device_register(&camera_device);
+}
+
+static void mackerel_camera_del(struct soc_camera_link *icl)
+{
+        if (icl != &camera_link)
+                return;
+
+        platform_device_unregister(&camera_device);
+        memset(&camera_device.dev.kobj, 0,
+               sizeof(camera_device.dev.kobj));
+}
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+};
+
+static struct resource ceu_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x880),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 0, /* "ceu0" clock */
+        .num_resources  = ARRAY_SIZE(ceu_resources),
+        .resource       = ceu_resources,
+        .dev            = {
+                .platform_data  = &sh_mobile_ceu_info,
+        },
+};
+
+static struct platform_device mackerel_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &camera_link,
+        },
+};
+
+static struct platform_device *mackerel_devices[] __initdata = {
+        &nor_flash_device,
+        &smc911x_device,
+        &lcdc_device,
+        &usb1_host_device,
+        &leds_device,
+        &fsi_device,
+        &fsi_ak4643_device,
+        &sdhi0_device,
+#if !defined(CONFIG_MMC_SH_MMCIF)
+        &sdhi1_device,
+#endif
+        &sdhi2_device,
+        &sh_mmcif_device,
+        &ceu_device,
+        &mackerel_camera,
+        &hdmi_lcdc_device,
+        &hdmi_device,
+};
+
+/* Keypad Initialization */
+#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
+{                                                               \
+        .type           = ev_type,                              \
+        .code           = ev_code,                              \
+        .active_low     = act_low,                              \
+}
+
+#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
+
+static struct tca6416_button mackerel_gpio_keys[] = {
+        KEYPAD_BUTTON_LOW(KEY_HOME),
+        KEYPAD_BUTTON_LOW(KEY_MENU),
+        KEYPAD_BUTTON_LOW(KEY_BACK),
+        KEYPAD_BUTTON_LOW(KEY_POWER),
+};
+
+static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
+        .buttons        = mackerel_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(mackerel_gpio_keys),
+        .rep            = 1,
+        .use_polling    = 0,
+        .pinmask        = 0x000F,
+};
+
+/* I2C */
+#define IRQ9 evt2irq(0x0320)
+
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("ak4643", 0x13),
+        },
+        /* Keypad */
+        {
+                I2C_BOARD_INFO("tca6408-keys", 0x20),
+                .platform_data = &mackerel_tca6416_keys_info,
+                .irq = IRQ9,
+        },
+};
+
+#define IRQ21 evt2irq(0x32a0)
+
+static struct i2c_board_info i2c1_devices[] = {
+        /* Accelerometer */
+        {
+                I2C_BOARD_INFO("adxl34x", 0x53),
+                .irq = IRQ21,
+        },
+};
+
+static struct map_desc mackerel_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init mackerel_map_io(void)
+{
+        iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
+
+        /* setup early devices and console here as well */
+        sh7372_add_early_devices();
+        shmobile_setup_console();
+}
+
+#define GPIO_PORT9CR    0xE6051009
+#define GPIO_PORT10CR   0xE605100A
+#define SRCR4           0xe61580bc
+#define USCCR1          0xE6058144
+static void __init mackerel_init(void)
+{
+        u32 srcr4;
+        struct clk *clk;
+
+        sh7372_pinmux_init();
+
+        /* enable SCIFA0 */
+        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
+        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
+
+        /* enable SMSC911X */
+        gpio_request(GPIO_FN_CS5A,      NULL);
+        gpio_request(GPIO_FN_IRQ6_39,   NULL);
+
+        /* LCDC */
+        gpio_request(GPIO_FN_LCDD23,   NULL);
+        gpio_request(GPIO_FN_LCDD22,   NULL);
+        gpio_request(GPIO_FN_LCDD21,   NULL);
+        gpio_request(GPIO_FN_LCDD20,   NULL);
+        gpio_request(GPIO_FN_LCDD19,   NULL);
+        gpio_request(GPIO_FN_LCDD18,   NULL);
+        gpio_request(GPIO_FN_LCDD17,   NULL);
+        gpio_request(GPIO_FN_LCDD16,   NULL);
+        gpio_request(GPIO_FN_LCDD15,   NULL);
+        gpio_request(GPIO_FN_LCDD14,   NULL);
+        gpio_request(GPIO_FN_LCDD13,   NULL);
+        gpio_request(GPIO_FN_LCDD12,   NULL);
+        gpio_request(GPIO_FN_LCDD11,   NULL);
+        gpio_request(GPIO_FN_LCDD10,   NULL);
+        gpio_request(GPIO_FN_LCDD9,    NULL);
+        gpio_request(GPIO_FN_LCDD8,    NULL);
+        gpio_request(GPIO_FN_LCDD7,    NULL);
+        gpio_request(GPIO_FN_LCDD6,    NULL);
+        gpio_request(GPIO_FN_LCDD5,    NULL);
+        gpio_request(GPIO_FN_LCDD4,    NULL);
+        gpio_request(GPIO_FN_LCDD3,    NULL);
+        gpio_request(GPIO_FN_LCDD2,    NULL);
+        gpio_request(GPIO_FN_LCDD1,    NULL);
+        gpio_request(GPIO_FN_LCDD0,    NULL);
+        gpio_request(GPIO_FN_LCDDISP,  NULL);
+        gpio_request(GPIO_FN_LCDDCK,   NULL);
+
+        gpio_request(GPIO_PORT31, NULL); /* backlight */
+        gpio_direction_output(GPIO_PORT31, 1);
+
+        gpio_request(GPIO_PORT151, NULL); /* LCDDON */
+        gpio_direction_output(GPIO_PORT151, 1);
+
+        /* USB enable */
+        gpio_request(GPIO_FN_VBUS0_1,    NULL);
+        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
+        gpio_request(GPIO_FN_PWEN_1_115, NULL);
+        gpio_request(GPIO_FN_OVCN_1_114, NULL);
+        gpio_request(GPIO_FN_EXTLP_1,    NULL);
+        gpio_request(GPIO_FN_OVCN2_1,    NULL);
+
+        /* setup USB phy */
+        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+
+        /* enable FSI2 port A (ak4643) */
+        gpio_request(GPIO_FN_FSIAIBT,   NULL);
+        gpio_request(GPIO_FN_FSIAILR,   NULL);
+        gpio_request(GPIO_FN_FSIAISLD,  NULL);
+        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        gpio_request(GPIO_PORT161,      NULL);
+        gpio_direction_output(GPIO_PORT161, 0); /* slave */
+
+        gpio_request(GPIO_PORT9,  NULL);
+        gpio_request(GPIO_PORT10, NULL);
+        gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+        gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+
+        intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
+
+        /* setup FSI2 port B (HDMI) */
+        gpio_request(GPIO_FN_FSIBCK, NULL);
+        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
+
+        /* set SPU2 clock to 119.6 MHz */
+        clk = clk_get(NULL, "spu_clk");
+        if (!IS_ERR(clk)) {
+                clk_set_rate(clk, clk_round_rate(clk, 119600000));
+                clk_put(clk);
+        }
+
+        /* enable Keypad */
+        gpio_request(GPIO_FN_IRQ9_42,   NULL);
+        set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
+
+        /* enable Accelerometer */
+        gpio_request(GPIO_FN_IRQ21,     NULL);
+        set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
+
+        /* enable SDHI0 */
+        gpio_request(GPIO_FN_SDHICD0, NULL);
+        gpio_request(GPIO_FN_SDHIWP0, NULL);
+        gpio_request(GPIO_FN_SDHICMD0, NULL);
+        gpio_request(GPIO_FN_SDHICLK0, NULL);
+        gpio_request(GPIO_FN_SDHID0_3, NULL);
+        gpio_request(GPIO_FN_SDHID0_2, NULL);
+        gpio_request(GPIO_FN_SDHID0_1, NULL);
+        gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+#if !defined(CONFIG_MMC_SH_MMCIF)
+        /* enable SDHI1 */
+        gpio_request(GPIO_FN_SDHICMD1, NULL);
+        gpio_request(GPIO_FN_SDHICLK1, NULL);
+        gpio_request(GPIO_FN_SDHID1_3, NULL);
+        gpio_request(GPIO_FN_SDHID1_2, NULL);
+        gpio_request(GPIO_FN_SDHID1_1, NULL);
+        gpio_request(GPIO_FN_SDHID1_0, NULL);
+#endif
+        /* card detect pin for MMC slot (CN7) */
+        gpio_request(GPIO_PORT41, NULL);
+        gpio_direction_input(GPIO_PORT41);
+
+        /* enable SDHI2 */
+        gpio_request(GPIO_FN_SDHICMD2, NULL);
+        gpio_request(GPIO_FN_SDHICLK2, NULL);
+        gpio_request(GPIO_FN_SDHID2_3, NULL);
+        gpio_request(GPIO_FN_SDHID2_2, NULL);
+        gpio_request(GPIO_FN_SDHID2_1, NULL);
+        gpio_request(GPIO_FN_SDHID2_0, NULL);
+
+        /* MMCIF */
+        gpio_request(GPIO_FN_MMCD0_0, NULL);
+        gpio_request(GPIO_FN_MMCD0_1, NULL);
+        gpio_request(GPIO_FN_MMCD0_2, NULL);
+        gpio_request(GPIO_FN_MMCD0_3, NULL);
+        gpio_request(GPIO_FN_MMCD0_4, NULL);
+        gpio_request(GPIO_FN_MMCD0_5, NULL);
+        gpio_request(GPIO_FN_MMCD0_6, NULL);
+        gpio_request(GPIO_FN_MMCD0_7, NULL);
+        gpio_request(GPIO_FN_MMCCMD0, NULL);
+        gpio_request(GPIO_FN_MMCCLK0, NULL);
+
+        /* enable GPS module (GT-720F) */
+        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
+        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
+
+        /* CEU */
+        gpio_request(GPIO_FN_VIO_CLK, NULL);
+        gpio_request(GPIO_FN_VIO_VD, NULL);
+        gpio_request(GPIO_FN_VIO_HD, NULL);
+        gpio_request(GPIO_FN_VIO_FIELD, NULL);
+        gpio_request(GPIO_FN_VIO_CKO, NULL);
+        gpio_request(GPIO_FN_VIO_D7, NULL);
+        gpio_request(GPIO_FN_VIO_D6, NULL);
+        gpio_request(GPIO_FN_VIO_D5, NULL);
+        gpio_request(GPIO_FN_VIO_D4, NULL);
+        gpio_request(GPIO_FN_VIO_D3, NULL);
+        gpio_request(GPIO_FN_VIO_D2, NULL);
+        gpio_request(GPIO_FN_VIO_D1, NULL);
+        gpio_request(GPIO_FN_VIO_D0, NULL);
+
+        /* HDMI */
+        gpio_request(GPIO_FN_HDMI_HPD, NULL);
+        gpio_request(GPIO_FN_HDMI_CEC, NULL);
+
+        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
+        srcr4 = __raw_readl(SRCR4);
+        __raw_writel(srcr4 | (1 << 13), SRCR4);
+        udelay(50);
+        __raw_writel(srcr4 & ~(1 << 13), SRCR4);
+
+        i2c_register_board_info(0, i2c0_devices,
+                                ARRAY_SIZE(i2c0_devices));
+        i2c_register_board_info(1, i2c1_devices,
+                                ARRAY_SIZE(i2c1_devices));
+
+        sh7372_add_standard_devices();
+
+        platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
+}
+
+static void __init mackerel_timer_init(void)
+{
+        sh7372_clock_init();
+        shmobile_timer.init();
+
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+}
+
+static struct sys_timer mackerel_timer = {
+        .init           = mackerel_timer_init,
+};
+
+MACHINE_START(MACKEREL, "mackerel")
+        .map_io         = mackerel_map_io,
+        .init_irq       = sh7372_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = mackerel_init,
+        .timer          = &mackerel_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
new file mode 100644
index 000000000000..6b186aefcbd6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -0,0 +1,358 @@
+/*
+ * SH7367 clock framework support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+/* SH7367 registers */
+#define RTFRQCR    0xe6150000
+#define SYFRQCR    0xe6150004
+#define CMFRQCR    0xe61500E0
+#define VCLKCR1    0xe6150008
+#define VCLKCR2    0xe615000C
+#define VCLKCR3    0xe615001C
+#define SCLKACR    0xe6150010
+#define SCLKBCR    0xe6150014
+#define SUBUSBCKCR 0xe6158080
+#define SPUCKCR    0xe6150084
+#define MSUCKCR    0xe6150088
+#define MVI3CKCR   0xe6150090
+#define VOUCKCR    0xe6150094
+#define MFCK1CR    0xe6150098
+#define MFCK2CR    0xe615009C
+#define PLLC1CR    0xe6150028
+#define PLLC2CR    0xe615002C
+#define RTMSTPCR0  0xe6158030
+#define RTMSTPCR2  0xe6158038
+#define SYMSTPCR0  0xe6158040
+#define SYMSTPCR2  0xe6158048
+#define CMMSTPCR0  0xe615804c
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTALB1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7367_extalb1_clk = {
+        .rate           = 26666666,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7367_extal2_clk = {
+        .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+        .recalc         = div2_recalc,
+};
+
+/* Divide extalb1 by two */
+static struct clk extalb1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7367_extalb1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7367_extal2_clk,
+};
+
+/* PLLC1 */
+static unsigned long pllc1_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLC1CR) & (1 << 14))
+                mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc1_clk_ops = {
+        .recalc         = pllc1_recalc,
+};
+
+static struct clk pllc1_clk = {
+        .ops            = &pllc1_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &extalb1_div2_clk,
+};
+
+/* Divide PLLC1 by two */
+static struct clk pllc1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &pllc1_clk,
+};
+
+/* PLLC2 */
+static unsigned long pllc2_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLC2CR) & (1 << 31))
+                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc2_clk_ops = {
+        .recalc         = pllc2_recalc,
+};
+
+static struct clk pllc2_clk = {
+        .ops            = &pllc2_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &extalb1_div2_clk,
+};
+
+static struct clk *main_clks[] = {
+        &r_clk,
+        &sh7367_extalb1_clk,
+        &sh7367_extal2_clk,
+        &extalb1_div2_clk,
+        &extal2_div2_clk,
+        &pllc1_clk,
+        &pllc1_div2_clk,
+        &pllc2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in SYFRQCR to update hardware setting */
+        value = __raw_readl(SYFRQCR);
+        value |= (1 << 31);
+        __raw_writel(value, SYFRQCR);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                          24, 32, 36, 48, 0, 72, 0, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
+       DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
+       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
+        [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
+        [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
+        [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
+        [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
+        [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
+        [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
+        [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
+        [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
+};
+
+enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
+       DIV6_MVI3, DIV6_MF1, DIV6_MF2,
+       DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
+       DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
+        [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
+        [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
+        [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
+        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
+        [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
+        [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
+        [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
+        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
+        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
+        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
+        [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
+};
+
+enum { RTMSTP001,
+       RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
+       RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
+       SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
+       SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
+       SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
+       SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
+       CMMSTP003,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
+        [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
+        [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
+        [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
+        [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
+        [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
+        [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
+        [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
+        [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
+        [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
+        [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
+        [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
+        [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
+        [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
+        [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
+        [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
+        [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
+        [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
+        [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
+        [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
+        [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
+        [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
+        [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
+        [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
+        [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
+        [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
+        [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
+        [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("r_clk", &r_clk),
+        CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
+        CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
+        CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
+        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
+        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
+        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
+        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
+        CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
+        CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
+        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+        CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
+        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
+        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+        CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
+        CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
+        CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
+        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
+        CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
+        CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
+        CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
+        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
+
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
+        CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
+        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
+        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
+        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
+        CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
+        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
+};
+
+void __init sh7367_clock_init(void)
+{
+        int k, ret = 0;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup sh7367 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
new file mode 100644
index 000000000000..9aa8d68d1a9c
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -0,0 +1,681 @@
+/*
+ * SH7372 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+/* SH7372 registers */
+#define FRQCRA          0xe6150000
+#define FRQCRB          0xe6150004
+#define FRQCRC          0xe61500e0
+#define FRQCRD          0xe61500e4
+#define VCLKCR1         0xe6150008
+#define VCLKCR2         0xe615000c
+#define VCLKCR3         0xe615001c
+#define FMSICKCR        0xe6150010
+#define FMSOCKCR        0xe6150014
+#define FSIACKCR        0xe6150018
+#define FSIBCKCR        0xe6150090
+#define SUBCKCR         0xe6150080
+#define SPUCKCR         0xe6150084
+#define VOUCKCR         0xe6150088
+#define HDMICKCR        0xe6150094
+#define DSITCKCR        0xe6150060
+#define DSI0PCKCR       0xe6150064
+#define DSI1PCKCR       0xe6150098
+#define PLLC01CR        0xe6150028
+#define PLLC2CR         0xe615002c
+#define SMSTPCR0        0xe6150130
+#define SMSTPCR1        0xe6150134
+#define SMSTPCR2        0xe6150138
+#define SMSTPCR3        0xe615013c
+#define SMSTPCR4        0xe6150140
+
+#define FSIDIVA         0xFE1F8000
+#define FSIDIVB         0xFE1F8008
+
+/* Platforms must set frequency on their DV_CLKI pin */
+struct clk sh7372_dv_clki_clk = {
+};
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7372_extal1_clk = {
+        .rate           = 26000000,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7372_extal2_clk = {
+        .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+        .recalc         = div2_recalc,
+};
+
+/* Divide dv_clki by two */
+struct clk sh7372_dv_clki_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7372_dv_clki_clk,
+};
+
+/* Divide extal1 by two */
+static struct clk extal1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7372_extal1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7372_extal2_clk,
+};
+
+/* Divide extal2 by four */
+static struct clk extal2_div4_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &extal2_div2_clk,
+};
+
+/* PLLC0 and PLLC1 */
+static unsigned long pllc01_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLC01CR) & (1 << 14))
+                mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc01_clk_ops = {
+        .recalc         = pllc01_recalc,
+};
+
+static struct clk pllc0_clk = {
+        .ops            = &pllc01_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &extal1_div2_clk,
+        .enable_reg     = (void __iomem *)FRQCRC,
+};
+
+static struct clk pllc1_clk = {
+        .ops            = &pllc01_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &extal1_div2_clk,
+        .enable_reg     = (void __iomem *)FRQCRA,
+};
+
+/* Divide PLLC1 by two */
+static struct clk pllc1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &pllc1_clk,
+};
+
+/* PLLC2 */
+
+/* Indices are important - they are the actual src selecting values */
+static struct clk *pllc2_parent[] = {
+        [0] = &extal1_div2_clk,
+        [1] = &extal2_div2_clk,
+        [2] = &sh7372_dv_clki_div2_clk,
+};
+
+/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
+static struct cpufreq_frequency_table pllc2_freq_table[29];
+
+static void pllc2_table_rebuild(struct clk *clk)
+{
+        int i;
+
+        /* Initialise PLLC2 frequency table */
+        for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
+                pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
+                pllc2_freq_table[i].index = i;
+        }
+
+        /* This is a special entry - switching PLL off makes it a repeater */
+        pllc2_freq_table[i].frequency = clk->parent->rate;
+        pllc2_freq_table[i].index = i;
+
+        pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
+        pllc2_freq_table[i].index = i;
+}
+
+static unsigned long pllc2_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        pllc2_table_rebuild(clk);
+
+        /*
+         * If the PLL is off, mult == 1, clk->rate will be updated in
+         * pllc2_enable().
+         */
+        if (__raw_readl(PLLC2CR) & (1 << 31))
+                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static long pllc2_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_rate_table_round(clk, clk->freq_table, rate);
+}
+
+static int pllc2_enable(struct clk *clk)
+{
+        int i;
+
+        __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
+
+        for (i = 0; i < 100; i++)
+                if (__raw_readl(PLLC2CR) & 0x80000000) {
+                        clk->rate = pllc2_recalc(clk);
+                        return 0;
+                }
+
+        pr_err("%s(): timeout!\n", __func__);
+
+        return -ETIMEDOUT;
+}
+
+static void pllc2_disable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
+}
+
+static int pllc2_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long value;
+        int idx;
+
+        idx = clk_rate_table_find(clk, clk->freq_table, rate);
+        if (idx < 0)
+                return idx;
+
+        if (rate == clk->parent->rate)
+                return -EINVAL;
+
+        value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
+
+        __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
+
+        return 0;
+}
+
+static int pllc2_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 value;
+        int ret, i;
+
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+
+        if (i == clk->parent_num)
+                return -ENODEV;
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        value = __raw_readl(PLLC2CR) & ~(3 << 6);
+
+        __raw_writel(value | (i << 6), PLLC2CR);
+
+        /* Rebiuld the frequency table */
+        pllc2_table_rebuild(clk);
+
+        return 0;
+}
+
+static struct clk_ops pllc2_clk_ops = {
+        .recalc         = pllc2_recalc,
+        .round_rate     = pllc2_round_rate,
+        .set_rate       = pllc2_set_rate,
+        .enable         = pllc2_enable,
+        .disable        = pllc2_disable,
+        .set_parent     = pllc2_set_parent,
+};
+
+struct clk sh7372_pllc2_clk = {
+        .ops            = &pllc2_clk_ops,
+        .parent         = &extal1_div2_clk,
+        .freq_table     = pllc2_freq_table,
+        .nr_freqs       = ARRAY_SIZE(pllc2_freq_table) - 1,
+        .parent_table   = pllc2_parent,
+        .parent_num     = ARRAY_SIZE(pllc2_parent),
+};
+
+/* External input clock (pin name: FSIACK/FSIBCK ) */
+struct clk sh7372_fsiack_clk = {
+};
+
+struct clk sh7372_fsibck_clk = {
+};
+
+static struct clk *main_clks[] = {
+        &sh7372_dv_clki_clk,
+        &r_clk,
+        &sh7372_extal1_clk,
+        &sh7372_extal2_clk,
+        &sh7372_dv_clki_div2_clk,
+        &extal1_div2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &pllc0_clk,
+        &pllc1_clk,
+        &pllc1_div2_clk,
+        &sh7372_pllc2_clk,
+        &sh7372_fsiack_clk,
+        &sh7372_fsibck_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = __raw_readl(FRQCRB);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRB);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                          24, 32, 36, 48, 0, 72, 96, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
+       DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
+       DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
+       DIV4_DDRP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
+        [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
+        [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
+        [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
+        [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
+        [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
+        [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
+        [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
+        [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
+        [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
+        [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
+       DIV6_SUB, DIV6_SPU,
+       DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
+       DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
+        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
+        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
+        [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
+        [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
+        [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
+        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
+        [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
+        [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
+        [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
+        [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
+};
+
+enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
+
+/* Indices are important - they are the actual src selecting values */
+static struct clk *hdmi_parent[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &sh7372_pllc2_clk,
+        [2] = &sh7372_dv_clki_clk,
+        [3] = NULL,     /* pllc2_div4 not implemented yet */
+};
+
+static struct clk *fsiackcr_parent[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &sh7372_pllc2_clk,
+        [2] = &sh7372_fsiack_clk, /* external input for FSI A */
+        [3] = NULL,     /* setting prohibited */
+};
+
+static struct clk *fsibckcr_parent[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &sh7372_pllc2_clk,
+        [2] = &sh7372_fsibck_clk, /* external input for FSI B */
+        [3] = NULL,     /* setting prohibited */
+};
+
+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
+        [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
+                                      hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
+        [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
+                                      fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
+        [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
+                                      fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
+};
+
+/* FSI DIV */
+static unsigned long fsidiv_recalc(struct clk *clk)
+{
+        unsigned long value;
+
+        value = __raw_readl(clk->mapping->base);
+
+        if ((value & 0x3) != 0x3)
+                return 0;
+
+        value >>= 16;
+        if (value < 2)
+                return 0;
+
+        return clk->parent->rate / value;
+}
+
+static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_rate_div_range_round(clk, 2, 0xffff, rate);
+}
+
+static void fsidiv_disable(struct clk *clk)
+{
+        __raw_writel(0, clk->mapping->base);
+}
+
+static int fsidiv_enable(struct clk *clk)
+{
+        unsigned long value;
+
+        value  = __raw_readl(clk->mapping->base) >> 16;
+        if (value < 2)
+                return -EIO;
+
+        __raw_writel((value << 16) | 0x3, clk->mapping->base);
+
+        return 0;
+}
+
+static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
+{
+        int idx;
+
+        idx = (clk->parent->rate / rate) & 0xffff;
+        if (idx < 2)
+                return -EINVAL;
+
+        __raw_writel(idx << 16, clk->mapping->base);
+        return 0;
+}
+
+static struct clk_ops fsidiv_clk_ops = {
+        .recalc         = fsidiv_recalc,
+        .round_rate     = fsidiv_round_rate,
+        .set_rate       = fsidiv_set_rate,
+        .enable         = fsidiv_enable,
+        .disable        = fsidiv_disable,
+};
+
+static struct clk_mapping sh7372_fsidiva_clk_mapping = {
+        .phys   = FSIDIVA,
+        .len    = 8,
+};
+
+struct clk sh7372_fsidiva_clk = {
+        .ops            = &fsidiv_clk_ops,
+        .parent         = &div6_reparent_clks[DIV6_FSIA], /* late install */
+        .mapping        = &sh7372_fsidiva_clk_mapping,
+};
+
+static struct clk_mapping sh7372_fsidivb_clk_mapping = {
+        .phys   = FSIDIVB,
+        .len    = 8,
+};
+
+struct clk sh7372_fsidivb_clk = {
+        .ops            = &fsidiv_clk_ops,
+        .parent         = &div6_reparent_clks[DIV6_FSIB],  /* late install */
+        .mapping        = &sh7372_fsidivb_clk_mapping,
+};
+
+static struct clk *late_main_clks[] = {
+        &sh7372_fsidiva_clk,
+        &sh7372_fsidivb_clk,
+};
+
+enum { MSTP001,
+       MSTP131, MSTP130,
+       MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
+       MSTP118, MSTP117, MSTP116,
+       MSTP106, MSTP101, MSTP100,
+       MSTP223,
+       MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
+       MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
+        [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
+        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
+        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
+        [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
+        [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
+        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+        [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
+        [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
+        [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
+        [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
+        [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
+        [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
+        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
+        [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
+        [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
+        [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
+        [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
+        [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
+        [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
+        [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
+        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
+        CLKDEV_CON_ID("r_clk", &r_clk),
+        CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
+        CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
+        CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
+        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
+        CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
+        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+        CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
+        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
+        CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
+        CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
+        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
+        CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
+        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+        CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
+        CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
+        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
+        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+        CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
+        CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
+        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
+        CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
+        CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
+        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
+        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
+        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
+        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
+        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
+        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+        CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
+        CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
+        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
+        CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
+        CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
+        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+
+        CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
+        CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
+        CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
+};
+
+void __init sh7372_clock_init(void)
+{
+        int k, ret = 0;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
+                ret = clk_register(late_main_clks[k]);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup sh7372 clocks\n");
+
+}
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
new file mode 100644
index 000000000000..95942466e63f
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -0,0 +1,369 @@
+/*
+ * SH7377 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+/* SH7377 registers */
+#define RTFRQCR    0xe6150000
+#define SYFRQCR    0xe6150004
+#define CMFRQCR    0xe61500E0
+#define VCLKCR1    0xe6150008
+#define VCLKCR2    0xe615000C
+#define VCLKCR3    0xe615001C
+#define FMSICKCR   0xe6150010
+#define FMSOCKCR   0xe6150014
+#define FSICKCR    0xe6150018
+#define PLLC1CR    0xe6150028
+#define PLLC2CR    0xe615002C
+#define SUBUSBCKCR 0xe6150080
+#define SPUCKCR    0xe6150084
+#define MSUCKCR    0xe6150088
+#define MVI3CKCR   0xe6150090
+#define HDMICKCR   0xe6150094
+#define MFCK1CR    0xe6150098
+#define MFCK2CR    0xe615009C
+#define DSITCKCR   0xe6150060
+#define DSIPCKCR   0xe6150064
+#define SMSTPCR0   0xe6150130
+#define SMSTPCR1   0xe6150134
+#define SMSTPCR2   0xe6150138
+#define SMSTPCR3   0xe615013C
+#define SMSTPCR4   0xe6150140
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTALC1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7377_extalc1_clk = {
+        .rate           = 26666666,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7377_extal2_clk = {
+        .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+        .recalc         = div2_recalc,
+};
+
+/* Divide extalc1 by two */
+static struct clk extalc1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7377_extalc1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh7377_extal2_clk,
+};
+
+/* Divide extal2 by four */
+static struct clk extal2_div4_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &extal2_div2_clk,
+};
+
+/* PLLC1 */
+static unsigned long pllc1_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLC1CR) & (1 << 14))
+                mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc1_clk_ops = {
+        .recalc         = pllc1_recalc,
+};
+
+static struct clk pllc1_clk = {
+        .ops            = &pllc1_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &extalc1_div2_clk,
+};
+
+/* Divide PLLC1 by two */
+static struct clk pllc1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &pllc1_clk,
+};
+
+/* PLLC2 */
+static unsigned long pllc2_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLC2CR) & (1 << 31))
+                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc2_clk_ops = {
+        .recalc         = pllc2_recalc,
+};
+
+static struct clk pllc2_clk = {
+        .ops            = &pllc2_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &extalc1_div2_clk,
+};
+
+static struct clk *main_clks[] = {
+        &r_clk,
+        &sh7377_extalc1_clk,
+        &sh7377_extal2_clk,
+        &extalc1_div2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &pllc1_clk,
+        &pllc1_div2_clk,
+        &pllc2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in SYFRQCR to update hardware setting */
+        value = __raw_readl(SYFRQCR);
+        value |= (1 << 31);
+        __raw_writel(value, SYFRQCR);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                          24, 32, 36, 48, 0, 72, 96, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
+       DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
+       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
+        [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
+        [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
+        [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
+        [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
+        [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
+        [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
+        [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
+        [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
+       DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
+       DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
+       DIV6_NR };
+
+static struct clk div6_clks[] = {
+        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
+        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
+        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
+        [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
+        [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
+        [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
+        [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
+        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
+        [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
+        [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
+        [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
+        [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
+        [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
+        [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
+        [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
+};
+
+enum { MSTP001,
+       MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
+       MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
+       MSTP315, MSTP314, MSTP313,
+       MSTP403,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[] = {
+        [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
+        [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
+        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
+        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
+        [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
+        [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
+        [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
+        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+        [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
+        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
+        [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
+        [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
+        [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("r_clk", &r_clk),
+        CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
+        CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
+        CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
+        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
+        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
+        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
+        CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
+        CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
+        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
+        CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
+        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+        CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
+        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
+        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
+        CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
+        CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
+        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
+        CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
+        CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
+        CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
+        CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
+        CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
+        CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
+        CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
+
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
+        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
+        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
+        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
+        CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+};
+
+void __init sh7377_clock_init(void)
+{
+        int k, ret = 0;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup sh7377 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
new file mode 100644
index 000000000000..720a71433be6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -0,0 +1,356 @@
+/*
+ * sh73a0 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+#define FRQCRA          0xe6150000
+#define FRQCRB          0xe6150004
+#define FRQCRD          0xe61500e4
+#define VCLKCR1         0xe6150008
+#define VCLKCR2         0xe615000C
+#define VCLKCR3         0xe615001C
+#define ZBCKCR          0xe6150010
+#define FLCKCR          0xe6150014
+#define SD0CKCR         0xe6150074
+#define SD1CKCR         0xe6150078
+#define SD2CKCR         0xe615007C
+#define FSIACKCR        0xe6150018
+#define FSIBCKCR        0xe6150090
+#define SUBCKCR         0xe6150080
+#define SPUACKCR        0xe6150084
+#define SPUVCKCR        0xe6150094
+#define MSUCKCR         0xe6150088
+#define HSICKCR         0xe615008C
+#define MFCK1CR         0xe6150098
+#define MFCK2CR         0xe615009C
+#define DSITCKCR        0xe6150060
+#define DSI0PCKCR       0xe6150064
+#define DSI1PCKCR       0xe6150068
+#define DSI0PHYCR       0xe615006C
+#define DSI1PHYCR       0xe6150070
+#define PLLECR          0xe61500d0
+#define PLL0CR          0xe61500d8
+#define PLL1CR          0xe6150028
+#define PLL2CR          0xe615002c
+#define PLL3CR          0xe61500dc
+#define SMSTPCR0        0xe6150130
+#define SMSTPCR1        0xe6150134
+#define SMSTPCR2        0xe6150138
+#define SMSTPCR3        0xe615013c
+#define SMSTPCR4        0xe6150140
+#define SMSTPCR5        0xe6150144
+#define CKSCR           0xe61500c0
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh73a0_extal1_clk = {
+        .rate           = 26000000,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh73a0_extal2_clk = {
+        .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+        .recalc         = div2_recalc,
+};
+
+/* Divide extal1 by two */
+static struct clk extal1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh73a0_extal1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh73a0_extal2_clk,
+};
+
+static struct clk_ops main_clk_ops = {
+        .recalc         = followparent_recalc,
+};
+
+/* Main clock */
+static struct clk main_clk = {
+        .ops            = &main_clk_ops,
+};
+
+/* PLL0, PLL1, PLL2, PLL3 */
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
+                mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll0_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL0CR,
+        .enable_bit     = 0,
+};
+
+static struct clk pll1_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL1CR,
+        .enable_bit     = 1,
+};
+
+static struct clk pll2_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL2CR,
+        .enable_bit     = 2,
+};
+
+static struct clk pll3_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL3CR,
+        .enable_bit     = 3,
+};
+
+/* Divide PLL1 by two */
+static struct clk pll1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &pll1_clk,
+};
+
+static struct clk *main_clks[] = {
+        &r_clk,
+        &sh73a0_extal1_clk,
+        &sh73a0_extal2_clk,
+        &extal1_div2_clk,
+        &extal2_div2_clk,
+        &main_clk,
+        &pll0_clk,
+        &pll1_clk,
+        &pll2_clk,
+        &pll3_clk,
+        &pll1_div2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = __raw_readl(FRQCRB);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRB);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                          24, 0, 36, 48, 7 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+        SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
+        [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
+        [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
+        [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
+        [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
+        [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
+        [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
+        DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
+        DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
+        DIV6_HSI,  DIV6_MFG1, DIV6_MFG2,
+        DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
+        DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
+        [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
+        [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
+        [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
+        [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
+        [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
+        [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
+        [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
+        [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
+        [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
+        [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
+        [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
+        [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
+        [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
+        [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
+        [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
+        [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
+        [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
+        [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
+};
+
+enum { MSTP001,
+        MSTP125, MSTP116,
+        MSTP219,
+        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+        MSTP331, MSTP329, MSTP323, MSTP312,
+        MSTP411, MSTP410, MSTP403,
+        MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+        SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+        [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
+        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+        [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
+        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
+        [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
+        [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("r_clk", &r_clk),
+
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
+        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
+        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
+        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+};
+
+void __init sh73a0_clock_init(void)
+{
+        int k, ret = 0;
+
+        /* detect main clock parent */
+        switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
+        case 0:
+                main_clk.parent = &sh73a0_extal1_clk;
+                break;
+        case 1:
+                main_clk.parent = &extal1_div2_clk;
+                break;
+        case 2:
+                main_clk.parent = &sh73a0_extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup sh73a0 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
new file mode 100644
index 000000000000..6b7c7c42bc8f
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock.c
@@ -0,0 +1,46 @@
+/*
+ * SH-Mobile Clock Framework
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sh_clk.h>
+
+int __init clk_init(void)
+{
+        /* Kick the child clocks.. */
+        recalculate_root_clocks();
+
+        /* Enable the necessary init clocks */
+        clk_enable_init_clocks();
+
+        return 0;
+}
+
+int __clk_get(struct clk *clk)
+{
+        return 1;
+}
+EXPORT_SYMBOL(__clk_get);
+
+void __clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(__clk_put);
diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c
new file mode 100644
index 000000000000..9411a5bf4fd6
--- /dev/null
+++ b/arch/arm/mach-shmobile/console.c
@@ -0,0 +1,31 @@
+/*
+ * SH-Mobile Console
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <mach/common.h>
+#include <asm/mach/map.h>
+
+void __init shmobile_setup_console(void)
+{
+        parse_early_param();
+
+        /* Let earlyprintk output early console messages */
+        early_platform_driver_probe("earlyprintk", 1, 1);
+}
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
new file mode 100644
index 000000000000..e20239b08c83
--- /dev/null
+++ b/arch/arm/mach-shmobile/entry-gic.S
@@ -0,0 +1,18 @@
+/*
+ * ARM Interrupt demux handler using GIC
+ *
+ * Copyright (C) 2010 Magnus Damm
+ * Copyright (C) 2011 Paul Mundt
+ * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/assembler.h>
+#include <asm/entry-macro-multi.S>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+        arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
new file mode 100644
index 000000000000..cac0a7ae2084
--- /dev/null
+++ b/arch/arm/mach-shmobile/entry-intc.S
@@ -0,0 +1,57 @@
+/*
+ * ARM Interrupt demux handler using INTC
+ *
+ * Copyright (C) 2010 Magnus Damm
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/entry-macro-multi.S>
+
+#define INTCA_BASE      0xe6980000
+#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
+#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
+#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
+#define INTLVLB_OFFS    0x00000034 /* previous priority level */
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =INTCA_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        /* The single INTFLGA read access below results in the following:
+         *
+         * 1. INTLVLB is updated with old priority value from INTLVLA
+         * 2. Highest priority interrupt is accepted
+         * 3. INTLVLA is updated to contain priority of accepted interrupt
+         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
+         */
+        ldr     \irqnr, [\base, #INTFLGA_OFFS]
+
+        /* Restore INTLVLA with the value saved in INTLVLB.
+         * This is required to support interrupt priorities properly.
+         */
+        ldrb    \tmp, [\base, #INTLVLB_OFFS]
+        strb    \tmp, [\base, #INTLVLA_OFFS]
+
+        /* Handle invalid vector number case */
+        cmp     \irqnr, #0
+        beq     1000f
+
+        /* Convert vector to irq number, same as the evt2irq() macro */
+        lsr     \irqnr, \irqnr, #0x5
+        subs    \irqnr, \irqnr, #16
+
+1000:
+        .endm
+
+        .macro  test_for_ipi, irqnr, irqstat, base, tmp
+        .endm
+
+        .macro  test_for_ltirq, irqnr, irqstat, base, tmp
+        .endm
+
+        arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
new file mode 100644
index 000000000000..d4cec6b4c7d9
--- /dev/null
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -0,0 +1,27 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2010  Takashi Yoshii
+ *
+ * Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+
+        __INIT
+
+/*
+ * Reset vector for secondary CPUs.
+ * This will be mapped at address 0 by SBAR register.
+ * We need _long_ jump to the physical address.
+ */
+        .align  12
+ENTRY(shmobile_secondary_vector)
+        ldr     pc, 1f
+1:      .long   secondary_startup - PAGE_OFFSET + PHYS_OFFSET
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
new file mode 100644
index 000000000000..238a0d97d2d5
--- /dev/null
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -0,0 +1,41 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+        while (1) {
+                /*
+                 * here's the WFI
+                 */
+                asm(".word      0xe320f003\n"
+                    :
+                    :
+                    : "memory", "cc");
+        }
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h
new file mode 100644
index 000000000000..36d0163a857a
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+int __clk_get(struct clk *clk);
+void __clk_put(struct clk *clk);
+
+#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
new file mode 100644
index 000000000000..013ac0ee8256
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -0,0 +1,49 @@
+#ifndef __ARCH_MACH_COMMON_H
+#define __ARCH_MACH_COMMON_H
+
+extern struct sys_timer shmobile_timer;
+extern void shmobile_setup_console(void);
+extern void shmobile_secondary_vector(void);
+struct clk;
+extern int clk_init(void);
+extern void shmobile_handle_irq_intc(struct pt_regs *);
+extern void shmobile_handle_irq_gic(struct pt_regs *);
+
+extern void sh7367_init_irq(void);
+extern void sh7367_add_early_devices(void);
+extern void sh7367_add_standard_devices(void);
+extern void sh7367_clock_init(void);
+extern void sh7367_pinmux_init(void);
+extern struct clk sh7367_extalb1_clk;
+extern struct clk sh7367_extal2_clk;
+
+extern void sh7377_init_irq(void);
+extern void sh7377_add_early_devices(void);
+extern void sh7377_add_standard_devices(void);
+extern void sh7377_clock_init(void);
+extern void sh7377_pinmux_init(void);
+extern struct clk sh7377_extalc1_clk;
+extern struct clk sh7377_extal2_clk;
+
+extern void sh7372_init_irq(void);
+extern void sh7372_add_early_devices(void);
+extern void sh7372_add_standard_devices(void);
+extern void sh7372_clock_init(void);
+extern void sh7372_pinmux_init(void);
+extern struct clk sh7372_extal1_clk;
+extern struct clk sh7372_extal2_clk;
+
+extern void sh73a0_init_irq(void);
+extern void sh73a0_add_early_devices(void);
+extern void sh73a0_add_standard_devices(void);
+extern void sh73a0_clock_init(void);
+extern void sh73a0_pinmux_init(void);
+extern struct clk sh73a0_extal1_clk;
+extern struct clk sh73a0_extal2_clk;
+
+extern unsigned int sh73a0_get_core_count(void);
+extern void sh73a0_secondary_init(unsigned int cpu);
+extern int sh73a0_boot_secondary(unsigned int cpu);
+extern void sh73a0_smp_prepare_cpus(void);
+
+#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
new file mode 100644
index 000000000000..d791f10eeac7
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        .endm
+
+        .macro  test_for_ipi, irqnr, irqstat, base, tmp
+        .endm
+
+        .macro  test_for_ltirq, irqnr, irqstat, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
new file mode 100644
index 000000000000..2b1bb9e43dda
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * Generic GPIO API and pinmux table support
+ *
+ * Copyright (c) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+
+#define ARCH_NR_GPIOS 1024
+#include <linux/sh_pfc.h>
+
+#ifdef CONFIG_GPIOLIB
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return -ENOSYS;
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h
new file mode 100644
index 000000000000..99264a5ce5e4
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/hardware.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_MACH_HARDWARE_H
+#define __ASM_MACH_HARDWARE_H
+
+#endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
new file mode 100644
index 000000000000..e3ebfa73956e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -0,0 +1,87 @@
+LIST "partner-jet-setup.txt"
+LIST "(C) Copyright 2010 Renesas Solutions Corp"
+LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
+
+LIST "RWT Setting"
+EW 0xE6020004, 0xA500
+EW 0xE6030004, 0xA500
+
+DD 0x01001000, 0x01001000
+
+LIST "GPIO Setting"
+EB 0xE6051013, 0xA2
+
+LIST "CPG"
+ED 0xE6150080, 0x00000180
+ED 0xE61500C0, 0x00000002
+
+WAIT 1, 0xFE40009C
+
+LIST "FRQCR"
+ED 0xE6150000, 0x2D1305C3
+ED 0xE61500E0, 0x9E40358E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE61500E4, 0x00002000
+
+WAIT 1, 0xFE40009C
+
+LIST "PLL"
+ED 0xE6150028, 0x00004000
+
+WAIT 1, 0xFE40009C
+
+ED 0xE615002C, 0x93000040
+
+WAIT 1, 0xFE40009C
+
+LIST "BSC"
+ED 0xFEC10000, 0x00E0001B
+
+LIST "SBSC1"
+ED 0xFE400354, 0x01AD8000
+ED 0xFE400354, 0x01AD8001
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400008, 0xBCC90151
+ED 0xFE400040, 0x41774113
+ED 0xFE400044, 0x2712E229
+ED 0xFE400048, 0x20C18505
+ED 0xFE40004C, 0x00110209
+ED 0xFE400010, 0x00000087
+
+WAIT 10, 0xFE40009C
+
+ED 0xFE400084, 0x0000003F
+EB 0xFE500000, 0x00
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400084, 0x0000FF0A
+EB 0xFE500000, 0x00
+
+WAIT 1, 0xFE40009C
+
+ED 0xFE400084, 0x00002201
+EB 0xFE500000, 0x00
+ED 0xFE400084, 0x00000302
+EB 0xFE500000, 0x00
+EB 0xFE5C0000, 0x00
+ED 0xFE400008, 0xBCC90159
+ED 0xFE40008C, 0x88800004
+ED 0xFE400094, 0x00000004
+ED 0xFE400028, 0xA55A0032
+ED 0xFE40002C, 0xA55A000C
+ED 0xFE400020, 0xA55A2048
+ED 0xFE400008, 0xBCC90959
+
+LIST "Change CPGA setting"
+ED 0xE61500E0, 0x9E40352E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE6150354, 0x00000002
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
new file mode 100644
index 000000000000..e3ebfa73956e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -0,0 +1,87 @@
+LIST "partner-jet-setup.txt"
+LIST "(C) Copyright 2010 Renesas Solutions Corp"
+LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
+
+LIST "RWT Setting"
+EW 0xE6020004, 0xA500
+EW 0xE6030004, 0xA500
+
+DD 0x01001000, 0x01001000
+
+LIST "GPIO Setting"
+EB 0xE6051013, 0xA2
+
+LIST "CPG"
+ED 0xE6150080, 0x00000180
+ED 0xE61500C0, 0x00000002
+
+WAIT 1, 0xFE40009C
+
+LIST "FRQCR"
+ED 0xE6150000, 0x2D1305C3
+ED 0xE61500E0, 0x9E40358E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE61500E4, 0x00002000
+
+WAIT 1, 0xFE40009C
+
+LIST "PLL"
+ED 0xE6150028, 0x00004000
+
+WAIT 1, 0xFE40009C
+
+ED 0xE615002C, 0x93000040
+
+WAIT 1, 0xFE40009C
+
+LIST "BSC"
+ED 0xFEC10000, 0x00E0001B
+
+LIST "SBSC1"
+ED 0xFE400354, 0x01AD8000
+ED 0xFE400354, 0x01AD8001
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400008, 0xBCC90151
+ED 0xFE400040, 0x41774113
+ED 0xFE400044, 0x2712E229
+ED 0xFE400048, 0x20C18505
+ED 0xFE40004C, 0x00110209
+ED 0xFE400010, 0x00000087
+
+WAIT 10, 0xFE40009C
+
+ED 0xFE400084, 0x0000003F
+EB 0xFE500000, 0x00
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400084, 0x0000FF0A
+EB 0xFE500000, 0x00
+
+WAIT 1, 0xFE40009C
+
+ED 0xFE400084, 0x00002201
+EB 0xFE500000, 0x00
+ED 0xFE400084, 0x00000302
+EB 0xFE500000, 0x00
+EB 0xFE5C0000, 0x00
+ED 0xFE400008, 0xBCC90159
+ED 0xFE40008C, 0x88800004
+ED 0xFE400094, 0x00000004
+ED 0xFE400028, 0xA55A0032
+ED 0xFE40002C, 0xA55A000C
+ED 0xFE400020, 0xA55A2048
+ED 0xFE400008, 0xBCC90959
+
+LIST "Change CPGA setting"
+ED 0xE61500E0, 0x9E40352E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE6150354, 0x00000002
diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
new file mode 100644
index 000000000000..7339fe46cb7c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/io.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_IO_H
+#define __ASM_MACH_IO_H
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
new file mode 100644
index 000000000000..dcb714f4d75a
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS         1024
+
+/* GIC */
+#define gic_spi(nr)             ((nr) + 32)
+
+/* INTCA */
+#define evt2irq(evt)            (((evt) >> 5) - 16)
+#define irq2evt(irq)            (((irq) + 16) << 5)
+
+/* INTCS */
+#define INTCS_VECT_BASE         0x2200
+#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
new file mode 100644
index 000000000000..377584e57e03
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/memory.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_MACH_MEMORY_H
+#define __ASM_MACH_MEMORY_H
+
+#define PHYS_OFFSET     UL(CONFIG_MEMORY_START)
+#define MEM_SIZE        UL(CONFIG_MEMORY_SIZE)
+
+/* DMA memory at 0xf6000000 - 0xffdfffff */
+#define CONSISTENT_DMA_SIZE (158 << 20)
+
+#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h
new file mode 100644
index 000000000000..52d0de686f68
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh7367.h
@@ -0,0 +1,332 @@
+#ifndef __ASM_SH7367_H__
+#define __ASM_SH7367_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* 49-1 -> 49-6 (GPIO) */
+        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+
+        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+
+        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+
+        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+        GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+        GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
+
+        /* Special Pull-up / Pull-down Functions */
+        GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
+        GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
+        GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
+        GPIO_FN_PORT58_KEYIN6_PU,
+
+        /* 49-1 (FN) */
+        GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
+        GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
+        GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
+        GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
+        GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
+        GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
+        GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
+        GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
+        GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
+        GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
+        GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
+        GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
+        GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+        GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
+        GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
+
+        /* 49-2 (FN) */
+        GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
+        GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
+        GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
+        GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
+        GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
+        GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
+        GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
+        GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
+        GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
+        GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
+        GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
+        GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
+        GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
+        GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
+        GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
+        GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
+        GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
+        GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
+        GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
+        GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
+        GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
+        GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
+        GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
+        GPIO_FN_XTALB1L,
+        GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
+        GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
+        GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
+        GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
+        GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
+        GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
+        GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
+        GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
+        GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
+        GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
+        GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
+        GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
+        GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
+        GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
+        GPIO_FN_NMI, GPIO_FN_TPU4TO0,
+        GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
+        GPIO_FN_IRQ_TMPB,
+        GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
+        GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
+        GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
+
+        /* 49-3 (FN) */
+        GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
+        GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
+        GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
+        GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
+        GPIO_FN_SCIFA5_RXD,
+        GPIO_FN_SCIFA5_TXD,
+        GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
+        GPIO_FN_A0_EA0, GPIO_FN_BS,
+        GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
+        GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
+        GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
+        GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
+        GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
+        GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
+        GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
+        GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
+        GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
+        GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
+        GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
+        GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
+        GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
+        GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
+        GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
+        GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
+        GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
+        GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
+        GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
+        GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
+        GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
+        GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
+        GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
+        GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
+        GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
+        GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
+        GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
+        GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
+
+        /* 49-4 (FN) */
+        GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
+        GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
+        GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
+        GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
+        GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
+        GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
+        GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
+        GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
+        GPIO_FN_VIO_CKO,
+        GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
+        GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
+        GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
+        GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
+        GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
+        GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
+        GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
+        GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
+        GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
+        GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
+        GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
+        GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
+        GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
+        GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
+        GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
+        GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
+        GPIO_FN_LCDD6, GPIO_FN_DV_D6,
+        GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
+        GPIO_FN_LCDD7, GPIO_FN_DV_D7,
+        GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
+        GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
+        GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
+        GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
+        GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
+        GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
+        GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
+        GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
+        GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
+        GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
+        GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
+        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
+        GPIO_FN_D26, GPIO_FN_ED26,
+        GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
+        GPIO_FN_D27, GPIO_FN_ED27,
+        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
+        GPIO_FN_D28, GPIO_FN_ED28,
+        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
+        GPIO_FN_D29, GPIO_FN_ED29,
+        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
+        GPIO_FN_D30, GPIO_FN_ED30,
+        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
+        GPIO_FN_D31, GPIO_FN_ED31,
+        GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
+        GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
+
+
+        /* 49-5 (FN) */
+        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
+        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
+        GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
+        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
+        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
+        GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
+        GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
+        GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
+        GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
+        GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
+        GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
+        GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
+        GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
+        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
+        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
+        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
+        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
+        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
+        GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
+        GPIO_FN_MSIOF1_SS2,
+        GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
+        GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
+        GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
+        GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
+        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
+        GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
+        GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
+        GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
+        GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
+        GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
+        GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
+        GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
+        GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
+        GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+        GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
+        GPIO_FN_SDHICD0,
+        GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
+        GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
+        GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
+        GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
+
+        /* 49-6 (FN) */
+        GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
+        GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
+        GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
+        GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
+        GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
+        GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
+        GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
+        GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
+        GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
+        GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
+        GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
+        GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
+        GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
+        GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
+        GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
+        GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
+        GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
+        GPIO_FN_SDHICMD2,
+        GPIO_FN_RESETOUTS,
+        GPIO_FN_DIVLOCK,
+};
+
+#endif /* __ASM_SH7367_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
new file mode 100644
index 000000000000..5736efcca60c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -0,0 +1,472 @@
+/*
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_SH7372_H__
+#define __ASM_SH7372_H__
+
+#include <linux/sh_clk.h>
+
+/*
+ * Pin Function Controller:
+ *      GPIO_FN_xx - GPIO used to select pin function
+ *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* PORT */
+        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+
+        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+
+        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+
+        GPIO_PORT190,
+
+        /* IRQ */
+        GPIO_FN_IRQ0_6,         /* PORT   6 */
+        GPIO_FN_IRQ0_162,       /* PORT 162 */
+        GPIO_FN_IRQ1,           /* PORT  12 */
+        GPIO_FN_IRQ2_4,         /* PORT   4 */
+        GPIO_FN_IRQ2_5,         /* PORT   5 */
+        GPIO_FN_IRQ3_8,         /* PORT   8 */
+        GPIO_FN_IRQ3_16,        /* PORT  16 */
+        GPIO_FN_IRQ4_17,        /* PORT  17 */
+        GPIO_FN_IRQ4_163,       /* PORT 163 */
+        GPIO_FN_IRQ5,           /* PORT  18 */
+        GPIO_FN_IRQ6_39,        /* PORT  39 */
+        GPIO_FN_IRQ6_164,       /* PORT 164 */
+        GPIO_FN_IRQ7_40,        /* PORT  40 */
+        GPIO_FN_IRQ7_167,       /* PORT 167 */
+        GPIO_FN_IRQ8_41,        /* PORT  41 */
+        GPIO_FN_IRQ8_168,       /* PORT 168 */
+        GPIO_FN_IRQ9_42,        /* PORT  42 */
+        GPIO_FN_IRQ9_169,       /* PORT 169 */
+        GPIO_FN_IRQ10,          /* PORT  65 */
+        GPIO_FN_IRQ11,          /* PORT  67 */
+        GPIO_FN_IRQ12_80,       /* PORT  80 */
+        GPIO_FN_IRQ12_137,      /* PORT 137 */
+        GPIO_FN_IRQ13_81,       /* PORT  81 */
+        GPIO_FN_IRQ13_145,      /* PORT 145 */
+        GPIO_FN_IRQ14_82,       /* PORT  82 */
+        GPIO_FN_IRQ14_146,      /* PORT 146 */
+        GPIO_FN_IRQ15_83,       /* PORT  83 */
+        GPIO_FN_IRQ15_147,      /* PORT 147 */
+        GPIO_FN_IRQ16_84,       /* PORT  84 */
+        GPIO_FN_IRQ16_170,      /* PORT 170 */
+        GPIO_FN_IRQ17,          /* PORT  85 */
+        GPIO_FN_IRQ18,          /* PORT  86 */
+        GPIO_FN_IRQ19,          /* PORT  87 */
+        GPIO_FN_IRQ20,          /* PORT  92 */
+        GPIO_FN_IRQ21,          /* PORT  93 */
+        GPIO_FN_IRQ22,          /* PORT  94 */
+        GPIO_FN_IRQ23,          /* PORT  95 */
+        GPIO_FN_IRQ24,          /* PORT 112 */
+        GPIO_FN_IRQ25,          /* PORT 119 */
+        GPIO_FN_IRQ26_121,      /* PORT 121 */
+        GPIO_FN_IRQ26_172,      /* PORT 172 */
+        GPIO_FN_IRQ27_122,      /* PORT 122 */
+        GPIO_FN_IRQ27_180,      /* PORT 180 */
+        GPIO_FN_IRQ28_123,      /* PORT 123 */
+        GPIO_FN_IRQ28_181,      /* PORT 181 */
+        GPIO_FN_IRQ29_129,      /* PORT 129 */
+        GPIO_FN_IRQ29_182,      /* PORT 182 */
+        GPIO_FN_IRQ30_130,      /* PORT 130 */
+        GPIO_FN_IRQ30_183,      /* PORT 183 */
+        GPIO_FN_IRQ31_138,      /* PORT 138 */
+        GPIO_FN_IRQ31_184,      /* PORT 184 */
+
+        /*
+         * MSIOF0       (PORT 36, 37, 38, 39
+         *                    40, 41, 42, 43, 44, 45)
+         */
+        GPIO_FN_MSIOF0_TSYNC,   GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_MSIOF0_MCK1,    GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_MSIOF0_SS2,     GPIO_FN_MSIOF0_TXD,
+
+        /*
+         * MSIOF1       (PORT 39, 40, 41, 42, 43, 44
+         *                    84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
+         */
+        GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
+        GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
+        GPIO_FN_MSIOF1_TXD_41,  GPIO_FN_MSIOF1_RXD_42,
+        GPIO_FN_MSIOF1_TXD_90,  GPIO_FN_MSIOF1_RXD_91,
+        GPIO_FN_MSIOF1_SS1_43,  GPIO_FN_MSIOF1_SS2_44,
+        GPIO_FN_MSIOF1_SS1_92,  GPIO_FN_MSIOF1_SS2_93,
+        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
+        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
+
+        /*
+         * MSIOF2       (PORT 134, 135, 136, 137, 138, 139
+         *                    148, 149, 150, 151)
+         */
+        GPIO_FN_MSIOF2_RSCK,    GPIO_FN_MSIOF2_RSYNC,
+        GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_MSIOF2_SS1,     GPIO_FN_MSIOF2_SS2,
+        GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_TSCK,
+        GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TXD,
+
+        /* MSIOF3       (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
+        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TSYNC,
+        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_TXD,
+        GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
+        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BB_RX_FLOW_N,
+
+        /* MSIOF4       (PORT 0, 1, 2, 3) */
+        GPIO_FN_BBIF2_TSCK1,    GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_BBIF2_TXD1,     GPIO_FN_BBIF2_RXD,
+
+        /* FSI          (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
+        GPIO_FN_FSIACK,         GPIO_FN_FSIBCK,
+        GPIO_FN_FSIAILR,        GPIO_FN_FSIAIBT,
+        GPIO_FN_FSIAISLD,       GPIO_FN_FSIAOMC,
+        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
+        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIASPDIF_11,
+        GPIO_FN_FSIASPDIF_15,
+
+        /* FMSI         (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
+        GPIO_FN_FMSOCK,         GPIO_FN_FMSOOLR,
+        GPIO_FN_FMSIOLR,        GPIO_FN_FMSOOBT,
+        GPIO_FN_FMSIOBT,        GPIO_FN_FMSOSLD,
+        GPIO_FN_FMSOILR,        GPIO_FN_FMSIILR,
+        GPIO_FN_FMSOIBT,        GPIO_FN_FMSIIBT,
+        GPIO_FN_FMSISLD,        GPIO_FN_FMSICK,
+
+        /* SCIFA0       (PORT 152, 153, 156, 157, 158) */
+        GPIO_FN_SCIFA0_TXD,     GPIO_FN_SCIFA0_RXD,
+        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_RTS,
+        GPIO_FN_SCIFA0_CTS,
+
+        /* SCIFA1       (PORT 154, 155, 159, 160, 161) */
+        GPIO_FN_SCIFA1_TXD,     GPIO_FN_SCIFA1_RXD,
+        GPIO_FN_SCIFA1_SCK,     GPIO_FN_SCIFA1_RTS,
+        GPIO_FN_SCIFA1_CTS,
+
+        /* SCIFA2       (PORT 94, 95, 96, 97, 98) */
+        GPIO_FN_SCIFA2_CTS1,    GPIO_FN_SCIFA2_RTS1,
+        GPIO_FN_SCIFA2_TXD1,    GPIO_FN_SCIFA2_RXD1,
+        GPIO_FN_SCIFA2_SCK1,
+
+        /* SCIFA3       (PORT 43, 44,
+                             140, 141, 142, 143, 144) */
+        GPIO_FN_SCIFA3_CTS_43,  GPIO_FN_SCIFA3_CTS_140,
+        GPIO_FN_SCIFA3_RTS_44,  GPIO_FN_SCIFA3_RTS_141,
+        GPIO_FN_SCIFA3_SCK,     GPIO_FN_SCIFA3_TXD,
+        GPIO_FN_SCIFA3_RXD,
+
+        /* SCIFA4       (PORT 5, 6) */
+        GPIO_FN_SCIFA4_RXD,     GPIO_FN_SCIFA4_TXD,
+
+        /* SCIFA5       (PORT 8, 12) */
+        GPIO_FN_SCIFA5_RXD,     GPIO_FN_SCIFA5_TXD,
+
+        /* SCIFB        (PORT 162, 163, 164, 165, 166) */
+        GPIO_FN_SCIFB_SCK,      GPIO_FN_SCIFB_RTS,
+        GPIO_FN_SCIFB_CTS,      GPIO_FN_SCIFB_TXD,
+        GPIO_FN_SCIFB_RXD,
+
+        /*
+         * CEU          (PORT 16, 17,
+         *                    100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
+         *                    110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
+         *                    120)
+         */
+        GPIO_FN_VIO_HD,         GPIO_FN_VIO_CKO1,       GPIO_FN_VIO_CKO2,
+        GPIO_FN_VIO_VD,         GPIO_FN_VIO_CLK,        GPIO_FN_VIO_FIELD,
+        GPIO_FN_VIO_CKO,
+        GPIO_FN_VIO_D0,         GPIO_FN_VIO_D1,         GPIO_FN_VIO_D2,
+        GPIO_FN_VIO_D3,         GPIO_FN_VIO_D4,         GPIO_FN_VIO_D5,
+        GPIO_FN_VIO_D6,         GPIO_FN_VIO_D7,         GPIO_FN_VIO_D8,
+        GPIO_FN_VIO_D9,         GPIO_FN_VIO_D10,        GPIO_FN_VIO_D11,
+        GPIO_FN_VIO_D12,        GPIO_FN_VIO_D13,        GPIO_FN_VIO_D14,
+        GPIO_FN_VIO_D15,
+
+        /* USB0         (PORT 113, 114, 115, 116, 117, 167) */
+        GPIO_FN_IDIN_0,         GPIO_FN_EXTLP_0,
+        GPIO_FN_OVCN2_0,        GPIO_FN_PWEN_0,
+        GPIO_FN_OVCN_0,         GPIO_FN_VBUS0_0,
+
+        /* USB1         (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
+        GPIO_FN_IDIN_1_18,      GPIO_FN_IDIN_1_113,
+        GPIO_FN_PWEN_1_115,     GPIO_FN_PWEN_1_138,
+        GPIO_FN_OVCN_1_114,     GPIO_FN_OVCN_1_162,
+        GPIO_FN_EXTLP_1,        GPIO_FN_OVCN2_1,
+        GPIO_FN_VBUS0_1,
+
+        /* GPIO         (PORT 41, 42, 43, 44) */
+        GPIO_FN_GPI0,   GPIO_FN_GPI1,   GPIO_FN_GPO0,   GPIO_FN_GPO1,
+
+        /*
+         * BSC          (PORT 19,
+         *                    20, 21, 22, 25, 26, 27, 28, 29,
+         *                    30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
+         *                    40, 41, 42, 43, 44, 45,
+         *                    62, 63, 64, 65, 66, 67,
+         *                    71, 72, 74, 75)
+         */
+        GPIO_FN_BS,     GPIO_FN_WE1,
+        GPIO_FN_CKO,    GPIO_FN_WAIT,   GPIO_FN_RDWR,
+
+        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
+        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
+        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
+        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
+        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
+        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
+        GPIO_FN_A26,
+
+        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
+        GPIO_FN_CS5A,   GPIO_FN_CS5B,   GPIO_FN_CS6A,
+
+        /*
+         * BSC/FLCTL            (PORT 23, 24,
+         *                            46, 47, 48, 49,
+         *                            50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
+         *                            60, 61, 69, 70)
+         */
+        GPIO_FN_RD_FSC,         GPIO_FN_WE0_FWE,
+        GPIO_FN_A4_FOE,         GPIO_FN_A5_FCDE,
+        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        GPIO_FN_D2_NAF2,
+        GPIO_FN_D3_NAF3,        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,
+        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        GPIO_FN_D8_NAF8,
+        GPIO_FN_D9_NAF9,        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,
+        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
+        GPIO_FN_D15_NAF15,
+
+        /*
+         * MMCIF(1)             (PORT 84, 85, 86, 87, 88, 89,
+         *                            90, 91, 92, 99)
+         */
+        GPIO_FN_MMCD0_0,        GPIO_FN_MMCD0_1,        GPIO_FN_MMCD0_2,
+        GPIO_FN_MMCD0_3,        GPIO_FN_MMCD0_4,        GPIO_FN_MMCD0_5,
+        GPIO_FN_MMCD0_6,        GPIO_FN_MMCD0_7,
+        GPIO_FN_MMCCMD0,        GPIO_FN_MMCCLK0,
+
+        /* MMCIF(2)             (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
+        GPIO_FN_MMCD1_0,        GPIO_FN_MMCD1_1,        GPIO_FN_MMCD1_2,
+        GPIO_FN_MMCD1_3,        GPIO_FN_MMCD1_4,        GPIO_FN_MMCD1_5,
+        GPIO_FN_MMCD1_6,        GPIO_FN_MMCD1_7,
+        GPIO_FN_MMCCLK1,        GPIO_FN_MMCCMD1,
+
+        /* SPU2         (PORT 65) */
+        GPIO_FN_VINT_I,
+
+        /* FLCTL        (PORT 66, 68, 73) */
+        GPIO_FN_FCE1,   GPIO_FN_FCE0,   GPIO_FN_FRB,
+
+        /* HSI          (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
+        GPIO_FN_GP_RX_FLAG,     GPIO_FN_GP_RX_DATA,     GPIO_FN_GP_TX_READY,
+        GPIO_FN_GP_RX_WAKE,     GPIO_FN_MP_TX_FLAG,     GPIO_FN_MP_TX_DATA,
+        GPIO_FN_MP_RX_READY,    GPIO_FN_MP_TX_WAKE,
+
+        /*
+         * MFI          (PORT 76, 77, 78, 79,
+         *                    80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
+         *                    90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
+         */
+        GPIO_FN_MFIv6,  /* see MSEL4CR 6 */
+        GPIO_FN_MFIv4,  /* see MSEL4CR 6 */
+
+        GPIO_FN_MEMC_CS0,               GPIO_FN_MEMC_BUSCLK_MEMC_A0,
+        GPIO_FN_MEMC_CS1_MEMC_A1,       GPIO_FN_MEMC_ADV_MEMC_DREQ0,
+        GPIO_FN_MEMC_WAIT_MEMC_DREQ1,   GPIO_FN_MEMC_NOE,
+        GPIO_FN_MEMC_NWE,               GPIO_FN_MEMC_INT,
+
+        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
+        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
+        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
+        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
+        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
+        GPIO_FN_MEMC_AD15,
+
+        /* SIM          (PORT 94, 95, 98) */
+        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,        GPIO_FN_SIM_D,
+
+        /* TPU          (PORT 93, 99, 112, 160, 161) */
+        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
+        GPIO_FN_TPU0TO2_93,     GPIO_FN_TPU0TO2_99,
+        GPIO_FN_TPU0TO3,
+
+        /* I2C2         (PORT 110, 111) */
+        GPIO_FN_I2C_SCL2,       GPIO_FN_I2C_SDA2,
+
+        /* I2C3(1)      (PORT 114, 115) */
+        GPIO_FN_I2C_SCL3,       GPIO_FN_I2C_SDA3,
+
+        /* I2C3(2)      (PORT 137, 145) */
+        GPIO_FN_I2C_SCL3S,      GPIO_FN_I2C_SDA3S,
+
+        /* I2C4(2)      (PORT 116, 117) */
+        GPIO_FN_I2C_SCL4,       GPIO_FN_I2C_SDA4,
+
+        /* I2C4(2)      (PORT 146, 147) */
+        GPIO_FN_I2C_SCL4S,      GPIO_FN_I2C_SDA4S,
+
+        /*
+         * KEYSC        (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
+         *                    130, 131, 132, 133, 134, 135, 136)
+         */
+        GPIO_FN_KEYOUT0,        GPIO_FN_KEYIN0_121,     GPIO_FN_KEYIN0_136,
+        GPIO_FN_KEYOUT1,        GPIO_FN_KEYIN1_122,     GPIO_FN_KEYIN1_135,
+        GPIO_FN_KEYOUT2,        GPIO_FN_KEYIN2_123,     GPIO_FN_KEYIN2_134,
+        GPIO_FN_KEYOUT3,        GPIO_FN_KEYIN3_124,     GPIO_FN_KEYIN3_133,
+        GPIO_FN_KEYOUT4,        GPIO_FN_KEYIN4,
+        GPIO_FN_KEYOUT5,        GPIO_FN_KEYIN5,
+        GPIO_FN_KEYOUT6,        GPIO_FN_KEYIN6,
+        GPIO_FN_KEYOUT7,        GPIO_FN_KEYIN7,
+
+        /*
+         * LCDC         (PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
+         *                    130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
+         *                    140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
+         *                    150, 151)
+         */
+        GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
+        GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
+        GPIO_FN_LCDHSYN,        GPIO_FN_LCDCS,  GPIO_FN_LCDVSYN,
+        GPIO_FN_LCDDCK,         GPIO_FN_LCDWR,  GPIO_FN_LCDRD,
+        GPIO_FN_LCDDISP,        GPIO_FN_LCDRS,  GPIO_FN_LCDLCLK,
+        GPIO_FN_LCDDON,
+
+        GPIO_FN_LCDD0,  GPIO_FN_LCDD1,  GPIO_FN_LCDD2,  GPIO_FN_LCDD3,
+        GPIO_FN_LCDD4,  GPIO_FN_LCDD5,  GPIO_FN_LCDD6,  GPIO_FN_LCDD7,
+        GPIO_FN_LCDD8,  GPIO_FN_LCDD9,  GPIO_FN_LCDD10, GPIO_FN_LCDD11,
+        GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
+        GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
+        GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
+
+        /* IRDA         (PORT 139, 140, 141, 142) */
+        GPIO_FN_IRDA_OUT,       GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_FIRSEL,
+        GPIO_FN_IROUT_139,      GPIO_FN_IROUT_140,
+
+        /* TSIF1        (PORT 156, 157, 158, 159) */
+        GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
+        GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
+        GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
+        GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
+
+        GPIO_FN_TS_SPSYNC1,     GPIO_FN_TS_SDAT1,
+        GPIO_FN_TS_SDEN1,       GPIO_FN_TS_SCK1,
+
+        /* TSIF2        (PORT 137, 145, 146, 147) */
+        GPIO_FN_TS_SPSYNC2,     GPIO_FN_TS_SDAT2,
+        GPIO_FN_TS_SDEN2,       GPIO_FN_TS_SCK2,
+
+        /* HDMI         (PORT 169, 170) */
+        GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
+
+        /* SDHI0        (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
+        GPIO_FN_SDHICLK0,       GPIO_FN_SDHICD0,
+        GPIO_FN_SDHICMD0,       GPIO_FN_SDHIWP0,
+        GPIO_FN_SDHID0_0,       GPIO_FN_SDHID0_1,
+        GPIO_FN_SDHID0_2,       GPIO_FN_SDHID0_3,
+
+        /* SDHI1        (PORT 179, 180, 181, 182, 183, 184) */
+        GPIO_FN_SDHICLK1,       GPIO_FN_SDHICMD1,       GPIO_FN_SDHID1_0,
+        GPIO_FN_SDHID1_1,       GPIO_FN_SDHID1_2,       GPIO_FN_SDHID1_3,
+
+        /* SDHI2        (PORT 185, 186, 187, 188, 189, 190) */
+        GPIO_FN_SDHICLK2,       GPIO_FN_SDHICMD2,       GPIO_FN_SDHID2_0,
+        GPIO_FN_SDHID2_1,       GPIO_FN_SDHID2_2,       GPIO_FN_SDHID2_3,
+
+        /* SDENC        see MSEL4CR 19 */
+        GPIO_FN_SDENC_CPG,
+        GPIO_FN_SDENC_DV_CLKI,
+};
+
+/* DMA slave IDs */
+enum {
+        SHDMA_SLAVE_SCIF0_TX,
+        SHDMA_SLAVE_SCIF0_RX,
+        SHDMA_SLAVE_SCIF1_TX,
+        SHDMA_SLAVE_SCIF1_RX,
+        SHDMA_SLAVE_SCIF2_TX,
+        SHDMA_SLAVE_SCIF2_RX,
+        SHDMA_SLAVE_SCIF3_TX,
+        SHDMA_SLAVE_SCIF3_RX,
+        SHDMA_SLAVE_SCIF4_TX,
+        SHDMA_SLAVE_SCIF4_RX,
+        SHDMA_SLAVE_SCIF5_TX,
+        SHDMA_SLAVE_SCIF5_RX,
+        SHDMA_SLAVE_SCIF6_TX,
+        SHDMA_SLAVE_SCIF6_RX,
+        SHDMA_SLAVE_SDHI0_RX,
+        SHDMA_SLAVE_SDHI0_TX,
+        SHDMA_SLAVE_SDHI1_RX,
+        SHDMA_SLAVE_SDHI1_TX,
+        SHDMA_SLAVE_SDHI2_RX,
+        SHDMA_SLAVE_SDHI2_TX,
+        SHDMA_SLAVE_MMCIF_RX,
+        SHDMA_SLAVE_MMCIF_TX,
+};
+
+extern struct clk sh7372_extal1_clk;
+extern struct clk sh7372_extal2_clk;
+extern struct clk sh7372_dv_clki_clk;
+extern struct clk sh7372_dv_clki_div2_clk;
+extern struct clk sh7372_pllc2_clk;
+extern struct clk sh7372_fsiack_clk;
+extern struct clk sh7372_fsibck_clk;
+extern struct clk sh7372_fsidiva_clk;
+extern struct clk sh7372_fsidivb_clk;
+
+#endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h
new file mode 100644
index 000000000000..f580e227dd1c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh7377.h
@@ -0,0 +1,360 @@
+#ifndef __ASM_SH7377_H__
+#define __ASM_SH7377_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* 55-1 -> 55-5 (GPIO) */
+        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+        GPIO_PORT128, GPIO_PORT129,
+
+        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+        GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+
+        /* Special Pull-up / Pull-down Functions */
+        GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU,
+        GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU,
+        GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU,
+        GPIO_FN_PORT72_KEYIN6_PU,
+
+        /* 55-1 (FN) */
+        GPIO_FN_VBUS_0,
+        GPIO_FN_CPORT0,
+        GPIO_FN_CPORT1,
+        GPIO_FN_CPORT2,
+        GPIO_FN_CPORT3,
+        GPIO_FN_CPORT4,
+        GPIO_FN_CPORT5,
+        GPIO_FN_CPORT6,
+        GPIO_FN_CPORT7,
+        GPIO_FN_CPORT8,
+        GPIO_FN_CPORT9,
+        GPIO_FN_CPORT10,
+        GPIO_FN_CPORT11, GPIO_FN_SIN2,
+        GPIO_FN_CPORT12, GPIO_FN_XCTS2,
+        GPIO_FN_CPORT13, GPIO_FN_RFSPO4,
+        GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
+        GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2,
+        GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3,
+        GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2,
+        GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2,
+        GPIO_FN_CPORT19_MPORT1,
+        GPIO_FN_CPORT20, GPIO_FN_RFSPO6,
+        GPIO_FN_CPORT21, GPIO_FN_STATUS0,
+        GPIO_FN_CPORT22, GPIO_FN_STATUS1,
+        GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
+        GPIO_FN_B_SYNLD1,
+        GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK,
+        GPIO_FN_XMAINPS,
+        GPIO_FN_XDIVPS,
+        GPIO_FN_XIDRST,
+        GPIO_FN_IDCLK, GPIO_FN_IC_DP,
+        GPIO_FN_IDIO, GPIO_FN_IC_DM,
+        GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT,
+        GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+        GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
+        GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
+        GPIO_FN_PCMCLKO,
+        GPIO_FN_SYNC8KO,
+
+        /* 55-2 (FN) */
+        GPIO_FN_DNPCM_A,
+        GPIO_FN_UPPCM_A,
+        GPIO_FN_VACK,
+        GPIO_FN_XTALB1L,
+        GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
+        GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
+        GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS,
+        GPIO_FN_GPS_IM,
+        GPIO_FN_GPS_IS,
+        GPIO_FN_GPS_QM,
+        GPIO_FN_GPS_QS,
+        GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
+        GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3,
+        GPIO_FN_FMSIOLR,
+        GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1,
+        GPIO_FN_FMSIOBT,
+        GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2,
+        GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
+        GPIO_FN_OPORT3, GPIO_FN_FMSIILR,
+        GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
+        GPIO_FN_FMSIIBT,
+        GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0,
+        GPIO_FN_A0_EA0, GPIO_FN_BS,
+        GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2,
+        GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2,
+        GPIO_FN_TPU0TO1,
+        GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5,
+        GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4,
+        GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+        GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+        GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD,
+        GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6,
+        GPIO_FN_D0_ED0_NAF0,
+        GPIO_FN_D1_ED1_NAF1,
+        GPIO_FN_D2_ED2_NAF2,
+        GPIO_FN_D3_ED3_NAF3,
+        GPIO_FN_D4_ED4_NAF4,
+        GPIO_FN_D5_ED5_NAF5,
+        GPIO_FN_D6_ED6_NAF6,
+        GPIO_FN_D7_ED7_NAF7,
+        GPIO_FN_D8_ED8_NAF8,
+        GPIO_FN_D9_ED9_NAF9,
+        GPIO_FN_D10_ED10_NAF10,
+        GPIO_FN_D11_ED11_NAF11,
+        GPIO_FN_D12_ED12_NAF12,
+        GPIO_FN_D13_ED13_NAF13,
+        GPIO_FN_D14_ED14_NAF14,
+        GPIO_FN_D15_ED15_NAF15,
+        GPIO_FN_CS4,
+        GPIO_FN_CS5A, GPIO_FN_FMSICK,
+        GPIO_FN_CS5B, GPIO_FN_FCE1,
+
+        /* 55-3 (FN) */
+        GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0,
+        GPIO_FN_FCE0,
+        GPIO_FN_WAIT, GPIO_FN_DREQ0,
+        GPIO_FN_RD_XRD,
+        GPIO_FN_WE0_XWR0_FWE,
+        GPIO_FN_WE1_XWR1,
+        GPIO_FN_FRB,
+        GPIO_FN_CKO,
+        GPIO_FN_NBRSTOUT,
+        GPIO_FN_NBRST,
+        GPIO_FN_GPS_EPPSIN,
+        GPIO_FN_LATCHPULSE,
+        GPIO_FN_LTESIGNAL,
+        GPIO_FN_LEGACYSTATE,
+        GPIO_FN_TCKON,
+        GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0,
+        GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1,
+        GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD,
+        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1,
+        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2,
+        GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC,
+        GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD,
+        GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK,
+        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2,
+        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3,
+        GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC,
+        GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR,
+        GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2,
+        GPIO_FN_PORT140_FSIAOBT,
+        GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3,
+        GPIO_FN_PORT141_FSIAOSLD,
+        GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK,
+        GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR,
+        GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT,
+        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD,
+        GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2,
+        GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5,
+        GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6,
+        GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1,
+        GPIO_FN_MFG0_IN2,
+        GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+        GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+        GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+        GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2,
+        GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD,
+
+        /* 55-4 (FN) */
+        GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0,
+        GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0,
+        GPIO_FN_MFG3_IN2,
+        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0,
+        GPIO_FN_MFG3_IN1,
+        GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0,
+        GPIO_FN_MFG3_OUT1,
+        GPIO_FN_TPU3TO0,
+        GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI,
+        GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS,
+        GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS,
+        GPIO_FN_BBIF2_TSCK1,
+        GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD,
+        GPIO_FN_BBIF2_TXD1,
+        GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD,
+        GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK,
+        GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1,
+        GPIO_FN_LCDD6, GPIO_FN_XWR2,
+        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
+        GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16,
+        GPIO_FN_ED16,
+        GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17,
+        GPIO_FN_ED17,
+        GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18,
+        GPIO_FN_ED18,
+        GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19,
+        GPIO_FN_ED19,
+        GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20,
+        GPIO_FN_ED20,
+        GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21,
+        GPIO_FN_ED21,
+        GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22,
+        GPIO_FN_ED22,
+        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0,
+        GPIO_FN_VIO_DR7,
+        GPIO_FN_D23, GPIO_FN_ED23,
+        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1,
+        GPIO_FN_VIO_VDR,
+        GPIO_FN_D24, GPIO_FN_ED24,
+        GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25,
+        GPIO_FN_ED25,
+        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+        GPIO_FN_ED26,
+        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27,
+        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+        GPIO_FN_ED28,
+        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+        GPIO_FN_ED29,
+        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+        GPIO_FN_ED30,
+        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+        GPIO_FN_ED31,
+        GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3,
+        GPIO_FN_VIO_CLKR,
+        GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC,
+        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
+        GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4,
+        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK,
+        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5,
+        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD,
+        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN,
+        GPIO_FN_MSIOF0L_TXD,
+        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM,
+        GPIO_FN_PORT226_VIO_CKO2,
+        GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN,
+        GPIO_FN_SCIFA1_RXD,
+        GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1,
+        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR,
+        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT,
+        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG,
+        GPIO_FN_PORT233_FSIACK,
+        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD,
+        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2,
+        GPIO_FN_PORT235_FSIAILR,
+        GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT,
+        GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
+
+        /* 55-5 (FN) */
+        GPIO_FN_MSIOF1_SS2,
+        GPIO_FN_SCIFA6_TXD,
+        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1,
+        GPIO_FN_TPU4TO0,
+        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+        GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS,
+        GPIO_FN_PORT244_MSIOF2_RXD,
+        GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS,
+        GPIO_FN_PORT245_MSIOF2_TXD,
+        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1,
+        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2,
+        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1,
+        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0,
+        GPIO_FN_PORT248_MSIOF2_TSCK,
+        GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC,
+        GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0,
+        GPIO_FN_SDHICD0,
+        GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0,
+        GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0,
+        GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
+        GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0,
+        GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
+        GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
+        GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1,
+        GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2,
+        GPIO_FN_TMS3_SWDIO_MC1,
+        GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2,
+        GPIO_FN_TDO3_SWO0_MC1,
+        GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
+        GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2,
+        GPIO_FN_RTCK3_SWO1_MC1,
+        GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
+        GPIO_FN_RESETOUTS,
+};
+
+#endif /* __ASM_SH7377_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
new file mode 100644
index 000000000000..ceb2cdc92bf9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -0,0 +1,467 @@
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* Hardware manual Table 25-1 (GPIO) */
+        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+        GPIO_PORT128, GPIO_PORT129,
+
+        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+        GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+        GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+        GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+        GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+        GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+        GPIO_PORT288, GPIO_PORT289,
+
+        GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+        GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+        GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+        GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+        /* Table 25-1 (Function 0-7) */
+        GPIO_FN_VBUS_0,
+        GPIO_FN_GPI0,
+        GPIO_FN_GPI1,
+        GPIO_FN_GPI2,
+        GPIO_FN_GPI3,
+        GPIO_FN_GPI4,
+        GPIO_FN_GPI5,
+        GPIO_FN_GPI6,
+        GPIO_FN_GPI7,
+        GPIO_FN_SCIFA7_RXD,
+        GPIO_FN_SCIFA7_CTS_,
+        GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+        GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+        GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+        GPIO_FN_PORT16_VIO_CKOR,
+        GPIO_FN_SCIFA0_TXD,
+        GPIO_FN_SCIFA7_TXD,
+        GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+        GPIO_FN_GPO0,
+        GPIO_FN_GPO1,
+        GPIO_FN_GPO2, GPIO_FN_STATUS0,
+        GPIO_FN_GPO3, GPIO_FN_STATUS1,
+        GPIO_FN_GPO4, GPIO_FN_STATUS2,
+        GPIO_FN_VINT,
+        GPIO_FN_TCKON,
+        GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+        GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+        GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+        GPIO_FN_PORT28_TPU1TO1,
+        GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+        GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+        GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+        GPIO_FN_SCIFA4_TXD,
+        GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+        GPIO_FN_SCIFA4_RTS_,
+        GPIO_FN_SCIFA4_CTS_,
+        GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+        GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+        GPIO_FN_FSIBOSLD,
+        GPIO_FN_FSIBISLD,
+        GPIO_FN_VACK,
+        GPIO_FN_XTAL1L,
+        GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+        GPIO_FN_SCIFA0_RXD,
+        GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+        GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+        GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+        GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+        GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+        GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+        GPIO_FN_FSIAOMC,
+        GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+        GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+        GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+        GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+        GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+        GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+        GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+        GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+        GPIO_FN_A0, GPIO_FN_BS_,
+        GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+        GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+        GPIO_FN_A14, GPIO_FN_KEYOUT5,
+        GPIO_FN_A15, GPIO_FN_KEYOUT4,
+        GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+        GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+        GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+        GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_A26, GPIO_FN_KEYIN6,
+        GPIO_FN_KEYIN7,
+        GPIO_FN_D0_NAF0,
+        GPIO_FN_D1_NAF1,
+        GPIO_FN_D2_NAF2,
+        GPIO_FN_D3_NAF3,
+        GPIO_FN_D4_NAF4,
+        GPIO_FN_D5_NAF5,
+        GPIO_FN_D6_NAF6,
+        GPIO_FN_D7_NAF7,
+        GPIO_FN_D8_NAF8,
+        GPIO_FN_D9_NAF9,
+        GPIO_FN_D10_NAF10,
+        GPIO_FN_D11_NAF11,
+        GPIO_FN_D12_NAF12,
+        GPIO_FN_D13_NAF13,
+        GPIO_FN_D14_NAF14,
+        GPIO_FN_D15_NAF15,
+        GPIO_FN_CS4_,
+        GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+        GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+        GPIO_FN_CS6B_, GPIO_FN_DACK0,
+        GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+        GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+        GPIO_FN_RD__FSC,
+        GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+        GPIO_FN_WE1_,
+        GPIO_FN_FRB,
+        GPIO_FN_CKO,
+        GPIO_FN_NBRSTOUT_,
+        GPIO_FN_NBRST_,
+        GPIO_FN_BBIF2_TXD,
+        GPIO_FN_BBIF2_RXD,
+        GPIO_FN_BBIF2_SYNC,
+        GPIO_FN_BBIF2_SCK,
+        GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+        GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+        GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+        GPIO_FN_SCIFA3_TXD,
+        GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+        GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+        GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+        GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+        GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+        GPIO_FN_PORT115_I2C_SCL3,
+        GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+        GPIO_FN_PORT116_I2C_SDA3,
+        GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+        GPIO_FN_HSI_TX_FLAG,
+        GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+        GPIO_FN_LCD2D0,
+
+        GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+        GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+        GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+        GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+        GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+        GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+        GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+        GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+        GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+        GPIO_FN_LCD2D6,
+        GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+        GPIO_FN_LCD2D7,
+        GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+        GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+        GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+        GPIO_FN_LCD2D2,
+        GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+        GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+        GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+        GPIO_FN_LCD2D4,
+        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+        GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+        GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+        GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+        GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+        GPIO_FN_VIO_CKO,
+        GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+        GPIO_FN_PORT149_KEYOUT9,
+        GPIO_FN_MFG0_IN2,
+        GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+        GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+        GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+        GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+        GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+        GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+        GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+        GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+        GPIO_FN_TPU3TO0,
+        GPIO_FN_LCDD0,
+        GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+        GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+        GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+        GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+        GPIO_FN_TPU2TO1,
+        GPIO_FN_LCDD6,
+        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+        GPIO_FN_LCDD8, GPIO_FN_D16,
+        GPIO_FN_LCDD9, GPIO_FN_D17,
+        GPIO_FN_LCDD10, GPIO_FN_D18,
+        GPIO_FN_LCDD11, GPIO_FN_D19,
+        GPIO_FN_LCDD12, GPIO_FN_D20,
+        GPIO_FN_LCDD13, GPIO_FN_D21,
+        GPIO_FN_LCDD14, GPIO_FN_D22,
+        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+        GPIO_FN_LCDD17, GPIO_FN_D25,
+        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+        GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+        GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+        GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+        GPIO_FN_PORT218_VIO_CKOR,
+        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+        GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+        GPIO_FN_LCD2DCK_2,
+        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+        GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+        GPIO_FN_PORT221_LCD2HSYN,
+        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+        GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+        GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+        GPIO_FN_SCIFA1_RXD,
+        GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+        GPIO_FN_LCD2D20,
+        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+        GPIO_FN_LCD2D21,
+        GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+        GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+        GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+        GPIO_FN_SCIFA6_TXD,
+        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+        GPIO_FN_TPU4TO0,
+        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+        GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+        GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+        GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+        GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+        GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+        GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+        GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+        GPIO_FN_SDHICLK0,
+        GPIO_FN_SDHICD0,
+        GPIO_FN_SDHID0_0,
+        GPIO_FN_SDHID0_1,
+        GPIO_FN_SDHID0_2,
+        GPIO_FN_SDHID0_3,
+        GPIO_FN_SDHICMD0,
+        GPIO_FN_SDHIWP0,
+        GPIO_FN_SDHICLK1,
+        GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+        GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+        GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+        GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+        GPIO_FN_SDHICMD1,
+        GPIO_FN_SDHICLK2,
+        GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+        GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+        GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+        GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+        GPIO_FN_SDHICMD2,
+        GPIO_FN_MMCCLK0,
+        GPIO_FN_MMCD0_0,
+        GPIO_FN_MMCD0_1,
+        GPIO_FN_MMCD0_2,
+        GPIO_FN_MMCD0_3,
+        GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+        GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+        GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+        GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+        GPIO_FN_MMCCMD0,
+        GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+        GPIO_FN_MCP_WAIT__MCP_FRB,
+        GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+        GPIO_FN_MCP_D15_MCP_NAF15,
+        GPIO_FN_MCP_D14_MCP_NAF14,
+        GPIO_FN_MCP_D13_MCP_NAF13,
+        GPIO_FN_MCP_D12_MCP_NAF12,
+        GPIO_FN_MCP_D11_MCP_NAF11,
+        GPIO_FN_MCP_D10_MCP_NAF10,
+        GPIO_FN_MCP_D9_MCP_NAF9,
+        GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+        GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+        GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+        GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+        GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+        GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+        GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+        GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+        GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+        GPIO_FN_MCP_NBRSTOUT_,
+        GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+        /* MSEL2 special case */
+        GPIO_FN_TSIF2_TS_XX1,
+        GPIO_FN_TSIF2_TS_XX2,
+        GPIO_FN_TSIF2_TS_XX3,
+        GPIO_FN_TSIF2_TS_XX4,
+        GPIO_FN_TSIF2_TS_XX5,
+        GPIO_FN_TSIF1_TS_XX1,
+        GPIO_FN_TSIF1_TS_XX2,
+        GPIO_FN_TSIF1_TS_XX3,
+        GPIO_FN_TSIF1_TS_XX4,
+        GPIO_FN_TSIF1_TS_XX5,
+        GPIO_FN_TSIF0_TS_XX1,
+        GPIO_FN_TSIF0_TS_XX2,
+        GPIO_FN_TSIF0_TS_XX3,
+        GPIO_FN_TSIF0_TS_XX4,
+        GPIO_FN_TSIF0_TS_XX5,
+        GPIO_FN_MST1_TS_XX1,
+        GPIO_FN_MST1_TS_XX2,
+        GPIO_FN_MST1_TS_XX3,
+        GPIO_FN_MST1_TS_XX4,
+        GPIO_FN_MST1_TS_XX5,
+        GPIO_FN_MST0_TS_XX1,
+        GPIO_FN_MST0_TS_XX2,
+        GPIO_FN_MST0_TS_XX3,
+        GPIO_FN_MST0_TS_XX4,
+        GPIO_FN_MST0_TS_XX5,
+
+        /* MSEL3 special cases */
+        GPIO_FN_SDHI0_VCCQ_MC0_ON,
+        GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+        GPIO_FN_DEBUG_MON_VIO,
+        GPIO_FN_DEBUG_MON_LCDD,
+        GPIO_FN_LCDC_LCDC0,
+        GPIO_FN_LCDC_LCDC1,
+
+        /* MSEL4 special cases */
+        GPIO_FN_IRQ9_MEM_INT,
+        GPIO_FN_IRQ9_MCP_INT,
+        GPIO_FN_A11,
+        GPIO_FN_KEYOUT8,
+        GPIO_FN_TPU4TO3,
+        GPIO_FN_RESETA_N_PU_ON,
+        GPIO_FN_RESETA_N_PU_OFF,
+        GPIO_FN_EDBGREQ_PD,
+        GPIO_FN_EDBGREQ_PU,
+
+        /* Functions with pull-ups */
+        GPIO_FN_KEYIN0_PU,
+        GPIO_FN_KEYIN1_PU,
+        GPIO_FN_KEYIN2_PU,
+        GPIO_FN_KEYIN3_PU,
+        GPIO_FN_KEYIN4_PU,
+        GPIO_FN_KEYIN5_PU,
+        GPIO_FN_KEYIN6_PU,
+        GPIO_FN_KEYIN7_PU,
+        GPIO_FN_SDHID1_0_PU,
+        GPIO_FN_SDHID1_1_PU,
+        GPIO_FN_SDHID1_2_PU,
+        GPIO_FN_SDHID1_3_PU,
+        GPIO_FN_SDHICMD1_PU,
+        GPIO_FN_MMCCMD0_PU,
+        GPIO_FN_MMCCMD1_PU,
+        GPIO_FN_FSIACK_PU,
+        GPIO_FN_FSIAILR_PU,
+        GPIO_FN_FSIAIBT_PU,
+        GPIO_FN_FSIAISLD_PU,
+};
+
+#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h
new file mode 100644
index 000000000000..50db94e927ad
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/smp.h
@@ -0,0 +1,16 @@
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
+{
+#if defined(CONFIG_ARM_GIC)
+        gic_raise_softirq(mask, ipi);
+#endif
+}
+
+#endif
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
new file mode 100644
index 000000000000..76a687eeaa22
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        cpu_reset(0);
+}
+
+#endif
diff --git a/arch/arm/mach-shmobile/include/mach/timex.h b/arch/arm/mach-shmobile/include/mach/timex.h
new file mode 100644
index 000000000000..ae0d8d825c23
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_MACH_TIMEX_H
+#define __ASM_MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE         1193180 /* unused i8253 PIT value */
+
+#endif /* __ASM_MACH_TIMEX_H */
diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h
new file mode 100644
index 000000000000..0bd7556b1387
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/uncompress.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_MACH_UNCOMPRESS_H
+#define __ASM_MACH_UNCOMPRESS_H
+
+/*
+ * This does not append a newline
+ */
+static void putc(int c)
+{
+}
+
+static inline void flush(void)
+{
+}
+
+static void arch_decomp_setup(void)
+{
+}
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
new file mode 100644
index 000000000000..2b8fd8b942fe
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_VMALLOC_H
+#define __ASM_MACH_VMALLOC_H
+
+/* Vmalloc at ... - 0xe5ffffff */
+#define VMALLOC_END 0xe6000000UL
+
+#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
new file mode 100644
index 000000000000..6d6a205bcf90
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -0,0 +1,23 @@
+#ifndef ZBOOT_H
+#define ZBOOT_H
+
+#include <asm/mach-types.h>
+#include <mach/zboot_macros.h>
+
+/**************************************************
+ *
+ *              board specific settings
+ *
+ **************************************************/
+
+#ifdef CONFIG_MACH_AP4EVB
+#define MACH_TYPE       MACH_TYPE_AP4EVB
+#include "mach/head-ap4evb.txt"
+#elif CONFIG_MACH_MACKEREL
+#define MACH_TYPE       MACH_TYPE_MACKEREL
+#include "mach/head-mackerel.txt"
+#else
+#error "unsupported board."
+#endif
+
+#endif /* ZBOOT_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
new file mode 100644
index 000000000000..aa6111fbc989
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
@@ -0,0 +1,65 @@
+#ifndef __ZBOOT_MACRO_H
+#define __ZBOOT_MACRO_H
+
+/* The LIST command is used to include comments in the script */
+.macro  LIST comment
+.endm
+
+/* The ED command is used to write a 32-bit word */
+.macro ED, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STR     r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+
+/* The EW command is used to write a 16-bit word */
+.macro EW, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STRH    r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+
+/* The EB command is used to write an 8-bit word */
+.macro EB, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STRB    r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+
+/* The WAIT command is used to delay the execution */
+.macro  WAIT, time, reg
+        LDR     r1, 1f
+        LDR     r0, 2f
+        STR     r0, [r1]
+10 :
+        LDR     r0, [r1]
+        CMP     r0, #0x00000000
+        BNE     10b
+        NOP
+        B       3f
+1 :     .long   \reg
+2 :     .long   \time * 100
+3 :
+.endm
+
+/* The DD command is used to read a 32-bit word */
+.macro  DD, start, end
+        LDR     r1, 1f
+        B       2f
+1 :     .long   \start
+2 :
+.endm
+
+#endif /* __ZBOOT_MACRO_H */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
new file mode 100644
index 000000000000..1a20c489b20d
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -0,0 +1,440 @@
+/*
+ * sh7367 processor support - INTC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+enum {
+        UNUSED_INTCA = 0,
+        ENABLED,
+        DISABLED,
+
+        /* interrupt sources INTCA */
+        IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
+        IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
+        DIRC,
+        CRYPT1_ERR, CRYPT2_STD,
+        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
+        ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
+        ETM11_ACQCMP, ETM11_FULL,
+        MFI_MFIM, MFI_MFIS,
+        BBIF1, BBIF2,
+        USBDMAC_USHDMI,
+        USBHS_USHI0, USBHS_USHI1,
+        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
+        KEYSC_KEY,
+        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
+        MSIOF2, MSIOF1,
+        SCIFA4, SCIFA5, SCIFB,
+        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
+        SDHI0,
+        SDHI1,
+        MSU_MSU, MSU_MSU2,
+        IREM,
+        SIU,
+        SPU,
+        IRDA,
+        TPU0, TPU1, TPU2, TPU3, TPU4,
+        LCRC,
+        PINT1, PINT2,
+        TTI20,
+        MISTY,
+        DDM,
+        SDHI2,
+        RWDT0, RWDT1,
+        DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
+        DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
+        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
+        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
+        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
+        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
+
+        /* interrupt groups INTCA */
+        DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
+        ETM11, ARM11, USBHS, FLCTL, IIC1
+};
+
+static struct intc_vect intca_vectors[] __initdata = {
+        INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
+        INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
+        INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
+        INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
+        INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
+        INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
+        INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
+        INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
+        INTC_VECT(DIRC, 0x0560),
+        INTC_VECT(CRYPT1_ERR, 0x05e0),
+        INTC_VECT(CRYPT2_STD, 0x0700),
+        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
+        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
+        INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
+        INTC_VECT(ARM11_COMMRX, 0x0860),
+        INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
+        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
+        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
+        INTC_VECT(USBDMAC_USHDMI, 0x0a00),
+        INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
+        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
+        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
+        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
+        INTC_VECT(KEYSC_KEY, 0x0be0),
+        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
+        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
+        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
+        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
+        INTC_VECT(SCIFB, 0x0d60),
+        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
+        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
+        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
+        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
+        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
+        INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
+        INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
+        INTC_VECT(IREM, 0x0f60),
+        INTC_VECT(SIU, 0x0fa0),
+        INTC_VECT(SPU, 0x0fc0),
+        INTC_VECT(IRDA, 0x0480),
+        INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
+        INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
+        INTC_VECT(TPU4, 0x0520),
+        INTC_VECT(LCRC, 0x0540),
+        INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
+        INTC_VECT(TTI20, 0x1100),
+        INTC_VECT(MISTY, 0x1120),
+        INTC_VECT(DDM, 0x1140),
+        INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
+        INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
+        INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
+        INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
+        INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
+        INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
+        INTC_VECT(DMAC_2_DADERR, 0x20c0),
+        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
+        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
+        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
+        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
+        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
+        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
+        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
+        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
+};
+
+static struct intc_group intca_groups[] __initdata = {
+        INTC_GROUP(DMAC_1, DMAC_1_DEI0,
+                   DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
+        INTC_GROUP(DMAC_2, DMAC_2_DEI4,
+                   DMAC_2_DEI5, DMAC_2_DADERR),
+        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
+                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
+        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
+                   DMAC2_2_DEI5, DMAC2_2_DADERR),
+        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
+                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
+        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
+                   DMAC3_2_DEI5, DMAC3_2_DADERR),
+        INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
+        INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
+        INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
+        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
+                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
+        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
+};
+
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
+        { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
+          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
+            ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
+        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
+          { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
+            DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
+        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
+          { PINT1, PINT2, 0, 0,
+            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
+        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
+          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
+            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
+        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
+          { DDM, 0, 0, 0,
+            0, 0, ETM11_FULL, ETM11_ACQCMP } },
+        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
+          { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
+            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
+        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
+          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
+            0, 0, MSIOF2, 0 } },
+        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            TTI20, USBDMAC_USHDMI, SPU, SIU } },
+        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
+          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
+            CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
+        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
+          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
+            0, 0, 0, 0 } },
+        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
+          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
+            LCRC, MSU_MSU2, IREM, MSU_MSU } },
+        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
+          { 0, 0, TPU0, TPU1,
+            TPU2, TPU3, TPU4, 0 } },
+        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            MISTY, CMT3, RWDT1, RWDT0 } },
+};
+
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
+        { 0xe6900010, 0, 32, 4, /* INTPRI00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900014, 0, 32, 4, /* INTPRI10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+
+        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
+        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
+        { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
+                                              CMT1_CMT11, ARM11 } },
+        { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
+                                              CMT1_CMT12, TPU4 } },
+        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
+                                              MFI_MFIM, USBHS } },
+        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
+                                              0, CMT1_CMT10 } },
+        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
+                                              SCIFA2, SCIFA3 } },
+        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
+                                              FLCTL, SDHI0 } },
+        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
+        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
+        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
+        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
+        { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
+        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
+        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
+};
+
+static struct intc_sense_reg intca_sense_registers[] __initdata = {
+        { 0xe6900000, 16, 2, /* ICR1A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900004, 16, 2, /* ICR2A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+};
+
+static struct intc_mask_reg intca_ack_registers[] __initdata = {
+        { 0xe6900020, 0, 8, /* INTREQ00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900024, 0, 8, /* INTREQ10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+};
+
+static struct intc_desc intca_desc __initdata = {
+        .name = "sh7367-intca",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
+                           intca_mask_registers, intca_prio_registers,
+                           intca_sense_registers, intca_ack_registers),
+};
+
+enum {
+        UNUSED_INTCS = 0,
+
+        INTCS,
+
+        /* interrupt sources INTCS */
+        VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
+        VIO3_VOU,
+        RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
+        VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
+        VPU,
+        SGX530,
+        _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
+        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
+        IPMMU_IPMMUB, IPMMU_IPMMUS,
+        RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
+        MSIOF,
+        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
+        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
+        CMT,
+        TSIF,
+        IPMMUI,
+        MVI3,
+        ICB,
+        PEP,
+        ASA,
+        BEM,
+        VE2HO,
+        HQE,
+        JPEG,
+        LCDC,
+
+        /* interrupt groups INTCS */
+        _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
+};
+
+static struct intc_vect intcs_vectors[] = {
+        INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
+        INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
+        INTCS_VECT(VIO3_VOU, 0x780),
+        INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
+        INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
+        INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
+        INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
+        INTCS_VECT(VPU, 0x980),
+        INTCS_VECT(SGX530, 0x9e0),
+        INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
+        INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
+        INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
+        INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
+        INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
+        INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
+        INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
+        INTCS_VECT(MSIOF, 0xd20),
+        INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
+        INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
+        INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
+        INTCS_VECT(TMU_TUNI2, 0xec0),
+        INTCS_VECT(CMT, 0xf00),
+        INTCS_VECT(TSIF, 0xf20),
+        INTCS_VECT(IPMMUI, 0xf60),
+        INTCS_VECT(MVI3, 0x420),
+        INTCS_VECT(ICB, 0x480),
+        INTCS_VECT(PEP, 0x4a0),
+        INTCS_VECT(ASA, 0x4c0),
+        INTCS_VECT(BEM, 0x4e0),
+        INTCS_VECT(VE2HO, 0x520),
+        INTCS_VECT(HQE, 0x540),
+        INTCS_VECT(JPEG, 0x560),
+        INTCS_VECT(LCDC, 0x580),
+
+        INTC_VECT(INTCS, 0xf80),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+        INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
+                   _2DDMAC_2DDM2, _2DDMAC_2DDM3),
+        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
+                   RTDMAC_1_DEI2, RTDMAC_1_DEI3),
+        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
+        INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
+        INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
+        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
+        INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
+        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+          { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
+            VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
+        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+          { VIO3_VOU, 0, VE2HO, VPU,
+            0, 0, 0, 0 } },
+        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+          { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
+            BEM, ASA, PEP, ICB } },
+        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+          { 0, 0, MVI3, 0,
+            JPEG, HQE, 0, LCDC } },
+        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+          { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
+            RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
+        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+          { 0, 0, MSIOF, 0,
+            SGX530, 0, 0, 0 } },
+        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
+            0, 0, 0, 0 } },
+        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+          { 0, 0, 0, CMT,
+            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
+        { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
+          { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
+            0, 0, 0, 0 } },
+        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
+            0, 0, IPMMUI, TSIF } },
+        { 0xffd20104, 0, 16, /* INTAMASK */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, INTCS } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+        { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
+        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
+        { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
+        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
+        { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
+        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
+                                              TMU_TUNI2, 0 } },
+        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
+        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
+        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
+        { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
+        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
+        { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+        [0] = {
+                .start  = 0xffd20000,
+                .end    = 0xffd2ffff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+        .name = "sh7367-intcs",
+        .resource = intcs_resources,
+        .num_resources = ARRAY_SIZE(intcs_resources),
+        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                           intcs_prio_registers, NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+        void __iomem *reg = (void *)get_irq_data(irq);
+        unsigned int evtcodeas = ioread32(reg);
+
+        generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
+void __init sh7367_init_irq(void)
+{
+        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
+        register_intc_controller(&intca_desc);
+        register_intc_controller(&intcs_desc);
+
+        /* demux using INTEVTSA */
+        set_irq_data(evt2irq(0xf80), (void *)intevtsa);
+        set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
+}
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
new file mode 100644
index 000000000000..30b2f400666a
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -0,0 +1,617 @@
+/*
+ * sh7372 processor support - INTC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+enum {
+        UNUSED_INTCA = 0,
+        ENABLED,
+        DISABLED,
+
+        /* interrupt sources INTCA */
+        IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
+        IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
+        IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
+        IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
+        DIRC,
+        CRYPT_STD,
+        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
+        AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
+        MFI_MFIM, MFI_MFIS,
+        BBIF1, BBIF2,
+        USBHSDMAC0_USHDMI,
+        _3DG_SGX540,
+        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
+        KEYSC_KEY,
+        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
+        MSIOF2, MSIOF1,
+        SCIFA4, SCIFA5, SCIFB,
+        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
+        SDHI0,
+        SDHI1,
+        IRREM,
+        IRDA,
+        TPU0,
+        TTI20,
+        DDM,
+        SDHI2,
+        RWDT0,
+        DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
+        DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
+        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
+        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
+        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
+        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
+        SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
+        HDMI,
+        SPU2_SPU0, SPU2_SPU1,
+        FSI, FMSI,
+        MIPI_HSI,
+        IPMMU_IPMMUD,
+        CEC_1, CEC_2,
+        AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
+        MFIS2,
+        CPORTR2S,
+        CMT14, CMT15,
+        MMC_MMC_ERR, MMC_MMC_NOR,
+        IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
+        IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
+        USB0_USB0I1, USB0_USB0I0,
+        USB1_USB1I1, USB1_USB1I0,
+        USBHSDMAC1_USHDMI,
+
+        /* interrupt groups INTCA */
+        DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
+        AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
+};
+
+static struct intc_vect intca_vectors[] __initdata = {
+        INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
+        INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
+        INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
+        INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
+        INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
+        INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
+        INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
+        INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
+        INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
+        INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
+        INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0),
+        INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
+        INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
+        INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
+        INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
+        INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
+        INTC_VECT(DIRC, 0x0560),
+        INTC_VECT(CRYPT_STD, 0x0700),
+        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
+        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
+        INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
+        INTC_VECT(AP_ARM_COMMRX, 0x0860),
+        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
+        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
+        INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
+        INTC_VECT(_3DG_SGX540, 0x0a60),
+        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
+        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
+        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
+        INTC_VECT(KEYSC_KEY, 0x0be0),
+        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
+        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
+        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
+        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
+        INTC_VECT(SCIFB, 0x0d60),
+        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
+        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
+        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
+        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
+        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
+        INTC_VECT(SDHI1, 0x0ec0),
+        INTC_VECT(IRREM, 0x0f60),
+        INTC_VECT(IRDA, 0x0480),
+        INTC_VECT(TPU0, 0x04a0),
+        INTC_VECT(TTI20, 0x1100),
+        INTC_VECT(DDM, 0x1140),
+        INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
+        INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
+        INTC_VECT(RWDT0, 0x1280),
+        INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
+        INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
+        INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
+        INTC_VECT(DMAC1_2_DADERR, 0x20c0),
+        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
+        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
+        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
+        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
+        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
+        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
+        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
+        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
+        INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
+        INTC_VECT(SHWYSTAT_COM, 0x1340),
+        INTC_VECT(HDMI, 0x17e0),
+        INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
+        INTC_VECT(FSI, 0x1840),
+        INTC_VECT(FMSI, 0x1860),
+        INTC_VECT(MIPI_HSI, 0x18e0),
+        INTC_VECT(IPMMU_IPMMUD, 0x1920),
+        INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
+        INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
+        INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
+        INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
+        INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
+        INTC_VECT(MFIS2, 0x1a00),
+        INTC_VECT(CPORTR2S, 0x1a20),
+        INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
+        INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
+        INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
+        INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
+        INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
+        INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
+        INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
+        INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
+        INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
+};
+
+static struct intc_group intca_groups[] __initdata = {
+        INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
+                   DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
+        INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
+                   DMAC1_2_DEI5, DMAC1_2_DADERR),
+        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
+                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
+        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
+                   DMAC2_2_DEI5, DMAC2_2_DADERR),
+        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
+                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
+        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
+                   DMAC3_2_DEI5, DMAC3_2_DADERR),
+        INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
+        INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
+                   AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
+        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
+        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
+                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
+        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
+        INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
+};
+
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
+        { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+
+        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
+          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
+            AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
+        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
+          { 0, CRYPT_STD, DIRC, 0,
+            DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
+        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
+          { 0, 0, 0, 0,
+            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
+        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
+          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
+            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
+        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
+          { DDM, 0, 0, 0,
+            0, 0, 0, 0 } },
+        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
+          { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
+            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
+        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
+          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
+            0, 0, MSIOF2, 0 } },
+        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
+          { 0, DISABLED, ENABLED, ENABLED,
+            TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
+        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
+          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
+            CMT2, 0, 0, _3DG_SGX540 } },
+        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
+          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
+            0, 0, 0, 0 } },
+        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
+          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
+            0, 0, IRREM, 0 } },
+        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
+          { 0, 0, TPU0, 0,
+            0, 0, 0, 0 } },
+        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            0, CMT3, 0, RWDT0 } },
+        { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
+          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
+            0, 0, 0, 0 } },
+        { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
+          { 0, 0, 0, 0,
+            0, 0, 0, HDMI } },
+        { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
+          { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
+            0, 0, 0, MIPI_HSI } },
+        { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
+          { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
+            AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
+            AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
+        { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
+          { MFIS2, CPORTR2S, CMT14, CMT15,
+            0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
+        { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
+          { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
+            IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
+        { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
+          { 0, 0, 0, 0,
+            USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
+        { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
+          { USBHSDMAC1_USHDMI, 0, 0, 0,
+            0, 0, 0, 0 } },
+};
+
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
+        { 0xe6900010, 0, 32, 4, /* INTPRI00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900014, 0, 32, 4, /* INTPRI10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900018, 0, 32, 4, /* INTPRI20A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690001c, 0, 32, 4, /* INTPRI30A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+
+        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
+        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
+        { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
+                                              CMT1_CMT11, AP_ARM1 } },
+        { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
+                                              CMT1_CMT12, 0 } },
+        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
+                                              MFI_MFIM, 0 } },
+        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
+                                              _3DG_SGX540, CMT1_CMT10 } },
+        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
+                                              SCIFA2, SCIFA3 } },
+        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
+                                              FLCTL, SDHI0 } },
+        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
+                                              0/* MSU */, IIC1 } },
+        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
+                                              0/* MSUG */, TTI20 } },
+        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
+        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
+        { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
+        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
+        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
+        { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
+        { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
+        { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
+        { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
+        { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
+                                               CEC_1, CEC_2 } },
+        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
+        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
+                                               CMT14, CMT15 } },
+        { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
+                                               MMC_MMC_ERR, MMC_MMC_NOR } },
+        { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
+                                               IIC4_WAITI4, IIC4_DTEI4 } },
+        { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
+                                               IIC3_WAITI3, IIC3_DTEI3 } },
+        { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
+                                               0/*TXI*/, 0/*TEI*/} },
+        { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
+                                               USB1_USB1I1, USB1_USB1I0 } },
+        { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
+};
+
+static struct intc_sense_reg intca_sense_registers[] __initdata = {
+        { 0xe6900000, 32, 4, /* ICR1A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900004, 32, 4, /* ICR2A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900008, 32, 4, /* ICR3A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690000c, 32, 4, /* ICR4A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+};
+
+static struct intc_mask_reg intca_ack_registers[] __initdata = {
+        { 0xe6900020, 0, 8, /* INTREQ00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900024, 0, 8, /* INTREQ10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900028, 0, 8, /* INTREQ20A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690002c, 0, 8, /* INTREQ30A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+};
+
+static struct intc_desc intca_desc __initdata = {
+        .name = "sh7372-intca",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
+                           intca_mask_registers, intca_prio_registers,
+                           intca_sense_registers, intca_ack_registers),
+};
+
+enum {
+        UNUSED_INTCS = 0,
+
+        INTCS,
+
+        /* interrupt sources INTCS */
+
+        /* IRQ0S - IRQ31S */
+        VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
+        RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
+        CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
+        /* MFI */
+        /* BBIF2 */
+        VPU,
+        TSIF1,
+        _3DG_SGX530,
+        _2DDMAC,
+        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
+        IPMMU_IPMMUR, IPMMU_IPMMUR2,
+        RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
+        /* KEYSC */
+        /* TTI20 */
+        MSIOF,
+        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
+        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
+        CMT0,
+        TSIF0,
+        /* CMT2 */
+        LMB,
+        CTI,
+        /* RWDT0 */
+        ICB,
+        JPU_JPEG,
+        LCDC,
+        LCRC,
+        RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
+        RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
+        ISP,
+        LCDC1,
+        CSIRX,
+        DSITX_DSITX0,
+        DSITX_DSITX1,
+        /* SPU2 */
+        /* FSI */
+        /* FMSI */
+        /* HDMI */
+        TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
+        CMT4,
+        DSITX1_DSITX1_0,
+        DSITX1_DSITX1_1,
+        /* MFIS2 */
+        CPORTS2R,
+        /* CEC */
+        JPU6E,
+
+        /* interrupt groups INTCS */
+        RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
+        RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
+};
+
+static struct intc_vect intcs_vectors[] = {
+        /* IRQ0S - IRQ31S */
+        INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
+        INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
+        INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
+        INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
+        INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
+        INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
+        /* MFI */
+        /* BBIF2 */
+        INTCS_VECT(VPU, 0x980),
+        INTCS_VECT(TSIF1, 0x9a0),
+        INTCS_VECT(_3DG_SGX530, 0x9e0),
+        INTCS_VECT(_2DDMAC, 0xa00),
+        INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
+        INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
+        INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
+        INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
+        INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
+        /* KEYSC */
+        /* TTI20 */
+        INTCS_VECT(MSIOF, 0x0d20),
+        INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
+        INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
+        INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
+        INTCS_VECT(TMU_TUNI2, 0xec0),
+        INTCS_VECT(CMT0, 0xf00),
+        INTCS_VECT(TSIF0, 0xf20),
+        /* CMT2 */
+        INTCS_VECT(LMB, 0xf60),
+        INTCS_VECT(CTI, 0x400),
+        /* RWDT0 */
+        INTCS_VECT(ICB, 0x480),
+        INTCS_VECT(JPU_JPEG, 0x560),
+        INTCS_VECT(LCDC, 0x580),
+        INTCS_VECT(LCRC, 0x5a0),
+        INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
+        INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
+        INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
+        INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
+        INTCS_VECT(ISP, 0x1720),
+        INTCS_VECT(LCDC1, 0x1780),
+        INTCS_VECT(CSIRX, 0x17a0),
+        INTCS_VECT(DSITX_DSITX0, 0x17c0),
+        INTCS_VECT(DSITX_DSITX1, 0x17e0),
+        /* SPU2 */
+        /* FSI */
+        /* FMSI */
+        /* HDMI */
+        INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
+        INTCS_VECT(TMU1_TUNI2, 0x1940),
+        INTCS_VECT(CMT4, 0x1980),
+        INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
+        INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
+        /* MFIS2 */
+        INTCS_VECT(CPORTS2R, 0x1a20),
+        /* CEC */
+        INTCS_VECT(JPU6E, 0x1a80),
+
+        INTC_VECT(INTCS, 0xf80),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
+                   RTDMAC_1_DEI2, RTDMAC_1_DEI3),
+        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
+        INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
+        INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
+        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
+        INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
+        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
+        INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
+                   RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
+        INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
+                   RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
+        INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
+        INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+          { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
+            VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
+        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+          { 0, 0, 0, VPU,
+            0, 0, 0, 0 } },
+        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+          { 0, 0, 0, _2DDMAC,
+            0, 0, 0, ICB } },
+        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+          { 0, 0, 0, CTI,
+            JPU_JPEG, 0, LCRC, LCDC } },
+        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+          { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
+            RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
+        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+          { 0, 0, MSIOF, 0,
+            _3DG_SGX530, 0, 0, 0 } },
+        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
+            0, 0, 0, 0 } },
+        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+          { 0, 0, 0, CMT0,
+            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
+        { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
+          { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
+            0, 0, 0, 0 } },
+        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
+            0, TSIF1, LMB, TSIF0 } },
+        { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
+          { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
+            RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
+        { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
+          { 0, ISP, 0, 0,
+            LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
+        { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
+          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+            CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
+        { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
+          { 0, CPORTS2R, 0, 0,
+            JPU6E, 0, 0, 0 } },
+        { 0xffd20104, 0, 16, /* INTAMASK */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, INTCS } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+        { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
+        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
+        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
+        { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
+        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
+                                              TMU_TUNI2, TSIF1 } },
+        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
+        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
+        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
+        { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
+        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
+        { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
+        { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
+        { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
+        { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
+        { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
+        { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
+        { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
+                                               DSITX1_DSITX1_1, 0 } },
+        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
+        { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+        [0] = {
+                .start  = 0xffd20000,
+                .end    = 0xffd201ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffd50000,
+                .end    = 0xffd501ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+        .name = "sh7372-intcs",
+        .resource = intcs_resources,
+        .num_resources = ARRAY_SIZE(intcs_resources),
+        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                           intcs_prio_registers, NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+        void __iomem *reg = (void *)get_irq_data(irq);
+        unsigned int evtcodeas = ioread32(reg);
+
+        generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
+void __init sh7372_init_irq(void)
+{
+        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
+        register_intc_controller(&intca_desc);
+        register_intc_controller(&intcs_desc);
+
+        /* demux using INTEVTSA */
+        set_irq_data(evt2irq(0xf80), (void *)intevtsa);
+        set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
+}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
new file mode 100644
index 000000000000..2cdeb8ccd821
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -0,0 +1,646 @@
+/*
+ * sh7377 processor support - INTC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+enum {
+        UNUSED_INTCA = 0,
+        ENABLED,
+        DISABLED,
+
+        /* interrupt sources INTCA */
+        IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
+        IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
+        IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
+        IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
+        DIRC,
+        _2DG,
+        CRYPT_STD,
+        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
+        AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
+        MFI_MFIM, MFI_MFIS,
+        BBIF1, BBIF2,
+        USBDMAC_USHDMI,
+        USBHS_USHI0, USBHS_USHI1,
+        _3DG_SGX540,
+        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
+        KEYSC_KEY,
+        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
+        MSIOF2, MSIOF1,
+        SCIFA4, SCIFA5, SCIFB,
+        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
+        SDHI0,
+        SDHI1,
+        MSU_MSU, MSU_MSU2,
+        IRREM,
+        MSUG,
+        IRDA,
+        TPU0, TPU1, TPU2, TPU3, TPU4,
+        LCRC,
+        PINTCA_PINT1, PINTCA_PINT2,
+        TTI20,
+        MISTY,
+        DDM,
+        RWDT0, RWDT1,
+        DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
+        DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
+        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
+        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
+        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
+        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
+        SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
+        ICUSB_ICUSB0, ICUSB_ICUSB1,
+        ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
+        SPU2_SPU0, SPU2_SPU1,
+        FSI,
+        FMSI,
+        SCUV,
+        IPMMU_IPMMUB,
+        AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
+        MFIS2,
+        CPORTR2S,
+        CMT14, CMT15,
+        SCIFA6,
+
+        /* interrupt groups INTCA */
+        DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
+        AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
+        ICUSB, ICUDMC
+};
+
+static struct intc_vect intca_vectors[] __initdata = {
+        INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
+        INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
+        INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
+        INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
+        INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
+        INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
+        INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
+        INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
+        INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
+        INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
+        INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
+        INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
+        INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
+        INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
+        INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
+        INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
+        INTC_VECT(DIRC, 0x0560),
+        INTC_VECT(_2DG, 0x05e0),
+        INTC_VECT(CRYPT_STD, 0x0700),
+        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
+        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
+        INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
+        INTC_VECT(AP_ARM_COMMRX, 0x0860),
+        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
+        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
+        INTC_VECT(USBDMAC_USHDMI, 0x0a00),
+        INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
+        INTC_VECT(_3DG_SGX540, 0x0a60),
+        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
+        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
+        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
+        INTC_VECT(KEYSC_KEY, 0x0be0),
+        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
+        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
+        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
+        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
+        INTC_VECT(SCIFB, 0x0d60),
+        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
+        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
+        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
+        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
+        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
+        INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
+        INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
+        INTC_VECT(IRREM, 0x0f60),
+        INTC_VECT(MSUG, 0x0fa0),
+        INTC_VECT(IRDA, 0x0480),
+        INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
+        INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
+        INTC_VECT(TPU4, 0x0520),
+        INTC_VECT(LCRC, 0x0540),
+        INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
+        INTC_VECT(TTI20, 0x1100),
+        INTC_VECT(MISTY, 0x1120),
+        INTC_VECT(DDM, 0x1140),
+        INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
+        INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
+        INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
+        INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
+        INTC_VECT(DMAC_2_DADERR, 0x20c0),
+        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
+        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
+        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
+        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
+        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
+        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
+        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
+        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
+        INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
+        INTC_VECT(SHWYSTAT_COM, 0x1340),
+        INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
+        INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
+        INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
+        INTC_VECT(FSI, 0x1840),
+        INTC_VECT(FMSI, 0x1860),
+        INTC_VECT(SCUV, 0x1880),
+        INTC_VECT(IPMMU_IPMMUB, 0x1900),
+        INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
+        INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
+        INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
+        INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
+        INTC_VECT(MFIS2, 0x1a00),
+        INTC_VECT(CPORTR2S, 0x1a20),
+        INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
+        INTC_VECT(SCIFA6, 0x1a80),
+};
+
+static struct intc_group intca_groups[] __initdata = {
+        INTC_GROUP(DMAC_1, DMAC_1_DEI0,
+                   DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
+        INTC_GROUP(DMAC_2, DMAC_2_DEI4,
+                   DMAC_2_DEI5, DMAC_2_DADERR),
+        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
+                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
+        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
+                   DMAC2_2_DEI5, DMAC2_2_DADERR),
+        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
+                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
+        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
+                   DMAC3_2_DEI5, DMAC3_2_DADERR),
+        INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
+        INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
+        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
+        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
+                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
+        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
+        INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
+        INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
+        INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
+};
+
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
+        { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+
+        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
+          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
+            AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
+        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
+          { _2DG, CRYPT_STD, DIRC, 0,
+            DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
+        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
+          { PINTCA_PINT1, PINTCA_PINT2, 0, 0,
+            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
+        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
+          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
+            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
+        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
+          { DDM, 0, 0, 0,
+            0, 0, 0, 0 } },
+        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
+          { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
+            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
+        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
+          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
+            0, 0, MSIOF2, 0 } },
+        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
+          { DISABLED, DISABLED, ENABLED, ENABLED,
+            TTI20, USBDMAC_USHDMI, 0, MSUG } },
+        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
+          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
+            CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
+        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
+          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
+            0, 0, 0, 0 } },
+        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
+          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
+            LCRC, MSU_MSU2, IRREM, MSU_MSU } },
+        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
+          { 0, 0, TPU0, TPU1,
+            TPU2, TPU3, TPU4, 0 } },
+        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
+          { 0, 0, 0, 0,
+            MISTY, CMT3, RWDT1, RWDT0 } },
+        { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
+          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
+            0, 0, 0, 0 } },
+        { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
+          { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
+            ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
+        { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
+          { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
+            SCUV, 0, 0, 0 } },
+        { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
+          { IPMMU_IPMMUB, 0, 0, 0,
+            AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
+            AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
+        { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
+          { MFIS2, CPORTR2S, CMT14, CMT15,
+            SCIFA6, 0, 0, 0 } },
+};
+
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
+        { 0xe6900010, 0, 32, 4, /* INTPRI00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900014, 0, 32, 4, /* INTPRI10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900018, 0, 32, 4, /* INTPRI10A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690001c, 0, 32, 4, /* INTPRI30A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+
+        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
+        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
+        { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
+                                              CMT1_CMT11, AP_ARM1 } },
+        { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
+                                              CMT1_CMT12, TPU4 } },
+        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
+                                              MFI_MFIM, USBHS } },
+        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
+                                              _3DG_SGX540, CMT1_CMT10 } },
+        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
+                                              SCIFA2, SCIFA3 } },
+        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
+                                              FLCTL, SDHI0 } },
+        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
+        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
+        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
+        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
+        { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
+        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
+        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
+        { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
+        { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
+        { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
+        { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
+        { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
+        { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
+        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
+        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
+                                               CMT14, CMT15 } },
+        { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
+};
+
+static struct intc_sense_reg intca_sense_registers[] __initdata = {
+        { 0xe6900000, 16, 2, /* ICR1A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900004, 16, 2, /* ICR2A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900008, 16, 2, /* ICR3A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690000c, 16, 2, /* ICR4A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+};
+
+static struct intc_mask_reg intca_ack_registers[] __initdata = {
+        { 0xe6900020, 0, 8, /* INTREQ00A */
+          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
+        { 0xe6900024, 0, 8, /* INTREQ10A */
+          { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
+        { 0xe6900028, 0, 8, /* INTREQ20A */
+          { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
+        { 0xe690002c, 0, 8, /* INTREQ30A */
+          { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
+};
+
+static struct intc_desc intca_desc __initdata = {
+        .name = "sh7377-intca",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
+                           intca_mask_registers, intca_prio_registers,
+                           intca_sense_registers, intca_ack_registers),
+};
+
+/* this macro ignore entry which is also in INTCA */
+#define __IGNORE(a...)
+#define __IGNORE0(a...) 0
+
+enum {
+        UNUSED_INTCS = 0,
+
+        INTCS,
+
+        /* interrupt sources INTCS */
+        VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
+        RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
+        CEU,
+        BEU_BEU0, BEU_BEU1, BEU_BEU2,
+        __IGNORE(MFI)
+        __IGNORE(BBIF2)
+        VPU,
+        TSIF1,
+        __IGNORE(SGX540)
+        _2DDMAC,
+        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
+        IPMMU_IPMMUR, IPMMU_IPMMUR2,
+        RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
+        __IGNORE(KEYSC)
+        __IGNORE(TTI20)
+        __IGNORE(MSIOF)
+        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
+        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
+        CMT0,
+        TSIF0,
+        __IGNORE(CMT2)
+        LMB,
+        __IGNORE(MSUG)
+        __IGNORE(MSU_MSU, MSU_MSU2)
+        __IGNORE(CTI)
+        MVI3,
+        __IGNORE(RWDT0)
+        __IGNORE(RWDT1)
+        ICB,
+        PEP,
+        ASA,
+        __IGNORE(_2DG)
+        HQE,
+        JPU,
+        LCDC0,
+        __IGNORE(LCRC)
+        RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
+        RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
+        FRC,
+        LCDC1,
+        CSIRX,
+        DSITX_DSITX0, DSITX_DSITX1,
+        __IGNORE(SPU2_SPU0, SPU2_SPU1)
+        __IGNORE(FSI)
+        __IGNORE(FMSI)
+        __IGNORE(SCUV)
+        TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
+        TSIF2,
+        CMT4,
+        __IGNORE(MFIS2)
+        CPORTS2R,
+
+        /* interrupt groups INTCS */
+        RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
+        IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
+};
+
+#define INTCS_INTVECT 0x0F80
+static struct intc_vect intcs_vectors[] __initdata = {
+        INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
+        INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
+        INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
+        INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
+        INTCS_VECT(CEU, 0x0880),
+        INTCS_VECT(BEU_BEU0, 0x08A0),
+        INTCS_VECT(BEU_BEU1, 0x08C0),
+        INTCS_VECT(BEU_BEU2, 0x08E0),
+        __IGNORE(INTCS_VECT(MFI, 0x0900))
+        __IGNORE(INTCS_VECT(BBIF2, 0x0960))
+        INTCS_VECT(VPU, 0x0980),
+        INTCS_VECT(TSIF1, 0x09A0),
+        __IGNORE(INTCS_VECT(SGX540, 0x09E0))
+        INTCS_VECT(_2DDMAC, 0x0A00),
+        INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
+        INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
+        INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
+        INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
+        INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
+        INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
+        __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
+        __IGNORE(INTCS_VECT(TTI20, 0x0C80))
+        __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
+        INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
+        INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
+        INTCS_VECT(TMU_TUNI0, 0x0E80),
+        INTCS_VECT(TMU_TUNI1, 0x0EA0),
+        INTCS_VECT(TMU_TUNI2, 0x0EC0),
+        INTCS_VECT(CMT0, 0x0F00),
+        INTCS_VECT(TSIF0, 0x0F20),
+        __IGNORE(INTCS_VECT(CMT2, 0x0F40))
+        INTCS_VECT(LMB, 0x0F60),
+        __IGNORE(INTCS_VECT(MSUG, 0x0F80))
+        __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
+        __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
+        __IGNORE(INTCS_VECT(CTI, 0x0400))
+        INTCS_VECT(MVI3, 0x0420),
+        __IGNORE(INTCS_VECT(RWDT0, 0x0440))
+        __IGNORE(INTCS_VECT(RWDT1, 0x0460))
+        INTCS_VECT(ICB, 0x0480),
+        INTCS_VECT(PEP, 0x04A0),
+        INTCS_VECT(ASA, 0x04C0),
+        __IGNORE(INTCS_VECT(_2DG, 0x04E0))
+        INTCS_VECT(HQE, 0x0540),
+        INTCS_VECT(JPU, 0x0560),
+        INTCS_VECT(LCDC0, 0x0580),
+        __IGNORE(INTCS_VECT(LCRC, 0x05A0))
+        INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
+        INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
+        INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
+        INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
+        INTCS_VECT(FRC, 0x1700),
+        INTCS_VECT(LCDC1, 0x1780),
+        INTCS_VECT(CSIRX, 0x17A0),
+        INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
+        __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
+        __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
+        __IGNORE(INTCS_VECT(FSI, 0x1840))
+        __IGNORE(INTCS_VECT(FMSI, 0x1860))
+        __IGNORE(INTCS_VECT(SCUV, 0x1880))
+        INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
+        INTCS_VECT(TMU1_TUNI12, 0x1940),
+        INTCS_VECT(TSIF2, 0x1960),
+        INTCS_VECT(CMT4, 0x1980),
+        __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
+        INTCS_VECT(CPORTS2R, 0x1A20),
+
+        INTC_VECT(INTCS, INTCS_INTVECT),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+        INTC_GROUP(RTDMAC1_1,
+                   RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
+                   RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
+        INTC_GROUP(RTDMAC1_2,
+                   RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
+        INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
+        INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
+        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
+        __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
+        INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
+        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
+        INTC_GROUP(RTDMAC2_1,
+                   RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
+                   RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
+        INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
+        INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
+        __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
+        INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] __initdata = {
+        { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS  */
+          { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
+            VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
+        { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
+          { 0, 0, 0, VPU,
+            __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
+        { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
+          { 0, 0, 0, _2DDMAC,
+            __IGNORE0(_2DG), ASA, PEP, ICB } },
+        { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
+          { 0, 0, MVI3, __IGNORE0(CTI),
+            JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
+        { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
+          { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
+            RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
+        __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
+          { 0, 0, MSIOF, 0,
+            SGX540, 0, TTI20, 0 } })
+        { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
+          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
+            0, 0, 0, 0 } },
+        __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
+          { 0, 0, 0, 0,
+            0, MSU_MSU, MSU_MSU2, MSUG } })
+        { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
+          { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
+            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
+        { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
+          { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
+            0, 0, 0, 0 } },
+        { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
+          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
+            0, TSIF1, LMB, TSIF0 } },
+        { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
+          { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
+            RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
+        { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
+          { FRC, 0, 0, 0,
+            LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
+        __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
+          {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
+           SCUV, 0, 0, 0 } })
+        { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
+          { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
+            CMT4, 0, 0, 0 } },
+        { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
+          { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
+            0, 0, 0, 0 } },
+        { 0xFFD20104, 0, 16, /* INTAMASK */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, INTCS } }
+};
+
+static struct intc_prio_reg intcs_prio_registers[] __initdata = {
+        /* IPRAS */
+        { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
+        /* IPRBS */
+        { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
+        /* IPRCS */
+        __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
+        /* IPRES */
+        { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
+        /* IPRFS */
+        { 0xFFD20014, 0, 16, 4,
+          { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
+        /* IPRGS */
+        { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
+        /* IPRHS */
+        { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
+        /* IPRIS */
+        { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
+        /* IPRJS */
+        __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
+        /* IPRKS */
+        { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
+        /* IPRLS */
+        { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
+        /* IPRMS */
+        { 0xFFD20030, 0, 16, 4,
+          { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
+        /* IPRAS3 */
+        { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
+        /* IPRBS3 */
+        { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
+        /* IPRIS3 */
+        { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
+        /* IPRJS3 */
+        { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
+        /* IPRKS3 */
+        __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
+        /* IPRLS3 */
+        __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
+        /* IPRMS3 */
+        { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
+        /* IPRNS3 */
+        { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
+        /* IPROS3 */
+        { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+        [0] = {
+                .start  = 0xffd20000,
+                .end    = 0xffd500ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+        .name = "sh7377-intcs",
+        .resource = intcs_resources,
+        .num_resources = ARRAY_SIZE(intcs_resources),
+        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
+                           intcs_mask_registers, intcs_prio_registers,
+                           NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+        void __iomem *reg = (void *)get_irq_data(irq);
+        unsigned int evtcodeas = ioread32(reg);
+
+        generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
+#define INTEVTSA 0xFFD20100
+void __init sh7377_init_irq(void)
+{
+        void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
+
+        register_intc_controller(&intca_desc);
+        register_intc_controller(&intcs_desc);
+
+        /* demux using INTEVTSA */
+        set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
+        set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
+}
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
new file mode 100644
index 000000000000..322d8d57cbcf
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -0,0 +1,267 @@
+/*
+ * sh73a0 processor support - INTC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources INTCS */
+        PINTCS_PINT1, PINTCS_PINT2,
+        RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
+        CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
+        RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
+        KEYSC_KEY, VINT, MSIOF,
+        TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
+        CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
+        CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
+        RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
+        RTDMAC_3_DEI10, RTDMAC_3_DEI11,
+        FRC, GCU, LCDC1, CSIRX,
+        DSITX0_DSITX00, DSITX0_DSITX01,
+        SPU2_SPU0, SPU2_SPU1, FSI,
+        TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
+        TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
+        VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
+        DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
+        MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
+        SPUV,
+
+        /* interrupt groups INTCS */
+        RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
+        DSITX0, SPU2, TMU1, MSU,
+};
+
+static struct intc_vect intcs_vectors[] = {
+        INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
+        INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
+        INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
+        INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
+        INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
+        INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
+        INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
+        INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
+        INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
+        INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
+        INTCS_VECT(MSIOF, 0x0d20),
+        INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
+        INTCS_VECT(TMU0_TUNI02, 0x0ec0),
+        INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
+        INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
+        INTCS_VECT(MSUG, 0x0f80),
+        INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
+        INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
+        INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
+        INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
+        INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
+        INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
+        INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
+        INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
+        INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
+        INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
+        INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
+        INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
+        INTCS_VECT(FSI, 0x1840),
+        INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
+        INTCS_VECT(TMU1_TUNI12, 0x1940),
+        INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
+        INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
+        INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
+        INTCS_VECT(SCUW, 0x1b40),
+        INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
+        INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
+        INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
+        INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
+        INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
+        INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
+        INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
+        INTCS_VECT(SPUV, 0x2300),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+        INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
+                   RTDMAC_0_DEI2, RTDMAC_0_DEI3),
+        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
+        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
+                   RTDMAC_2_DEI8, RTDMAC_2_DEI9),
+        INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
+        INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
+        INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
+        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
+        INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+          { 0, 0, 0, CEU,
+            0, 0, 0, 0 } },
+        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+          { 0, 0, 0, VPU,
+            BBIF2, 0, 0, MFI } },
+        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+          { 0, 0, 0, _2DDMAC_2DDM0,
+            0, ASA, PEP, ICB } },
+        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+          { 0, 0, 0, CTI,
+            JPU_JPEG, 0, LCRC, LCDC } },
+        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+          { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
+            RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
+        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+          { 0, 0, MSIOF, 0,
+            _3DG_SGX543, 0, 0, 0 } },
+        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+          { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
+            0, 0, 0, 0 } },
+        { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
+          { 0, 0, 0, 0,
+            0, MSU_MSU, MSU_MSU2, MSUG } },
+        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+          { 0, RWDT0, CMT2, CMT0,
+            0, 0, 0, 0 } },
+        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+          { 0, 0, 0, 0,
+            0, TSIF1, LMB, TSIF0 } },
+        { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
+          { 0, 0, 0, 0,
+            0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
+        { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
+          { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
+            RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
+        { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
+          { FRC, 0, 0, GCU,
+            LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
+        { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
+          { SPU2_SPU0, SPU2_SPU1, FSI, 0,
+            0, 0, 0, 0 } },
+        { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
+          { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
+            TSIF2, CMT4, 0, 0 } },
+        { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
+          { MFIS2, CPORTS2R, 0, 0,
+            0, 0, 0, TSG } },
+        { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
+          { DMASCH1, 0, SCUW, VIO60,
+            VIO61, CEU21, 0, CSI21 } },
+        { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
+          { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
+            EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
+        { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
+          { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
+            0, 0, 0, 0  } },
+        { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
+          { SPUV, 0, 0, 0,
+            0, 0, 0, 0  } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+        { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
+        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
+        { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
+        { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
+                                              0, 0 } },
+        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
+        { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
+                                              CMT2, CMT0 } },
+        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
+                                              TMU0_TUNI02, TSIF1 } },
+        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
+        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
+        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
+        { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
+        { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
+        { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
+        { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
+        { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
+        { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
+        { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
+        { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
+        { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
+        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
+        { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
+        { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
+        { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
+                                               DISP, DSRV } },
+        { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
+                                               MSTIF0_MST00I, MSTIF0_MST01I } },
+        { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
+                                               0, 0 } },
+        { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+        [0] = {
+                .start  = 0xffd20000,
+                .end    = 0xffd201ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffd50000,
+                .end    = 0xffd501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 0xffd60000,
+                .end    = 0xffd601ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+        .name = "sh73a0-intcs",
+        .resource = intcs_resources,
+        .num_resources = ARRAY_SIZE(intcs_resources),
+        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                           intcs_prio_registers, NULL, NULL),
+};
+
+static struct irqaction sh73a0_intcs_cascade;
+
+static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
+{
+        unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
+
+        generic_handle_irq(intcs_evt2irq(evtcodeas));
+
+        return IRQ_HANDLED;
+}
+
+void __init sh73a0_init_irq(void)
+{
+        void __iomem *gic_base = __io(0xf0001000);
+        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
+        gic_init(0, 29, gic_base, gic_base);
+
+        register_intc_controller(&intcs_desc);
+
+        /* demux using INTEVTSA */
+        sh73a0_intcs_cascade.name = "INTCS cascade";
+        sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
+        sh73a0_intcs_cascade.dev_id = intevtsa;
+        setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
+}
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
new file mode 100644
index 000000000000..2111c28b724e
--- /dev/null
+++ b/arch/arm/mach-shmobile/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile - local timer portion
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        evt->irq = 29;
+        twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
new file mode 100644
index 000000000000..128555e76e43
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh7367.c
@@ -0,0 +1,1801 @@
+/*
+ * sh7367 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/sh7367.h>
+
+#define _1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define _10(fn, pfx, sfx)                               \
+        _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx),       \
+        _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx),       \
+        _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx),       \
+        _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx),       \
+        _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
+
+#define _90(fn, pfx, sfx)                               \
+        _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx),     \
+        _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx),     \
+        _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx),     \
+        _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx),     \
+        _10(fn, pfx##9, sfx)
+
+#define _273(fn, pfx, sfx)              \
+        _10(fn, pfx, sfx), _90(fn, pfx, sfx),           \
+        _10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx),    \
+        _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx),   \
+        _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx),   \
+        _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx),   \
+        _10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx),   \
+        _1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx)
+
+#define _PORT(pfx, sfx) pfx##_##sfx
+#define PORT_273(str) _273(_PORT, PORT, str)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PORT_273(IN), /* PORT0_IN -> PORT272_IN */
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
+        PINMUX_INPUT_PULLDOWN_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
+        PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
+        PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */
+        PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */
+        PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */
+        PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */
+        PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */
+        PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */
+        PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */
+        PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */
+
+        MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* Special Pull-up / Pull-down Functions */
+        PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
+        PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
+        PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
+        PORT58_KEYIN6_PU_MARK,
+
+        /* 49-1 */
+        VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
+        CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
+        CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
+        CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
+        CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
+        CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
+        CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
+        RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
+        STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
+        MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
+        XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
+        IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
+        M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
+        XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
+        XCTS1_MARK, SCIFA4_CTS_MARK,
+
+        /* 49-2 */
+        HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
+        HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
+        HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
+        HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
+        HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
+        HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
+        HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
+        HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
+        HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
+        HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
+        HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
+        HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
+        HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
+        HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
+        HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
+        HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
+        B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
+        HSU_SDI_MARK, PORT55_KEYIN3_MARK,
+        HSU_SCO_MARK, PORT56_KEYIN4_MARK,
+        HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
+        HSU_DACK_MARK, PORT58_KEYIN6_MARK,
+        HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
+        HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
+        PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
+        XTALB1L_MARK,
+        GPS_AGC1_MARK, SCIFA0_RTS_MARK,
+        GPS_AGC2_MARK, SCIFA0_SCK_MARK,
+        GPS_AGC3_MARK, SCIFA0_TXD_MARK,
+        GPS_AGC4_MARK, SCIFA0_RXD_MARK,
+        GPS_PWRD_MARK, SCIFA0_CTS_MARK,
+        GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
+        SIUBOMC_MARK, TPU2TO0_MARK,
+        SIUCKB_MARK, TPU2TO1_MARK,
+        SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
+        SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
+        SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
+        SIUBILR_MARK, TPU3TO1_MARK,
+        SIUBIBT_MARK, TPU3TO2_MARK,
+        SIUBISLD_MARK, TPU3TO3_MARK,
+        NMI_MARK, TPU4TO0_MARK,
+        DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
+        IRQ_TMPB_MARK,
+        PWEN_MARK, MFG1_OUT1_MARK,
+        OVCN_MARK, MFG1_IN1_MARK,
+        OVCN2_MARK, MFG1_IN2_MARK,
+
+        /* 49-3 */
+        RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
+        USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
+        SCIFA5_CTS_MARK, MFG0_IN1_MARK,
+        SCIFA5_RTS_MARK, MFG0_IN2_MARK,
+        SCIFA5_RXD_MARK,
+        SCIFA5_TXD_MARK,
+        SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
+        A0_EA0_MARK, BS_MARK,
+        A14_EA14_MARK, PORT102_KEYOUT0_MARK,
+        A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
+        A16_EA16_MARK, PORT104_KEYOUT2_MARK,
+        DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
+        A17_EA17_MARK, PORT105_KEYOUT3_MARK,
+        DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
+        A18_EA18_MARK, PORT106_KEYOUT4_MARK,
+        DV_DL0_MARK, MSIOF0_TSCK_MARK,
+        A19_EA19_MARK, PORT107_KEYOUT5_MARK,
+        DV_DL1_MARK, MSIOF0_TXD_MARK,
+        A20_EA20_MARK, PORT108_KEYIN0_MARK,
+        DV_DL2_MARK, MSIOF0_RSCK_MARK,
+        A21_EA21_MARK, PORT109_KEYIN1_MARK,
+        DV_DL3_MARK, MSIOF0_RSYNC_MARK,
+        A22_EA22_MARK, PORT110_KEYIN2_MARK,
+        DV_DL4_MARK, MSIOF0_MCK0_MARK,
+        A23_EA23_MARK, PORT111_KEYIN3_MARK,
+        DV_DL5_MARK, MSIOF0_MCK1_MARK,
+        A24_EA24_MARK, PORT112_KEYIN4_MARK,
+        DV_DL6_MARK, MSIOF0_RXD_MARK,
+        A25_EA25_MARK, PORT113_KEYIN5_MARK,
+        DV_DL7_MARK, MSIOF0_SS2_MARK,
+        A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
+        D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
+        D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
+        D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
+        D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
+        D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
+        D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
+        CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
+        CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
+        DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
+        A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
+        WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
+        NBRSTOUT_MARK, NBRST_MARK,
+
+        /* 49-4 */
+        RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
+        VIO_VD_MARK, VIO_HD_MARK,
+        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
+        VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
+        VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
+        VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
+        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
+        VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
+        VIO_CKO_MARK,
+        MFG3_IN1_MARK, MFG3_IN2_MARK,
+        M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
+        M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
+        M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
+        M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
+        LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
+        SIUCKA_MARK, MFG0_OUT2_MARK,
+        LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
+        SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
+        LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
+        SIUAOBT_MARK, BBIF2_TSCK1_MARK,
+        LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
+        SIUAOSLD_MARK, BBIF2_TXD1_MARK,
+        LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
+        SIUAISPD_MARK, MFG1_OUT2_MARK,
+        LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
+        SIUAILR_MARK, MFG2_OUT2_MARK,
+        LCDD6_MARK, DV_D6_MARK,
+        SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
+        LCDD7_MARK, DV_D7_MARK,
+        SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
+        LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
+        LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
+        LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
+        LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
+        LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
+        LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
+        LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
+        LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
+        LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
+        LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
+        LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
+        D26_MARK, ED26_MARK,
+        LCDD19_MARK, MSIOF0L_TSYNC_MARK,
+        D27_MARK, ED27_MARK,
+        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
+        D28_MARK, ED28_MARK,
+        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
+        D29_MARK, ED29_MARK,
+        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
+        D30_MARK, ED30_MARK,
+        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
+        D31_MARK, ED31_MARK,
+        LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
+        LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
+
+        /* 49-5 */
+        LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
+        LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
+        LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
+        LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
+        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
+        VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
+        VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
+        VIO_VDR_MARK, VIO_HDR_MARK,
+        VIO_CLKR_MARK, VIO_CKOR_MARK,
+        SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
+        SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
+        SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
+        SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
+        MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
+        MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
+        MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
+        MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
+        MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
+        MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
+        MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
+        MSIOF1_SS1_MARK, EDBGREQ3_MARK,
+        MSIOF1_SS2_MARK,
+        PORT236_IROUT_MARK, IRDA_OUT_MARK,
+        IRDA_IN_MARK, IRDA_FIRSEL_MARK,
+        TPU1TO0_MARK, TS_SPSYNC3_MARK,
+        TPU1TO1_MARK, TS_SDAT3_MARK,
+        TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
+        TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
+        M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
+        M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
+        PORT245_IROUT_MARK, M15_RSW_MARK,
+        SOUT3_MARK, SCIFA2_TXD1_MARK,
+        SIN3_MARK, SCIFA2_RXD1_MARK,
+        XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
+        XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
+        DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+        SDHICLK0_MARK, TCK2_MARK,
+        SDHICD0_MARK,
+        SDHID0_0_MARK, TMS2_MARK,
+        SDHID0_1_MARK, TDO2_MARK,
+        SDHID0_2_MARK, TDI2_MARK,
+        SDHID0_3_MARK, RTCK2_MARK,
+
+        /* 49-6 */
+        SDHICMD0_MARK, TRST2_MARK,
+        SDHIWP0_MARK, EDBGREQ2_MARK,
+        SDHICLK1_MARK, TCK3_MARK,
+        SDHID1_0_MARK, M11_SLCD_SO2_MARK,
+        TS_SPSYNC2_MARK, TMS3_MARK,
+        SDHID1_1_MARK, M9_SLCD_AO2_MARK,
+        TS_SDAT2_MARK, TDO3_MARK,
+        SDHID1_2_MARK, M10_SLCD_CK2_MARK,
+        TS_SDEN2_MARK, TDI3_MARK,
+        SDHID1_3_MARK, M12_SLCD_CE2_MARK,
+        TS_SCK2_MARK, RTCK3_MARK,
+        SDHICMD1_MARK, TRST3_MARK,
+        SDHICLK2_MARK, SCIFB_SCK_MARK,
+        SDHID2_0_MARK, SCIFB_TXD_MARK,
+        SDHID2_1_MARK, SCIFB_CTS_MARK,
+        SDHID2_2_MARK, SCIFB_RXD_MARK,
+        SDHID2_3_MARK, SCIFB_RTS_MARK,
+        SDHICMD2_MARK,
+        RESETOUTS_MARK,
+        DIVLOCK_MARK,
+        PINMUX_MARK_END,
+};
+
+#define PORT_DATA_I(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
+                    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+
+static pinmux_enum_t pinmux_data[] = {
+
+        /* specify valid pin states for each pin in GPIO mode */
+
+        /* 49-1 (GPIO) */
+        PORT_DATA_I_PD(0),
+        PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
+        PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
+        PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
+        PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
+        PORT_DATA_I_PU(13),
+        PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
+        PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
+        PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
+        PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
+        PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
+        PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
+        PORT_DATA_IO_PU(33),
+        PORT_DATA_O(34),
+        PORT_DATA_I_PU(35),
+        PORT_DATA_O(36),
+        PORT_DATA_I_PU_PD(37),
+
+        /* 49-2 (GPIO) */
+        PORT_DATA_IO_PU_PD(38),
+        PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
+        PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
+        PORT_DATA_O(46), PORT_DATA_O(47),
+        PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
+        PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
+        PORT_DATA_O(53),
+        PORT_DATA_IO_PD(54),
+        PORT_DATA_I_PU_PD(55),
+        PORT_DATA_IO_PU_PD(56),
+        PORT_DATA_I_PU_PD(57),
+        PORT_DATA_IO_PU_PD(58),
+        PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
+        PORT_DATA_O(63),
+        PORT_DATA_I_PU(64),
+        PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
+        PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
+        PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
+        PORT_DATA_I_PD(74),
+        PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
+        PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
+        PORT_DATA_O(79),
+        PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
+        PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
+        PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
+        PORT_DATA_I_PD(87),
+        PORT_DATA_IO_PU_PD(88),
+        PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
+
+        /* 49-3 (GPIO) */
+        PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
+        PORT_DATA_I_PU_PD(95),
+        PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
+        PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
+        PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
+        PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
+        PORT_DATA_IO_PD(107),
+        PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
+        PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
+        PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
+        PORT_DATA_IO_PU_PD(114),
+        PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
+        PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
+        PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
+        PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
+        PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
+        PORT_DATA_IO_PU(130),
+        PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
+        PORT_DATA_IO_PU(134),
+        PORT_DATA_O(135), PORT_DATA_O(136),
+        PORT_DATA_I_PU_PD(137),
+        PORT_DATA_IO(138),
+        PORT_DATA_IO_PU_PD(139),
+        PORT_DATA_IO(140), PORT_DATA_IO(141),
+        PORT_DATA_I_PU(142),
+        PORT_DATA_O(143), PORT_DATA_O(144),
+        PORT_DATA_I_PU(145),
+
+        /* 49-4 (GPIO) */
+        PORT_DATA_O(146),
+        PORT_DATA_I_PU_PD(147),
+        PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
+        PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
+        PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
+        PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
+        PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
+        PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
+        PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
+        PORT_DATA_IO_PU_PD(167),
+        PORT_DATA_O(168),
+        PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
+        PORT_DATA_O(171),
+        PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
+        PORT_DATA_O(174),
+        PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
+        PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
+        PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
+        PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
+        PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
+        PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
+        PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
+        PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
+        PORT_DATA_O(199),
+        PORT_DATA_IO_PD(200),
+
+        /* 49-5 (GPIO) */
+        PORT_DATA_O(201),
+        PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
+        PORT_DATA_I(204),
+        PORT_DATA_O(205),
+        PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
+        PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
+        PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
+        PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
+        PORT_DATA_O(217),
+        PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
+        PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
+        PORT_DATA_I_PD(223),
+        PORT_DATA_I_PU_PD(224),
+        PORT_DATA_O(225),
+        PORT_DATA_IO_PD(226),
+        PORT_DATA_IO_PU_PD(227),
+        PORT_DATA_I_PD(228),
+        PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
+        PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
+        PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
+        PORT_DATA_I_PU_PD(235),
+        PORT_DATA_O(236),
+        PORT_DATA_I_PD(237),
+        PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
+        PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
+        PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
+        PORT_DATA_O(244),
+        PORT_DATA_IO_PU_PD(245),
+        PORT_DATA_O(246),
+        PORT_DATA_I_PD(247),
+        PORT_DATA_IO_PU_PD(248),
+        PORT_DATA_I_PU_PD(249),
+        PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
+        PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
+        PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
+        PORT_DATA_IO_PU_PD(256),
+
+        /* 49-6 (GPIO) */
+        PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
+        PORT_DATA_IO_PD(259),
+        PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
+        PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
+        PORT_DATA_O(265),
+        PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
+        PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
+        PORT_DATA_O(271),
+        PORT_DATA_I_PD(272),
+
+        /* Special Pull-up / Pull-down Functions */
+        PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT48_FN2, PORT48_IN_PU),
+        PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT49_FN2, PORT49_IN_PU),
+        PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT50_FN2, PORT50_IN_PU),
+        PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT55_FN2, PORT55_IN_PU),
+        PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT56_FN2, PORT56_IN_PU),
+        PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT57_FN2, PORT57_IN_PU),
+        PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
+                    PORT58_FN2, PORT58_IN_PU),
+
+        /* 49-1 (FN) */
+        PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
+        PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
+        PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
+        PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
+        PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
+        PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
+        PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
+        PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
+        PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
+        PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
+        PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
+        PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
+        PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
+        PINMUX_DATA(SIN2_MARK, PORT12_FN2),
+        PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
+        PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
+        PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
+        PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
+        PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
+        PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
+        PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
+        PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
+        PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
+        PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
+        PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
+        PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
+        PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
+        PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
+        PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
+        PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
+        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+        PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
+        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+        PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
+        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+        PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
+        PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
+        PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
+        PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
+        PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
+        PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
+        PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
+        PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
+        PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
+        PINMUX_DATA(IDIO_MARK, PORT33_FN1),
+        PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
+        PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
+        PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
+        PINMUX_DATA(SIN1_MARK, PORT35_FN1),
+        PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
+        PINMUX_DATA(XWUP_MARK, PORT35_FN3),
+        PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
+        PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
+        PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
+        PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
+        PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
+
+        /* 49-2 (FN) */
+        PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
+        PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
+        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
+        PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
+        PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
+        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
+        PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
+        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
+        PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
+        PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
+        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
+        PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
+        PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
+        PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
+        PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
+        PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
+        PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
+        PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
+        PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
+        PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
+        PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
+        PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
+        PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
+        PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
+        PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
+        PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
+        PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
+        PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
+        PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
+        PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
+        PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
+        PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
+        PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
+        PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
+        PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
+        PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
+        PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
+        PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
+        PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
+        PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
+        PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
+        PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
+        PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
+        PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
+        PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
+        PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
+        PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
+        PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
+        PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
+        PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
+        PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
+        PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
+        PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
+        PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
+        PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
+        PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
+        PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
+        PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
+        PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
+        PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
+        PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
+        PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
+        PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
+        PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
+        PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
+        PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
+        PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
+        PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
+        PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
+        PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
+        PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
+        PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
+        PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
+        PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
+        PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
+        PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
+        PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
+        PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
+        PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
+        PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
+        PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
+        PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
+        PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
+        PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
+        PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
+        PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
+        PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
+        PINMUX_DATA(NMI_MARK, PORT83_FN1),
+        PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
+        PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
+        PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
+        PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
+        PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
+        PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
+        PINMUX_DATA(PWEN_MARK, PORT88_FN1),
+        PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
+        PINMUX_DATA(OVCN_MARK, PORT89_FN1),
+        PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
+        PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
+        PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
+
+        /* 49-3 (FN) */
+        PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
+        PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
+        PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
+        PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
+        PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
+        PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
+        PINMUX_DATA(IDIN_MARK, PORT95_FN1),
+        PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
+        PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
+        PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
+        PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
+        PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
+        PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
+        PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
+        PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
+        PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
+        PINMUX_DATA(BS_MARK, PORT101_FN2),
+        PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
+        PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
+        PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
+        PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
+        PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
+        PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
+        PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
+        PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
+        PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
+        PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
+        PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
+        PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
+        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
+        PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
+        PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
+        PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
+        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
+        PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
+        PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
+        PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
+        PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
+        PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
+        PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
+        PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
+        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
+        PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
+        PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
+        PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
+        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
+        PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
+        PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
+        PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
+        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
+        PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
+        PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
+        PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
+        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
+        PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
+        PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
+        PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
+        PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
+        PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
+        PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
+        PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
+        PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
+        PINMUX_DATA(A26_MARK, PORT114_FN1),
+        PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
+        PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
+        PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
+        PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
+        PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
+        PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
+        PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
+        PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
+        PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
+        PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
+        PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
+        PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
+        PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
+        PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
+        PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
+        PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
+        PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
+        PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
+        PINMUX_DATA(CS4_MARK, PORT131_FN1),
+        PINMUX_DATA(CS5A_MARK, PORT132_FN1),
+        PINMUX_DATA(CS5B_MARK, PORT133_FN1),
+        PINMUX_DATA(FCE1_MARK, PORT133_FN2),
+        PINMUX_DATA(CS6B_MARK, PORT134_FN1),
+        PINMUX_DATA(XCS2_MARK, PORT134_FN2),
+        PINMUX_DATA(FCE0_MARK, PORT135_FN1),
+        PINMUX_DATA(CS6A_MARK, PORT136_FN1),
+        PINMUX_DATA(DACK0_MARK, PORT136_FN2),
+        PINMUX_DATA(WAIT_MARK, PORT137_FN1),
+        PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
+        PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
+        PINMUX_DATA(A27_MARK, PORT139_FN1),
+        PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
+        PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
+        PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
+        PINMUX_DATA(FRB_MARK, PORT142_FN1),
+        PINMUX_DATA(CKO_MARK, PORT143_FN1),
+        PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
+        PINMUX_DATA(NBRST_MARK, PORT145_FN1),
+
+        /* 49-4 (FN) */
+        PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
+        PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
+        PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
+        PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
+        PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
+        PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
+        PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
+        PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
+        PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
+        PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
+        PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
+        PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
+        PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
+        PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
+        PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
+        PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
+        PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
+        PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
+        PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
+        PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
+        PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
+        PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
+        PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
+        PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
+        PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
+        PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
+        PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
+        PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
+        PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
+        PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
+        PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
+        PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
+        PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
+        PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
+        PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
+        PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
+        PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
+        PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
+        PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
+        PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
+        PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
+        PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
+        PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
+        PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
+        PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
+        PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
+        PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
+        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
+        PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
+        PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
+        PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
+        PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
+        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
+        PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
+        PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
+        PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
+        PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
+        PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
+        PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
+        PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
+        PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
+        PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
+        PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
+        PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
+        PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
+        PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
+        PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
+        PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
+        PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
+        PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
+        PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
+        PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
+        PINMUX_DATA(XWR2_MARK, PORT181_FN7),
+        PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
+        PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
+        PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
+        PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
+        PINMUX_DATA(XWR3_MARK, PORT182_FN7),
+        PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
+        PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
+        PINMUX_DATA(D16_MARK, PORT183_FN6),
+        PINMUX_DATA(ED16_MARK, PORT183_FN7),
+        PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
+        PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
+        PINMUX_DATA(D17_MARK, PORT184_FN6),
+        PINMUX_DATA(ED17_MARK, PORT184_FN7),
+        PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
+        PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
+        PINMUX_DATA(D18_MARK, PORT185_FN6),
+        PINMUX_DATA(ED18_MARK, PORT185_FN7),
+        PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
+        PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
+        PINMUX_DATA(D19_MARK, PORT186_FN6),
+        PINMUX_DATA(ED19_MARK, PORT186_FN7),
+        PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
+        PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
+        PINMUX_DATA(D20_MARK, PORT187_FN6),
+        PINMUX_DATA(ED20_MARK, PORT187_FN7),
+        PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
+        PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
+        PINMUX_DATA(D21_MARK, PORT188_FN6),
+        PINMUX_DATA(ED21_MARK, PORT188_FN7),
+        PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
+        PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
+        PINMUX_DATA(D22_MARK, PORT189_FN6),
+        PINMUX_DATA(ED22_MARK, PORT189_FN7),
+        PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
+        PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
+        PINMUX_DATA(D23_MARK, PORT190_FN6),
+        PINMUX_DATA(ED23_MARK, PORT190_FN7),
+        PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
+        PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
+        PINMUX_DATA(D24_MARK, PORT191_FN6),
+        PINMUX_DATA(ED24_MARK, PORT191_FN7),
+        PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
+        PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
+        PINMUX_DATA(D25_MARK, PORT192_FN6),
+        PINMUX_DATA(ED25_MARK, PORT192_FN7),
+        PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
+        PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
+        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
+        PINMUX_DATA(D26_MARK, PORT193_FN6),
+        PINMUX_DATA(ED26_MARK, PORT193_FN7),
+        PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
+        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
+        PINMUX_DATA(D27_MARK, PORT194_FN6),
+        PINMUX_DATA(ED27_MARK, PORT194_FN7),
+        PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
+        PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
+        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
+        PINMUX_DATA(D28_MARK, PORT195_FN6),
+        PINMUX_DATA(ED28_MARK, PORT195_FN7),
+        PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
+        PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
+        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
+        PINMUX_DATA(D29_MARK, PORT196_FN6),
+        PINMUX_DATA(ED29_MARK, PORT196_FN7),
+        PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
+        PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
+        PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
+        PINMUX_DATA(D30_MARK, PORT197_FN6),
+        PINMUX_DATA(ED30_MARK, PORT197_FN7),
+        PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
+        PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
+        PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
+        PINMUX_DATA(D31_MARK, PORT198_FN6),
+        PINMUX_DATA(ED31_MARK, PORT198_FN7),
+        PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
+        PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
+        PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
+        PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
+        PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
+        PINMUX_DATA(DACK2_MARK, PORT200_FN2),
+        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
+
+        /* 49-5 (FN) */
+        PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
+        PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
+        PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
+        PINMUX_DATA(DACK3_MARK, PORT201_FN4),
+        PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
+        PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
+        PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
+        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
+        PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
+        PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
+        PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
+        PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
+        PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
+        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
+        PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
+        PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
+        PINMUX_DATA(DACK1_MARK, PORT205_FN3),
+        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
+        PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
+        PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
+        PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
+        PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
+        PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
+        PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
+        PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
+        PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
+        PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
+        PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
+        PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
+        PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
+        PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
+        PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
+        PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
+        PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
+        PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
+        PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
+        PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
+        PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
+        PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
+        PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
+        PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
+        PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
+        PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
+        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
+        PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
+        PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
+        PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
+        PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
+        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
+        PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
+        PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
+        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
+        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
+        PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
+        PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
+        PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
+        PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
+        PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
+        PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
+        PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
+        PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
+        PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
+        PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
+        PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
+        PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
+        PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
+        PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
+        PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
+        PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
+        PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
+        PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
+        PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
+        PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
+        PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
+        PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
+        PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
+        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
+        PINMUX_DATA(SIN3_MARK, PORT247_FN1),
+        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
+        PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
+        PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
+        PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
+        PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
+        PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
+        PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
+        PINMUX_DATA(DINT_MARK, PORT250_FN1),
+        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
+        PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
+        PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
+        PINMUX_DATA(TCK2_MARK, PORT251_FN2),
+        PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
+        PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
+        PINMUX_DATA(TMS2_MARK, PORT253_FN2),
+        PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
+        PINMUX_DATA(TDO2_MARK, PORT254_FN2),
+        PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
+        PINMUX_DATA(TDI2_MARK, PORT255_FN2),
+        PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
+        PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
+
+        /* 49-6 (FN) */
+        PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
+        PINMUX_DATA(TRST2_MARK, PORT257_FN2),
+        PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
+        PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
+        PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
+        PINMUX_DATA(TCK3_MARK, PORT259_FN4),
+        PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
+        PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
+        PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
+        PINMUX_DATA(TMS3_MARK, PORT260_FN4),
+        PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
+        PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
+        PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
+        PINMUX_DATA(TDO3_MARK, PORT261_FN4),
+        PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
+        PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
+        PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
+        PINMUX_DATA(TDI3_MARK, PORT262_FN4),
+        PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
+        PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
+        PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
+        PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
+        PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
+        PINMUX_DATA(TRST3_MARK, PORT264_FN4),
+        PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
+        PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
+        PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
+        PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
+        PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
+        PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
+        PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
+        PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
+        PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
+        PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
+        PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
+        PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
+        PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
+};
+
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define GPIO_PORT_273() _273(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* 49-1 -> 49-6 (GPIO) */
+        GPIO_PORT_273(),
+
+        /* Special Pull-up / Pull-down Functions */
+        GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
+        GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
+        GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
+        GPIO_FN(PORT58_KEYIN6_PU),
+
+        /* 49-1 (FN) */
+        GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
+        GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
+        GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
+        GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
+        GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
+        GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
+        GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
+        GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
+        GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
+        GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
+        GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
+        GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
+        GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
+        GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
+        GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
+
+        /* 49-2 (FN) */
+        GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
+        GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
+        GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
+        GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
+        GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
+        GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
+        GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
+        GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
+        GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
+        GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
+        GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
+        GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
+        GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
+        GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
+        GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
+        GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
+        GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
+        GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
+        GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
+        GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
+        GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
+        GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
+        GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
+        GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
+        GPIO_FN(XTALB1L),
+        GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
+        GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
+        GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
+        GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
+        GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
+        GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
+        GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
+        GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
+        GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
+        GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
+        GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
+        GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
+        GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
+        GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
+        GPIO_FN(NMI), GPIO_FN(TPU4TO0),
+        GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
+        GPIO_FN(IRQ_TMPB),
+        GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
+        GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
+        GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
+
+        /* 49-3 (FN) */
+        GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
+        GPIO_FN(PORT93_VIO_CKO2),
+        GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
+        GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
+        GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
+        GPIO_FN(SCIFA5_RXD),
+        GPIO_FN(SCIFA5_TXD),
+        GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
+        GPIO_FN(A0_EA0), GPIO_FN(BS),
+        GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
+        GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
+        GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
+        GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
+        GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
+        GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
+        GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
+        GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
+        GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
+        GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
+        GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
+        GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
+        GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
+        GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
+        GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
+        GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
+        GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
+        GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
+        GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
+        GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
+        GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
+        GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
+        GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
+        GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
+        GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
+        GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
+        GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
+        GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
+        GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
+        GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
+        GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
+        GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
+        GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
+        GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
+
+        /* 49-4 (FN) */
+        GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
+        GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
+        GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
+        GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
+        GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
+        GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
+        GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
+        GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
+        GPIO_FN(VIO_CKO),
+        GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
+        GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
+        GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
+        GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
+        GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
+        GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
+        GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
+        GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
+        GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
+        GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
+        GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
+        GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
+        GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
+        GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
+        GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
+        GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
+        GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
+        GPIO_FN(LCDD6), GPIO_FN(DV_D6),
+        GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
+        GPIO_FN(LCDD7), GPIO_FN(DV_D7),
+        GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
+        GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
+        GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
+        GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
+        GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
+        GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
+        GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
+        GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
+        GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
+        GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
+        GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
+        GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
+        GPIO_FN(D26), GPIO_FN(ED26),
+        GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
+        GPIO_FN(D27), GPIO_FN(ED27),
+        GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
+        GPIO_FN(D28), GPIO_FN(ED28),
+        GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
+        GPIO_FN(D29), GPIO_FN(ED29),
+        GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
+        GPIO_FN(D30), GPIO_FN(ED30),
+        GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
+        GPIO_FN(D31), GPIO_FN(ED31),
+        GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
+        GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
+
+        /* 49-5 (FN) */
+        GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
+        GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
+        GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
+        GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
+        GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
+        GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
+        GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
+        GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
+        GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
+        GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
+        GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
+        GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
+        GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
+        GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
+        GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
+        GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
+        GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
+        GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
+        GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
+        GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
+        GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
+        GPIO_FN(MSIOF1_SS2),
+        GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
+        GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
+        GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
+        GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
+        GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
+        GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
+        GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
+        GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
+        GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
+        GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
+        GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
+        GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
+        GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
+        GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
+        GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
+        GPIO_FN(SDHICD0),
+        GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
+        GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
+        GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
+        GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
+
+        /* 49-6 (FN) */
+        GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
+        GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
+        GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
+        GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
+        GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
+        GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
+        GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
+        GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
+        GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
+        GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
+        GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
+        GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
+        GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
+        GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
+        GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
+        GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
+        GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
+        GPIO_FN(SDHICMD2),
+        GPIO_FN(RESETOUTS),
+        GPIO_FN(DIVLOCK),
+};
+
+/* helper for top 4 bits in PORTnCR */
+#define PCRH(in, in_pd, in_pu, out)             \
+        0, (out), (in), 0,                      \
+        0, 0, 0, 0,                             \
+        0, 0, (in_pd), 0,                       \
+        0, 0, (in_pu), 0
+
+#define PORTCR(nr, reg)                                         \
+        { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {           \
+                PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,           \
+                     PORT##nr##_IN_PU, PORT##nr##_OUT),         \
+                PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
+                PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
+                PORT##nr##_FN6, PORT##nr##_FN7 }                \
+        }
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        PORTCR(0, 0xe6050000), /* PORT0CR */
+        PORTCR(1, 0xe6050001), /* PORT1CR */
+        PORTCR(2, 0xe6050002), /* PORT2CR */
+        PORTCR(3, 0xe6050003), /* PORT3CR */
+        PORTCR(4, 0xe6050004), /* PORT4CR */
+        PORTCR(5, 0xe6050005), /* PORT5CR */
+        PORTCR(6, 0xe6050006), /* PORT6CR */
+        PORTCR(7, 0xe6050007), /* PORT7CR */
+        PORTCR(8, 0xe6050008), /* PORT8CR */
+        PORTCR(9, 0xe6050009), /* PORT9CR */
+
+        PORTCR(10, 0xe605000a), /* PORT10CR */
+        PORTCR(11, 0xe605000b), /* PORT11CR */
+        PORTCR(12, 0xe605000c), /* PORT12CR */
+        PORTCR(13, 0xe605000d), /* PORT13CR */
+        PORTCR(14, 0xe605000e), /* PORT14CR */
+        PORTCR(15, 0xe605000f), /* PORT15CR */
+        PORTCR(16, 0xe6050010), /* PORT16CR */
+        PORTCR(17, 0xe6050011), /* PORT17CR */
+        PORTCR(18, 0xe6050012), /* PORT18CR */
+        PORTCR(19, 0xe6050013), /* PORT19CR */
+
+        PORTCR(20, 0xe6050014), /* PORT20CR */
+        PORTCR(21, 0xe6050015), /* PORT21CR */
+        PORTCR(22, 0xe6050016), /* PORT22CR */
+        PORTCR(23, 0xe6050017), /* PORT23CR */
+        PORTCR(24, 0xe6050018), /* PORT24CR */
+        PORTCR(25, 0xe6050019), /* PORT25CR */
+        PORTCR(26, 0xe605001a), /* PORT26CR */
+        PORTCR(27, 0xe605001b), /* PORT27CR */
+        PORTCR(28, 0xe605001c), /* PORT28CR */
+        PORTCR(29, 0xe605001d), /* PORT29CR */
+
+        PORTCR(30, 0xe605001e), /* PORT30CR */
+        PORTCR(31, 0xe605001f), /* PORT31CR */
+        PORTCR(32, 0xe6050020), /* PORT32CR */
+        PORTCR(33, 0xe6050021), /* PORT33CR */
+        PORTCR(34, 0xe6050022), /* PORT34CR */
+        PORTCR(35, 0xe6050023), /* PORT35CR */
+        PORTCR(36, 0xe6050024), /* PORT36CR */
+        PORTCR(37, 0xe6050025), /* PORT37CR */
+        PORTCR(38, 0xe6050026), /* PORT38CR */
+        PORTCR(39, 0xe6050027), /* PORT39CR */
+
+        PORTCR(40, 0xe6050028), /* PORT40CR */
+        PORTCR(41, 0xe6050029), /* PORT41CR */
+        PORTCR(42, 0xe605002a), /* PORT42CR */
+        PORTCR(43, 0xe605002b), /* PORT43CR */
+        PORTCR(44, 0xe605002c), /* PORT44CR */
+        PORTCR(45, 0xe605002d), /* PORT45CR */
+        PORTCR(46, 0xe605002e), /* PORT46CR */
+        PORTCR(47, 0xe605002f), /* PORT47CR */
+        PORTCR(48, 0xe6050030), /* PORT48CR */
+        PORTCR(49, 0xe6050031), /* PORT49CR */
+
+        PORTCR(50, 0xe6050032), /* PORT50CR */
+        PORTCR(51, 0xe6050033), /* PORT51CR */
+        PORTCR(52, 0xe6050034), /* PORT52CR */
+        PORTCR(53, 0xe6050035), /* PORT53CR */
+        PORTCR(54, 0xe6050036), /* PORT54CR */
+        PORTCR(55, 0xe6050037), /* PORT55CR */
+        PORTCR(56, 0xe6050038), /* PORT56CR */
+        PORTCR(57, 0xe6050039), /* PORT57CR */
+        PORTCR(58, 0xe605003a), /* PORT58CR */
+        PORTCR(59, 0xe605003b), /* PORT59CR */
+
+        PORTCR(60, 0xe605003c), /* PORT60CR */
+        PORTCR(61, 0xe605003d), /* PORT61CR */
+        PORTCR(62, 0xe605003e), /* PORT62CR */
+        PORTCR(63, 0xe605003f), /* PORT63CR */
+        PORTCR(64, 0xe6050040), /* PORT64CR */
+        PORTCR(65, 0xe6050041), /* PORT65CR */
+        PORTCR(66, 0xe6050042), /* PORT66CR */
+        PORTCR(67, 0xe6050043), /* PORT67CR */
+        PORTCR(68, 0xe6050044), /* PORT68CR */
+        PORTCR(69, 0xe6050045), /* PORT69CR */
+
+        PORTCR(70, 0xe6050046), /* PORT70CR */
+        PORTCR(71, 0xe6050047), /* PORT71CR */
+        PORTCR(72, 0xe6050048), /* PORT72CR */
+        PORTCR(73, 0xe6050049), /* PORT73CR */
+        PORTCR(74, 0xe605004a), /* PORT74CR */
+        PORTCR(75, 0xe605004b), /* PORT75CR */
+        PORTCR(76, 0xe605004c), /* PORT76CR */
+        PORTCR(77, 0xe605004d), /* PORT77CR */
+        PORTCR(78, 0xe605004e), /* PORT78CR */
+        PORTCR(79, 0xe605004f), /* PORT79CR */
+
+        PORTCR(80, 0xe6050050), /* PORT80CR */
+        PORTCR(81, 0xe6050051), /* PORT81CR */
+        PORTCR(82, 0xe6050052), /* PORT82CR */
+        PORTCR(83, 0xe6050053), /* PORT83CR */
+        PORTCR(84, 0xe6050054), /* PORT84CR */
+        PORTCR(85, 0xe6050055), /* PORT85CR */
+        PORTCR(86, 0xe6050056), /* PORT86CR */
+        PORTCR(87, 0xe6050057), /* PORT87CR */
+        PORTCR(88, 0xe6051058), /* PORT88CR */
+        PORTCR(89, 0xe6051059), /* PORT89CR */
+
+        PORTCR(90, 0xe605105a), /* PORT90CR */
+        PORTCR(91, 0xe605105b), /* PORT91CR */
+        PORTCR(92, 0xe605105c), /* PORT92CR */
+        PORTCR(93, 0xe605105d), /* PORT93CR */
+        PORTCR(94, 0xe605105e), /* PORT94CR */
+        PORTCR(95, 0xe605105f), /* PORT95CR */
+        PORTCR(96, 0xe6051060), /* PORT96CR */
+        PORTCR(97, 0xe6051061), /* PORT97CR */
+        PORTCR(98, 0xe6051062), /* PORT98CR */
+        PORTCR(99, 0xe6051063), /* PORT99CR */
+
+        PORTCR(100, 0xe6051064), /* PORT100CR */
+        PORTCR(101, 0xe6051065), /* PORT101CR */
+        PORTCR(102, 0xe6051066), /* PORT102CR */
+        PORTCR(103, 0xe6051067), /* PORT103CR */
+        PORTCR(104, 0xe6051068), /* PORT104CR */
+        PORTCR(105, 0xe6051069), /* PORT105CR */
+        PORTCR(106, 0xe605106a), /* PORT106CR */
+        PORTCR(107, 0xe605106b), /* PORT107CR */
+        PORTCR(108, 0xe605106c), /* PORT108CR */
+        PORTCR(109, 0xe605106d), /* PORT109CR */
+
+        PORTCR(110, 0xe605106e), /* PORT110CR */
+        PORTCR(111, 0xe605106f), /* PORT111CR */
+        PORTCR(112, 0xe6051070), /* PORT112CR */
+        PORTCR(113, 0xe6051071), /* PORT113CR */
+        PORTCR(114, 0xe6051072), /* PORT114CR */
+        PORTCR(115, 0xe6051073), /* PORT115CR */
+        PORTCR(116, 0xe6051074), /* PORT116CR */
+        PORTCR(117, 0xe6051075), /* PORT117CR */
+        PORTCR(118, 0xe6051076), /* PORT118CR */
+        PORTCR(119, 0xe6051077), /* PORT119CR */
+
+        PORTCR(120, 0xe6051078), /* PORT120CR */
+        PORTCR(121, 0xe6051079), /* PORT121CR */
+        PORTCR(122, 0xe605107a), /* PORT122CR */
+        PORTCR(123, 0xe605107b), /* PORT123CR */
+        PORTCR(124, 0xe605107c), /* PORT124CR */
+        PORTCR(125, 0xe605107d), /* PORT125CR */
+        PORTCR(126, 0xe605107e), /* PORT126CR */
+        PORTCR(127, 0xe605107f), /* PORT127CR */
+        PORTCR(128, 0xe6051080), /* PORT128CR */
+        PORTCR(129, 0xe6051081), /* PORT129CR */
+
+        PORTCR(130, 0xe6051082), /* PORT130CR */
+        PORTCR(131, 0xe6051083), /* PORT131CR */
+        PORTCR(132, 0xe6051084), /* PORT132CR */
+        PORTCR(133, 0xe6051085), /* PORT133CR */
+        PORTCR(134, 0xe6051086), /* PORT134CR */
+        PORTCR(135, 0xe6051087), /* PORT135CR */
+        PORTCR(136, 0xe6051088), /* PORT136CR */
+        PORTCR(137, 0xe6051089), /* PORT137CR */
+        PORTCR(138, 0xe605108a), /* PORT138CR */
+        PORTCR(139, 0xe605108b), /* PORT139CR */
+
+        PORTCR(140, 0xe605108c), /* PORT140CR */
+        PORTCR(141, 0xe605108d), /* PORT141CR */
+        PORTCR(142, 0xe605108e), /* PORT142CR */
+        PORTCR(143, 0xe605108f), /* PORT143CR */
+        PORTCR(144, 0xe6051090), /* PORT144CR */
+        PORTCR(145, 0xe6051091), /* PORT145CR */
+        PORTCR(146, 0xe6051092), /* PORT146CR */
+        PORTCR(147, 0xe6051093), /* PORT147CR */
+        PORTCR(148, 0xe6051094), /* PORT148CR */
+        PORTCR(149, 0xe6051095), /* PORT149CR */
+
+        PORTCR(150, 0xe6051096), /* PORT150CR */
+        PORTCR(151, 0xe6051097), /* PORT151CR */
+        PORTCR(152, 0xe6051098), /* PORT152CR */
+        PORTCR(153, 0xe6051099), /* PORT153CR */
+        PORTCR(154, 0xe605109a), /* PORT154CR */
+        PORTCR(155, 0xe605109b), /* PORT155CR */
+        PORTCR(156, 0xe605109c), /* PORT156CR */
+        PORTCR(157, 0xe605109d), /* PORT157CR */
+        PORTCR(158, 0xe605109e), /* PORT158CR */
+        PORTCR(159, 0xe605109f), /* PORT159CR */
+
+        PORTCR(160, 0xe60510a0), /* PORT160CR */
+        PORTCR(161, 0xe60510a1), /* PORT161CR */
+        PORTCR(162, 0xe60510a2), /* PORT162CR */
+        PORTCR(163, 0xe60510a3), /* PORT163CR */
+        PORTCR(164, 0xe60510a4), /* PORT164CR */
+        PORTCR(165, 0xe60510a5), /* PORT165CR */
+        PORTCR(166, 0xe60510a6), /* PORT166CR */
+        PORTCR(167, 0xe60510a7), /* PORT167CR */
+        PORTCR(168, 0xe60510a8), /* PORT168CR */
+        PORTCR(169, 0xe60510a9), /* PORT169CR */
+
+        PORTCR(170, 0xe60510aa), /* PORT170CR */
+        PORTCR(171, 0xe60510ab), /* PORT171CR */
+        PORTCR(172, 0xe60510ac), /* PORT172CR */
+        PORTCR(173, 0xe60510ad), /* PORT173CR */
+        PORTCR(174, 0xe60510ae), /* PORT174CR */
+        PORTCR(175, 0xe60520af), /* PORT175CR */
+        PORTCR(176, 0xe60520b0), /* PORT176CR */
+        PORTCR(177, 0xe60520b1), /* PORT177CR */
+        PORTCR(178, 0xe60520b2), /* PORT178CR */
+        PORTCR(179, 0xe60520b3), /* PORT179CR */
+
+        PORTCR(180, 0xe60520b4), /* PORT180CR */
+        PORTCR(181, 0xe60520b5), /* PORT181CR */
+        PORTCR(182, 0xe60520b6), /* PORT182CR */
+        PORTCR(183, 0xe60520b7), /* PORT183CR */
+        PORTCR(184, 0xe60520b8), /* PORT184CR */
+        PORTCR(185, 0xe60520b9), /* PORT185CR */
+        PORTCR(186, 0xe60520ba), /* PORT186CR */
+        PORTCR(187, 0xe60520bb), /* PORT187CR */
+        PORTCR(188, 0xe60520bc), /* PORT188CR */
+        PORTCR(189, 0xe60520bd), /* PORT189CR */
+
+        PORTCR(190, 0xe60520be), /* PORT190CR */
+        PORTCR(191, 0xe60520bf), /* PORT191CR */
+        PORTCR(192, 0xe60520c0), /* PORT192CR */
+        PORTCR(193, 0xe60520c1), /* PORT193CR */
+        PORTCR(194, 0xe60520c2), /* PORT194CR */
+        PORTCR(195, 0xe60520c3), /* PORT195CR */
+        PORTCR(196, 0xe60520c4), /* PORT196CR */
+        PORTCR(197, 0xe60520c5), /* PORT197CR */
+        PORTCR(198, 0xe60520c6), /* PORT198CR */
+        PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+        PORTCR(200, 0xe60520c8), /* PORT200CR */
+        PORTCR(201, 0xe60520c9), /* PORT201CR */
+        PORTCR(202, 0xe60520ca), /* PORT202CR */
+        PORTCR(203, 0xe60520cb), /* PORT203CR */
+        PORTCR(204, 0xe60520cc), /* PORT204CR */
+        PORTCR(205, 0xe60520cd), /* PORT205CR */
+        PORTCR(206, 0xe60520ce), /* PORT206CR */
+        PORTCR(207, 0xe60520cf), /* PORT207CR */
+        PORTCR(208, 0xe60520d0), /* PORT208CR */
+        PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+        PORTCR(210, 0xe60520d2), /* PORT210CR */
+        PORTCR(211, 0xe60520d3), /* PORT211CR */
+        PORTCR(212, 0xe60520d4), /* PORT212CR */
+        PORTCR(213, 0xe60520d5), /* PORT213CR */
+        PORTCR(214, 0xe60520d6), /* PORT214CR */
+        PORTCR(215, 0xe60520d7), /* PORT215CR */
+        PORTCR(216, 0xe60520d8), /* PORT216CR */
+        PORTCR(217, 0xe60520d9), /* PORT217CR */
+        PORTCR(218, 0xe60520da), /* PORT218CR */
+        PORTCR(219, 0xe60520db), /* PORT219CR */
+
+        PORTCR(220, 0xe60520dc), /* PORT220CR */
+        PORTCR(221, 0xe60520dd), /* PORT221CR */
+        PORTCR(222, 0xe60520de), /* PORT222CR */
+        PORTCR(223, 0xe60520df), /* PORT223CR */
+        PORTCR(224, 0xe60520e0), /* PORT224CR */
+        PORTCR(225, 0xe60520e1), /* PORT225CR */
+        PORTCR(226, 0xe60520e2), /* PORT226CR */
+        PORTCR(227, 0xe60520e3), /* PORT227CR */
+        PORTCR(228, 0xe60520e4), /* PORT228CR */
+        PORTCR(229, 0xe60520e5), /* PORT229CR */
+
+        PORTCR(230, 0xe60520e6), /* PORT230CR */
+        PORTCR(231, 0xe60520e7), /* PORT231CR */
+        PORTCR(232, 0xe60520e8), /* PORT232CR */
+        PORTCR(233, 0xe60520e9), /* PORT233CR */
+        PORTCR(234, 0xe60520ea), /* PORT234CR */
+        PORTCR(235, 0xe60520eb), /* PORT235CR */
+        PORTCR(236, 0xe60530ec), /* PORT236CR */
+        PORTCR(237, 0xe60530ed), /* PORT237CR */
+        PORTCR(238, 0xe60530ee), /* PORT238CR */
+        PORTCR(239, 0xe60530ef), /* PORT239CR */
+
+        PORTCR(240, 0xe60530f0), /* PORT240CR */
+        PORTCR(241, 0xe60530f1), /* PORT241CR */
+        PORTCR(242, 0xe60530f2), /* PORT242CR */
+        PORTCR(243, 0xe60530f3), /* PORT243CR */
+        PORTCR(244, 0xe60530f4), /* PORT244CR */
+        PORTCR(245, 0xe60530f5), /* PORT245CR */
+        PORTCR(246, 0xe60530f6), /* PORT246CR */
+        PORTCR(247, 0xe60530f7), /* PORT247CR */
+        PORTCR(248, 0xe60530f8), /* PORT248CR */
+        PORTCR(249, 0xe60530f9), /* PORT249CR */
+
+        PORTCR(250, 0xe60530fa), /* PORT250CR */
+        PORTCR(251, 0xe60530fb), /* PORT251CR */
+        PORTCR(252, 0xe60530fc), /* PORT252CR */
+        PORTCR(253, 0xe60530fd), /* PORT253CR */
+        PORTCR(254, 0xe60530fe), /* PORT254CR */
+        PORTCR(255, 0xe60530ff), /* PORT255CR */
+        PORTCR(256, 0xe6053100), /* PORT256CR */
+        PORTCR(257, 0xe6053101), /* PORT257CR */
+        PORTCR(258, 0xe6053102), /* PORT258CR */
+        PORTCR(259, 0xe6053103), /* PORT259CR */
+
+        PORTCR(260, 0xe6053104), /* PORT260CR */
+        PORTCR(261, 0xe6053105), /* PORT261CR */
+        PORTCR(262, 0xe6053106), /* PORT262CR */
+        PORTCR(263, 0xe6053107), /* PORT263CR */
+        PORTCR(264, 0xe6053108), /* PORT264CR */
+        PORTCR(265, 0xe6053109), /* PORT265CR */
+        PORTCR(266, 0xe605310a), /* PORT266CR */
+        PORTCR(267, 0xe605310b), /* PORT267CR */
+        PORTCR(268, 0xe605310c), /* PORT268CR */
+        PORTCR(269, 0xe605310d), /* PORT269CR */
+
+        PORTCR(270, 0xe605310e), /* PORT270CR */
+        PORTCR(271, 0xe605310f), /* PORT271CR */
+        PORTCR(272, 0xe6053110), /* PORT272CR */
+
+        { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
+                0, 0,
+                0, 0 }
+        },
+        { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+                PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+                PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+                PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+                PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+                PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+                PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+                PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+                PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+        },
+        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
+                PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+                PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+                PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+                PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+                PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+                PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+                PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+                PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+        },
+        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
+                PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+                PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+                PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+                PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+                PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+                PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+                PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+                PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
+                PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+                PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
+                PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+                PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+                PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+                PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+                PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+                PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
+                PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+                PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+                PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+                PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+                PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+                PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+                PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+                PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
+                PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
+                PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
+                PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
+                PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+                PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+                PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+                PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
+                PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
+                PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+                PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+                PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+                PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+                PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+                PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+                PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+                PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+                PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+                PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+                PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+                PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+                PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+                PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+                PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+                PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, PORT272_DATA,
+                PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+                PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+                PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+                PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7367_pinmux_info = {
+        .name = "sh7367_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PORT0,
+        .last_gpio = GPIO_FN_DIVLOCK,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void sh7367_pinmux_init(void)
+{
+        register_pinmux(&sh7367_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
new file mode 100644
index 000000000000..9c265dae138a
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -0,0 +1,1640 @@
+/*
+ * sh7372 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010  Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on
+ * sh7367 processor support - PFC hardware block
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/sh7372.h>
+
+#define _1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define _10(fn, pfx, sfx)                               \
+        _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx),       \
+        _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx),       \
+        _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx),       \
+        _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx),       \
+        _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
+
+#define _80(fn, pfx, sfx)                               \
+        _10(fn, pfx##1, sfx),   _10(fn, pfx##2, sfx),   \
+        _10(fn, pfx##3, sfx),   _10(fn, pfx##4, sfx),   \
+        _10(fn, pfx##5, sfx),   _10(fn, pfx##6, sfx),   \
+        _10(fn, pfx##7, sfx),   _10(fn, pfx##8, sfx)
+
+#define _190(fn, pfx, sfx) \
+        _10(fn, pfx, sfx), _80(fn, pfx, sfx), _10(fn, pfx##9, sfx), \
+        _10(fn, pfx##10, sfx), _80(fn, pfx##1, sfx), _1(fn, pfx##190, sfx)
+
+#define _PORT(pfx, sfx) pfx##_##sfx
+#define PORT_ALL(str) _190(_PORT, PORT, str)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        /* PORT0_DATA -> PORT190_DATA */
+        PINMUX_DATA_BEGIN,
+        PORT_ALL(DATA),
+        PINMUX_DATA_END,
+
+        /* PORT0_IN -> PORT190_IN */
+        PINMUX_INPUT_BEGIN,
+        PORT_ALL(IN),
+        PINMUX_INPUT_END,
+
+        /* PORT0_IN_PU -> PORT190_IN_PU */
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PORT_ALL(IN_PU),
+        PINMUX_INPUT_PULLUP_END,
+
+        /* PORT0_IN_PD -> PORT190_IN_PD */
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PORT_ALL(IN_PD),
+        PINMUX_INPUT_PULLDOWN_END,
+
+        /* PORT0_OUT -> PORT190_OUT */
+        PINMUX_OUTPUT_BEGIN,
+        PORT_ALL(OUT),
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PORT_ALL(FN_IN),        /* PORT0_FN_IN  -> PORT190_FN_IN */
+        PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT190_FN_OUT */
+        PORT_ALL(FN0),          /* PORT0_FN0    -> PORT190_FN0 */
+        PORT_ALL(FN1),          /* PORT0_FN1    -> PORT190_FN1 */
+        PORT_ALL(FN2),          /* PORT0_FN2    -> PORT190_FN2 */
+        PORT_ALL(FN3),          /* PORT0_FN3    -> PORT190_FN3 */
+        PORT_ALL(FN4),          /* PORT0_FN4    -> PORT190_FN4 */
+        PORT_ALL(FN5),          /* PORT0_FN5    -> PORT190_FN5 */
+        PORT_ALL(FN6),          /* PORT0_FN6    -> PORT190_FN6 */
+        PORT_ALL(FN7),          /* PORT0_FN7    -> PORT190_FN7 */
+
+        MSEL1CR_31_0,   MSEL1CR_31_1,
+        MSEL1CR_30_0,   MSEL1CR_30_1,
+        MSEL1CR_29_0,   MSEL1CR_29_1,
+        MSEL1CR_28_0,   MSEL1CR_28_1,
+        MSEL1CR_27_0,   MSEL1CR_27_1,
+        MSEL1CR_26_0,   MSEL1CR_26_1,
+        MSEL1CR_16_0,   MSEL1CR_16_1,
+        MSEL1CR_15_0,   MSEL1CR_15_1,
+        MSEL1CR_14_0,   MSEL1CR_14_1,
+        MSEL1CR_13_0,   MSEL1CR_13_1,
+        MSEL1CR_12_0,   MSEL1CR_12_1,
+        MSEL1CR_9_0,    MSEL1CR_9_1,
+        MSEL1CR_8_0,    MSEL1CR_8_1,
+        MSEL1CR_7_0,    MSEL1CR_7_1,
+        MSEL1CR_6_0,    MSEL1CR_6_1,
+        MSEL1CR_4_0,    MSEL1CR_4_1,
+        MSEL1CR_3_0,    MSEL1CR_3_1,
+        MSEL1CR_2_0,    MSEL1CR_2_1,
+        MSEL1CR_0_0,    MSEL1CR_0_1,
+
+        MSEL3CR_27_0,   MSEL3CR_27_1,
+        MSEL3CR_26_0,   MSEL3CR_26_1,
+        MSEL3CR_21_0,   MSEL3CR_21_1,
+        MSEL3CR_20_0,   MSEL3CR_20_1,
+        MSEL3CR_15_0,   MSEL3CR_15_1,
+        MSEL3CR_9_0,    MSEL3CR_9_1,
+        MSEL3CR_6_0,    MSEL3CR_6_1,
+
+        MSEL4CR_19_0,   MSEL4CR_19_1,
+        MSEL4CR_18_0,   MSEL4CR_18_1,
+        MSEL4CR_17_0,   MSEL4CR_17_1,
+        MSEL4CR_16_0,   MSEL4CR_16_1,
+        MSEL4CR_15_0,   MSEL4CR_15_1,
+        MSEL4CR_14_0,   MSEL4CR_14_1,
+        MSEL4CR_10_0,   MSEL4CR_10_1,
+        MSEL4CR_6_0,    MSEL4CR_6_1,
+        MSEL4CR_4_0,    MSEL4CR_4_1,
+        MSEL4CR_1_0,    MSEL4CR_1_1,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        /* IRQ */
+        IRQ0_6_MARK,    IRQ0_162_MARK,  IRQ1_MARK,      IRQ2_4_MARK,
+        IRQ2_5_MARK,    IRQ3_8_MARK,    IRQ3_16_MARK,   IRQ4_17_MARK,
+        IRQ4_163_MARK,  IRQ5_MARK,      IRQ6_39_MARK,   IRQ6_164_MARK,
+        IRQ7_40_MARK,   IRQ7_167_MARK,  IRQ8_41_MARK,   IRQ8_168_MARK,
+        IRQ9_42_MARK,   IRQ9_169_MARK,  IRQ10_MARK,     IRQ11_MARK,
+        IRQ12_80_MARK,  IRQ12_137_MARK, IRQ13_81_MARK,  IRQ13_145_MARK,
+        IRQ14_82_MARK,  IRQ14_146_MARK, IRQ15_83_MARK,  IRQ15_147_MARK,
+        IRQ16_84_MARK,  IRQ16_170_MARK, IRQ17_MARK,     IRQ18_MARK,
+        IRQ19_MARK,     IRQ20_MARK,     IRQ21_MARK,     IRQ22_MARK,
+        IRQ23_MARK,     IRQ24_MARK,     IRQ25_MARK,     IRQ26_121_MARK,
+        IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
+        IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
+        IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
+
+        /* MSIOF0 */
+        MSIOF0_TSYNC_MARK,      MSIOF0_TSCK_MARK,       MSIOF0_RXD_MARK,
+        MSIOF0_RSCK_MARK,       MSIOF0_RSYNC_MARK,      MSIOF0_MCK0_MARK,
+        MSIOF0_MCK1_MARK,       MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,
+        MSIOF0_TXD_MARK,
+
+        /* MSIOF1 */
+        MSIOF1_TSCK_39_MARK,    MSIOF1_TSYNC_40_MARK,
+        MSIOF1_TSCK_88_MARK,    MSIOF1_TSYNC_89_MARK,
+        MSIOF1_TXD_41_MARK,     MSIOF1_RXD_42_MARK,
+        MSIOF1_TXD_90_MARK,     MSIOF1_RXD_91_MARK,
+        MSIOF1_SS1_43_MARK,     MSIOF1_SS2_44_MARK,
+        MSIOF1_SS1_92_MARK,     MSIOF1_SS2_93_MARK,
+        MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
+        MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
+
+        /* MSIOF2 */
+        MSIOF2_RSCK_MARK,       MSIOF2_RSYNC_MARK,      MSIOF2_MCK0_MARK,
+        MSIOF2_MCK1_MARK,       MSIOF2_SS1_MARK,        MSIOF2_SS2_MARK,
+        MSIOF2_TSYNC_MARK,      MSIOF2_TSCK_MARK,       MSIOF2_RXD_MARK,
+        MSIOF2_TXD_MARK,
+
+        /* BBIF1 */
+        BBIF1_RXD_MARK,         BBIF1_TSYNC_MARK,       BBIF1_TSCK_MARK,
+        BBIF1_TXD_MARK,         BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
+        BBIF1_FLOW_MARK,        BB_RX_FLOW_N_MARK,
+
+        /* BBIF2 */
+        BBIF2_TSCK1_MARK,       BBIF2_TSYNC1_MARK,
+        BBIF2_TXD1_MARK,        BBIF2_RXD_MARK,
+
+        /* FSI */
+        FSIACK_MARK,    FSIBCK_MARK,            FSIAILR_MARK,   FSIAIBT_MARK,
+        FSIAISLD_MARK,  FSIAOMC_MARK,           FSIAOLR_MARK,   FSIAOBT_MARK,
+        FSIAOSLD_MARK,  FSIASPDIF_11_MARK,      FSIASPDIF_15_MARK,
+
+        /* FMSI */
+        FMSOCK_MARK,    FMSOOLR_MARK,   FMSIOLR_MARK,   FMSOOBT_MARK,
+        FMSIOBT_MARK,   FMSOSLD_MARK,   FMSOILR_MARK,   FMSIILR_MARK,
+        FMSOIBT_MARK,   FMSIIBT_MARK,   FMSISLD_MARK,   FMSICK_MARK,
+
+        /* SCIFA0 */
+        SCIFA0_TXD_MARK,        SCIFA0_RXD_MARK,        SCIFA0_SCK_MARK,
+        SCIFA0_RTS_MARK,        SCIFA0_CTS_MARK,
+
+        /* SCIFA1 */
+        SCIFA1_TXD_MARK,        SCIFA1_RXD_MARK,        SCIFA1_SCK_MARK,
+        SCIFA1_RTS_MARK,        SCIFA1_CTS_MARK,
+
+        /* SCIFA2 */
+        SCIFA2_CTS1_MARK,       SCIFA2_RTS1_MARK,       SCIFA2_TXD1_MARK,
+        SCIFA2_RXD1_MARK,       SCIFA2_SCK1_MARK,
+
+        /* SCIFA3 */
+        SCIFA3_CTS_43_MARK,     SCIFA3_CTS_140_MARK,    SCIFA3_RTS_44_MARK,
+        SCIFA3_RTS_141_MARK,    SCIFA3_SCK_MARK,        SCIFA3_TXD_MARK,
+        SCIFA3_RXD_MARK,
+
+        /* SCIFA4 */
+        SCIFA4_RXD_MARK,        SCIFA4_TXD_MARK,
+
+        /* SCIFA5 */
+        SCIFA5_RXD_MARK,        SCIFA5_TXD_MARK,
+
+        /* SCIFB */
+        SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
+        SCIFB_TXD_MARK, SCIFB_RXD_MARK,
+
+        /* CEU */
+        VIO_HD_MARK,    VIO_CKO1_MARK,  VIO_CKO2_MARK,  VIO_VD_MARK,
+        VIO_CLK_MARK,   VIO_FIELD_MARK, VIO_CKO_MARK,
+        VIO_D0_MARK,    VIO_D1_MARK,    VIO_D2_MARK,    VIO_D3_MARK,
+        VIO_D4_MARK,    VIO_D5_MARK,    VIO_D6_MARK,    VIO_D7_MARK,
+        VIO_D8_MARK,    VIO_D9_MARK,    VIO_D10_MARK,   VIO_D11_MARK,
+        VIO_D12_MARK,   VIO_D13_MARK,   VIO_D14_MARK,   VIO_D15_MARK,
+
+        /* USB0 */
+        IDIN_0_MARK,    EXTLP_0_MARK,   OVCN2_0_MARK,   PWEN_0_MARK,
+        OVCN_0_MARK,    VBUS0_0_MARK,
+
+        /* USB1 */
+        IDIN_1_18_MARK,         IDIN_1_113_MARK,
+        PWEN_1_115_MARK,        PWEN_1_138_MARK,
+        OVCN_1_114_MARK,        OVCN_1_162_MARK,
+        EXTLP_1_MARK,           OVCN2_1_MARK,
+        VBUS0_1_MARK,
+
+        /* GPIO */
+        GPI0_MARK,      GPI1_MARK,      GPO0_MARK,      GPO1_MARK,
+
+        /* BSC */
+        BS_MARK,        WE1_MARK,
+        CKO_MARK,       WAIT_MARK,      RDWR_MARK,
+
+        A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
+        A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
+        A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
+        A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
+        A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
+        A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
+        A26_MARK,
+
+        CS0_MARK,       CS2_MARK,       CS4_MARK,
+        CS5A_MARK,      CS5B_MARK,      CS6A_MARK,
+
+        /* BSC/FLCTL */
+        RD_FSC_MARK,    WE0_FWE_MARK,   A4_FOE_MARK,    A5_FCDE_MARK,
+        D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   D3_NAF3_MARK,
+        D4_NAF4_MARK,   D5_NAF5_MARK,   D6_NAF6_MARK,   D7_NAF7_MARK,
+        D8_NAF8_MARK,   D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+
+        /* MMCIF(1) */
+        MMCD0_0_MARK,   MMCD0_1_MARK,   MMCD0_2_MARK,   MMCD0_3_MARK,
+        MMCD0_4_MARK,   MMCD0_5_MARK,   MMCD0_6_MARK,   MMCD0_7_MARK,
+        MMCCMD0_MARK,   MMCCLK0_MARK,
+
+        /* MMCIF(2) */
+        MMCD1_0_MARK,   MMCD1_1_MARK,   MMCD1_2_MARK,   MMCD1_3_MARK,
+        MMCD1_4_MARK,   MMCD1_5_MARK,   MMCD1_6_MARK,   MMCD1_7_MARK,
+        MMCCLK1_MARK,   MMCCMD1_MARK,
+
+        /* SPU2 */
+        VINT_I_MARK,
+
+        /* FLCTL */
+        FCE1_MARK,      FCE0_MARK,      FRB_MARK,
+
+        /* HSI */
+        GP_RX_FLAG_MARK,        GP_RX_DATA_MARK,        GP_TX_READY_MARK,
+        GP_RX_WAKE_MARK,        MP_TX_FLAG_MARK,        MP_TX_DATA_MARK,
+        MP_RX_READY_MARK,       MP_TX_WAKE_MARK,
+
+        /* MFI */
+        MFIv6_MARK,
+        MFIv4_MARK,
+
+        MEMC_CS0_MARK,                  MEMC_BUSCLK_MEMC_A0_MARK,
+        MEMC_CS1_MEMC_A1_MARK,          MEMC_ADV_MEMC_DREQ0_MARK,
+        MEMC_WAIT_MEMC_DREQ1_MARK,      MEMC_NOE_MARK,
+        MEMC_NWE_MARK,                  MEMC_INT_MARK,
+
+        MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,
+        MEMC_AD3_MARK,  MEMC_AD4_MARK,  MEMC_AD5_MARK,
+        MEMC_AD6_MARK,  MEMC_AD7_MARK,  MEMC_AD8_MARK,
+        MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
+        MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
+        MEMC_AD15_MARK,
+
+        /* SIM */
+        SIM_RST_MARK,   SIM_CLK_MARK,   SIM_D_MARK,
+
+        /* TPU */
+        TPU0TO0_MARK,           TPU0TO1_MARK,
+        TPU0TO2_93_MARK,        TPU0TO2_99_MARK,
+        TPU0TO3_MARK,
+
+        /* I2C2 */
+        I2C_SCL2_MARK,  I2C_SDA2_MARK,
+
+        /* I2C3(1) */
+        I2C_SCL3_MARK,  I2C_SDA3_MARK,
+
+        /* I2C3(2) */
+        I2C_SCL3S_MARK, I2C_SDA3S_MARK,
+
+        /* I2C4(2) */
+        I2C_SCL4_MARK,  I2C_SDA4_MARK,
+
+        /* I2C4(2) */
+        I2C_SCL4S_MARK, I2C_SDA4S_MARK,
+
+        /* KEYSC */
+        KEYOUT0_MARK,   KEYIN0_121_MARK,        KEYIN0_136_MARK,
+        KEYOUT1_MARK,   KEYIN1_122_MARK,        KEYIN1_135_MARK,
+        KEYOUT2_MARK,   KEYIN2_123_MARK,        KEYIN2_134_MARK,
+        KEYOUT3_MARK,   KEYIN3_124_MARK,        KEYIN3_133_MARK,
+        KEYOUT4_MARK,   KEYIN4_MARK,
+        KEYOUT5_MARK,   KEYIN5_MARK,
+        KEYOUT6_MARK,   KEYIN6_MARK,
+        KEYOUT7_MARK,   KEYIN7_MARK,
+
+        /* LCDC */
+        LCDC0_SELECT_MARK,
+        LCDC1_SELECT_MARK,
+        LCDHSYN_MARK,   LCDCS_MARK,     LCDVSYN_MARK,   LCDDCK_MARK,
+        LCDWR_MARK,     LCDRD_MARK,     LCDDISP_MARK,   LCDRS_MARK,
+        LCDLCLK_MARK,   LCDDON_MARK,
+
+        LCDD0_MARK,     LCDD1_MARK,     LCDD2_MARK,     LCDD3_MARK,
+        LCDD4_MARK,     LCDD5_MARK,     LCDD6_MARK,     LCDD7_MARK,
+        LCDD8_MARK,     LCDD9_MARK,     LCDD10_MARK,    LCDD11_MARK,
+        LCDD12_MARK,    LCDD13_MARK,    LCDD14_MARK,    LCDD15_MARK,
+        LCDD16_MARK,    LCDD17_MARK,    LCDD18_MARK,    LCDD19_MARK,
+        LCDD20_MARK,    LCDD21_MARK,    LCDD22_MARK,    LCDD23_MARK,
+
+        /* IRDA */
+        IRDA_OUT_MARK,  IRDA_IN_MARK,   IRDA_FIRSEL_MARK,
+        IROUT_139_MARK, IROUT_140_MARK,
+
+        /* TSIF1 */
+        TS0_1SELECT_MARK,
+        TS0_2SELECT_MARK,
+        TS1_1SELECT_MARK,
+        TS1_2SELECT_MARK,
+
+        TS_SPSYNC1_MARK,        TS_SDAT1_MARK,
+        TS_SDEN1_MARK,          TS_SCK1_MARK,
+
+        /* TSIF2 */
+        TS_SPSYNC2_MARK,        TS_SDAT2_MARK,
+        TS_SDEN2_MARK,          TS_SCK2_MARK,
+
+        /* HDMI */
+        HDMI_HPD_MARK,  HDMI_CEC_MARK,
+
+        /* SDHI0 */
+        SDHICLK0_MARK,  SDHICD0_MARK,
+        SDHICMD0_MARK,  SDHIWP0_MARK,
+        SDHID0_0_MARK,  SDHID0_1_MARK,
+        SDHID0_2_MARK,  SDHID0_3_MARK,
+
+        /* SDHI1 */
+        SDHICLK1_MARK,  SDHICMD1_MARK,  SDHID1_0_MARK,
+        SDHID1_1_MARK,  SDHID1_2_MARK,  SDHID1_3_MARK,
+
+        /* SDHI2 */
+        SDHICLK2_MARK,  SDHICMD2_MARK,  SDHID2_0_MARK,
+        SDHID2_1_MARK,  SDHID2_2_MARK,  SDHID2_3_MARK,
+
+        /* SDENC */
+        SDENC_CPG_MARK,
+        SDENC_DV_CLKI_MARK,
+
+        PINMUX_MARK_END,
+};
+
+/* PORT_DATA_I_PD(nr) */
+#define _I___D(nr)                           \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+/* PORT_DATA_I_PU(nr) */
+#define _I__U_(nr)                           \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
+                    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+/* PORT_DATA_I_PU_PD(nr) */
+#define _I__UD(nr)                           \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+/* PORT_DATA_O(nr) */
+#define __O___(nr)                                                      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
+
+/* PORT_DATA_IO(nr) */
+#define _IO___(nr)                                   \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN)
+
+/* PORT_DATA_IO_PD(nr) */
+#define _IO__D(nr)                                           \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+/* PORT_DATA_IO_PU(nr) */
+#define _IO_U_(nr)                                           \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+/* PORT_DATA_IO_PU_PD(nr) */
+#define _IO_UD(nr)                                           \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
+                    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+
+static pinmux_enum_t pinmux_data[] = {
+
+        /* specify valid pin states for each pin in GPIO mode */
+
+        _IO__D(0), _IO__D(1), __O___(2), _I___D(3), _I___D(4),
+        _I___D(5), _IO_UD(6), _I___D(7), _IO__D(8), __O___(9),
+
+        __O___(10), __O___(11), _IO_UD(12), _IO__D(13), _IO__D(14),
+        __O___(15), _IO__D(16), _IO__D(17), _I___D(18), _IO___(19),
+
+        _IO___(20), _IO___(21), _IO___(22), _IO___(23), _IO___(24),
+        _IO___(25), _IO___(26), _IO___(27), _IO___(28), _IO___(29),
+
+        _IO___(30), _IO___(31), _IO___(32), _IO___(33), _IO___(34),
+        _IO___(35), _IO___(36), _IO___(37), _IO___(38), _IO___(39),
+
+        _IO___(40), _IO___(41), _IO___(42), _IO___(43), _IO___(44),
+        _IO___(45), _IO_U_(46), _IO_U_(47), _IO_U_(48), _IO_U_(49),
+
+        _IO_U_(50), _IO_U_(51), _IO_U_(52), _IO_U_(53), _IO_U_(54),
+        _IO_U_(55), _IO_U_(56), _IO_U_(57), _IO_U_(58), _IO_U_(59),
+
+        _IO_U_(60), _IO_U_(61), _IO___(62), __O___(63), __O___(64),
+        _IO_U_(65), __O___(66), _IO_U_(67), __O___(68), _IO___(69), /*66?*/
+
+        _IO___(70), _IO___(71), __O___(72), _I__U_(73), _I__UD(74),
+        _IO_UD(75), _IO_UD(76), _IO_UD(77), _IO_UD(78), _IO_UD(79),
+
+        _IO_UD(80), _IO_UD(81), _IO_UD(82), _IO_UD(83), _IO_UD(84),
+        _IO_UD(85), _IO_UD(86), _IO_UD(87), _IO_UD(88), _IO_UD(89),
+
+        _IO_UD(90), _IO_UD(91), _IO_UD(92), _IO_UD(93), _IO_UD(94),
+        _IO_UD(95), _IO_U_(96), _IO_UD(97), _IO_UD(98), __O___(99), /*99?*/
+
+        _IO__D(100), _IO__D(101), _IO__D(102), _IO__D(103), _IO__D(104),
+        _IO__D(105), _IO_U_(106), _IO_U_(107), _IO_U_(108), _IO_U_(109),
+
+        _IO_U_(110), _IO_U_(111), _IO__D(112), _IO__D(113), _IO_U_(114),
+        _IO_U_(115), _IO_U_(116), _IO_U_(117), _IO_U_(118), _IO_U_(119),
+
+        _IO_U_(120), _IO__D(121), _IO__D(122), _IO__D(123), _IO__D(124),
+        _IO__D(125), _IO__D(126), _IO__D(127), _IO__D(128), _IO_UD(129),
+
+        _IO_UD(130), _IO_UD(131), _IO_UD(132), _IO_UD(133), _IO_UD(134),
+        _IO_UD(135), _IO__D(136), _IO__D(137), _IO__D(138), _IO__D(139),
+
+        _IO__D(140), _IO__D(141), _IO__D(142), _IO_UD(143), _IO__D(144),
+        _IO__D(145), _IO__D(146), _IO__D(147), _IO__D(148), _IO__D(149),
+
+        _IO__D(150), _IO__D(151), _IO_UD(152), _I___D(153), _IO_UD(154),
+        _I___D(155), _IO__D(156), _IO__D(157), _I___D(158), _IO__D(159),
+
+        __O___(160), _IO__D(161), _IO__D(162), _IO__D(163), _I___D(164),
+        _IO__D(165), _I___D(166), _I___D(167), _I___D(168), _I___D(169),
+
+        _I___D(170), __O___(171), _IO_UD(172), _IO_UD(173), _IO_UD(174),
+        _IO_UD(175), _IO_UD(176), _IO_UD(177), _IO_UD(178), __O___(179),
+
+        _IO_UD(180), _IO_UD(181), _IO_UD(182), _IO_UD(183), _IO_UD(184),
+        __O___(185), _IO_UD(186), _IO_UD(187), _IO_UD(188), _IO_UD(189),
+
+        _IO_UD(190),
+
+        /* IRQ */
+        PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
+        PINMUX_DATA(IRQ0_162_MARK,      PORT162_FN0,    MSEL1CR_0_1),
+        PINMUX_DATA(IRQ1_MARK,          PORT12_FN0),
+        PINMUX_DATA(IRQ2_4_MARK,        PORT4_FN0,      MSEL1CR_2_0),
+        PINMUX_DATA(IRQ2_5_MARK,        PORT5_FN0,      MSEL1CR_2_1),
+        PINMUX_DATA(IRQ3_8_MARK,        PORT8_FN0,      MSEL1CR_3_0),
+        PINMUX_DATA(IRQ3_16_MARK,       PORT16_FN0,     MSEL1CR_3_1),
+        PINMUX_DATA(IRQ4_17_MARK,       PORT17_FN0,     MSEL1CR_4_0),
+        PINMUX_DATA(IRQ4_163_MARK,      PORT163_FN0,    MSEL1CR_4_1),
+        PINMUX_DATA(IRQ5_MARK,          PORT18_FN0),
+        PINMUX_DATA(IRQ6_39_MARK,       PORT39_FN0,     MSEL1CR_6_0),
+        PINMUX_DATA(IRQ6_164_MARK,      PORT164_FN0,    MSEL1CR_6_1),
+        PINMUX_DATA(IRQ7_40_MARK,       PORT40_FN0,     MSEL1CR_7_1),
+        PINMUX_DATA(IRQ7_167_MARK,      PORT167_FN0,    MSEL1CR_7_0),
+        PINMUX_DATA(IRQ8_41_MARK,       PORT41_FN0,     MSEL1CR_8_1),
+        PINMUX_DATA(IRQ8_168_MARK,      PORT168_FN0,    MSEL1CR_8_0),
+        PINMUX_DATA(IRQ9_42_MARK,       PORT42_FN0,     MSEL1CR_9_0),
+        PINMUX_DATA(IRQ9_169_MARK,      PORT169_FN0,    MSEL1CR_9_1),
+        PINMUX_DATA(IRQ10_MARK,         PORT65_FN0,     MSEL1CR_9_1),
+        PINMUX_DATA(IRQ11_MARK,         PORT67_FN0),
+        PINMUX_DATA(IRQ12_80_MARK,      PORT80_FN0,     MSEL1CR_12_0),
+        PINMUX_DATA(IRQ12_137_MARK,     PORT137_FN0,    MSEL1CR_12_1),
+        PINMUX_DATA(IRQ13_81_MARK,      PORT81_FN0,     MSEL1CR_13_0),
+        PINMUX_DATA(IRQ13_145_MARK,     PORT145_FN0,    MSEL1CR_13_1),
+        PINMUX_DATA(IRQ14_82_MARK,      PORT82_FN0,     MSEL1CR_14_0),
+        PINMUX_DATA(IRQ14_146_MARK,     PORT146_FN0,    MSEL1CR_14_1),
+        PINMUX_DATA(IRQ15_83_MARK,      PORT83_FN0,     MSEL1CR_15_0),
+        PINMUX_DATA(IRQ15_147_MARK,     PORT147_FN0,    MSEL1CR_15_1),
+        PINMUX_DATA(IRQ16_84_MARK,      PORT84_FN0,     MSEL1CR_16_0),
+        PINMUX_DATA(IRQ16_170_MARK,     PORT170_FN0,    MSEL1CR_16_1),
+        PINMUX_DATA(IRQ17_MARK,         PORT85_FN0),
+        PINMUX_DATA(IRQ18_MARK,         PORT86_FN0),
+        PINMUX_DATA(IRQ19_MARK,         PORT87_FN0),
+        PINMUX_DATA(IRQ20_MARK,         PORT92_FN0),
+        PINMUX_DATA(IRQ21_MARK,         PORT93_FN0),
+        PINMUX_DATA(IRQ22_MARK,         PORT94_FN0),
+        PINMUX_DATA(IRQ23_MARK,         PORT95_FN0),
+        PINMUX_DATA(IRQ24_MARK,         PORT112_FN0),
+        PINMUX_DATA(IRQ25_MARK,         PORT119_FN0),
+        PINMUX_DATA(IRQ26_121_MARK,     PORT121_FN0,    MSEL1CR_26_1),
+        PINMUX_DATA(IRQ26_172_MARK,     PORT172_FN0,    MSEL1CR_26_0),
+        PINMUX_DATA(IRQ27_122_MARK,     PORT122_FN0,    MSEL1CR_27_1),
+        PINMUX_DATA(IRQ27_180_MARK,     PORT180_FN0,    MSEL1CR_27_0),
+        PINMUX_DATA(IRQ28_123_MARK,     PORT123_FN0,    MSEL1CR_28_1),
+        PINMUX_DATA(IRQ28_181_MARK,     PORT181_FN0,    MSEL1CR_28_0),
+        PINMUX_DATA(IRQ29_129_MARK,     PORT129_FN0,    MSEL1CR_29_1),
+        PINMUX_DATA(IRQ29_182_MARK,     PORT182_FN0,    MSEL1CR_29_0),
+        PINMUX_DATA(IRQ30_130_MARK,     PORT130_FN0,    MSEL1CR_30_1),
+        PINMUX_DATA(IRQ30_183_MARK,     PORT183_FN0,    MSEL1CR_30_0),
+        PINMUX_DATA(IRQ31_138_MARK,     PORT138_FN0,    MSEL1CR_31_1),
+        PINMUX_DATA(IRQ31_184_MARK,     PORT184_FN0,    MSEL1CR_31_0),
+
+        /* Function 1 */
+        PINMUX_DATA(BBIF2_TSCK1_MARK,           PORT0_FN1),
+        PINMUX_DATA(BBIF2_TSYNC1_MARK,          PORT1_FN1),
+        PINMUX_DATA(BBIF2_TXD1_MARK,            PORT2_FN1),
+        PINMUX_DATA(BBIF2_RXD_MARK,             PORT3_FN1),
+        PINMUX_DATA(FSIACK_MARK,                PORT4_FN1),
+        PINMUX_DATA(FSIAILR_MARK,               PORT5_FN1),
+        PINMUX_DATA(FSIAIBT_MARK,               PORT6_FN1),
+        PINMUX_DATA(FSIAISLD_MARK,              PORT7_FN1),
+        PINMUX_DATA(FSIAOMC_MARK,               PORT8_FN1),
+        PINMUX_DATA(FSIAOLR_MARK,               PORT9_FN1),
+        PINMUX_DATA(FSIAOBT_MARK,               PORT10_FN1),
+        PINMUX_DATA(FSIAOSLD_MARK,              PORT11_FN1),
+        PINMUX_DATA(FMSOCK_MARK,                PORT12_FN1),
+        PINMUX_DATA(FMSOOLR_MARK,               PORT13_FN1),
+        PINMUX_DATA(FMSOOBT_MARK,               PORT14_FN1),
+        PINMUX_DATA(FMSOSLD_MARK,               PORT15_FN1),
+        PINMUX_DATA(FMSOILR_MARK,               PORT16_FN1),
+        PINMUX_DATA(FMSOIBT_MARK,               PORT17_FN1),
+        PINMUX_DATA(FMSISLD_MARK,               PORT18_FN1),
+        PINMUX_DATA(A0_MARK,                    PORT19_FN1),
+        PINMUX_DATA(A1_MARK,                    PORT20_FN1),
+        PINMUX_DATA(A2_MARK,                    PORT21_FN1),
+        PINMUX_DATA(A3_MARK,                    PORT22_FN1),
+        PINMUX_DATA(A4_FOE_MARK,                PORT23_FN1),
+        PINMUX_DATA(A5_FCDE_MARK,               PORT24_FN1),
+        PINMUX_DATA(A6_MARK,                    PORT25_FN1),
+        PINMUX_DATA(A7_MARK,                    PORT26_FN1),
+        PINMUX_DATA(A8_MARK,                    PORT27_FN1),
+        PINMUX_DATA(A9_MARK,                    PORT28_FN1),
+        PINMUX_DATA(A10_MARK,                   PORT29_FN1),
+        PINMUX_DATA(A11_MARK,                   PORT30_FN1),
+        PINMUX_DATA(A12_MARK,                   PORT31_FN1),
+        PINMUX_DATA(A13_MARK,                   PORT32_FN1),
+        PINMUX_DATA(A14_MARK,                   PORT33_FN1),
+        PINMUX_DATA(A15_MARK,                   PORT34_FN1),
+        PINMUX_DATA(A16_MARK,                   PORT35_FN1),
+        PINMUX_DATA(A17_MARK,                   PORT36_FN1),
+        PINMUX_DATA(A18_MARK,                   PORT37_FN1),
+        PINMUX_DATA(A19_MARK,                   PORT38_FN1),
+        PINMUX_DATA(A20_MARK,                   PORT39_FN1),
+        PINMUX_DATA(A21_MARK,                   PORT40_FN1),
+        PINMUX_DATA(A22_MARK,                   PORT41_FN1),
+        PINMUX_DATA(A23_MARK,                   PORT42_FN1),
+        PINMUX_DATA(A24_MARK,                   PORT43_FN1),
+        PINMUX_DATA(A25_MARK,                   PORT44_FN1),
+        PINMUX_DATA(A26_MARK,                   PORT45_FN1),
+        PINMUX_DATA(D0_NAF0_MARK,               PORT46_FN1),
+        PINMUX_DATA(D1_NAF1_MARK,               PORT47_FN1),
+        PINMUX_DATA(D2_NAF2_MARK,               PORT48_FN1),
+        PINMUX_DATA(D3_NAF3_MARK,               PORT49_FN1),
+        PINMUX_DATA(D4_NAF4_MARK,               PORT50_FN1),
+        PINMUX_DATA(D5_NAF5_MARK,               PORT51_FN1),
+        PINMUX_DATA(D6_NAF6_MARK,               PORT52_FN1),
+        PINMUX_DATA(D7_NAF7_MARK,               PORT53_FN1),
+        PINMUX_DATA(D8_NAF8_MARK,               PORT54_FN1),
+        PINMUX_DATA(D9_NAF9_MARK,               PORT55_FN1),
+        PINMUX_DATA(D10_NAF10_MARK,             PORT56_FN1),
+        PINMUX_DATA(D11_NAF11_MARK,             PORT57_FN1),
+        PINMUX_DATA(D12_NAF12_MARK,             PORT58_FN1),
+        PINMUX_DATA(D13_NAF13_MARK,             PORT59_FN1),
+        PINMUX_DATA(D14_NAF14_MARK,             PORT60_FN1),
+        PINMUX_DATA(D15_NAF15_MARK,             PORT61_FN1),
+        PINMUX_DATA(CS0_MARK,                   PORT62_FN1),
+        PINMUX_DATA(CS2_MARK,                   PORT63_FN1),
+        PINMUX_DATA(CS4_MARK,                   PORT64_FN1),
+        PINMUX_DATA(CS5A_MARK,                  PORT65_FN1),
+        PINMUX_DATA(CS5B_MARK,                  PORT66_FN1),
+        PINMUX_DATA(CS6A_MARK,                  PORT67_FN1),
+        PINMUX_DATA(FCE0_MARK,                  PORT68_FN1),
+        PINMUX_DATA(RD_FSC_MARK,                PORT69_FN1),
+        PINMUX_DATA(WE0_FWE_MARK,               PORT70_FN1),
+        PINMUX_DATA(WE1_MARK,                   PORT71_FN1),
+        PINMUX_DATA(CKO_MARK,                   PORT72_FN1),
+        PINMUX_DATA(FRB_MARK,                   PORT73_FN1),
+        PINMUX_DATA(WAIT_MARK,                  PORT74_FN1),
+        PINMUX_DATA(RDWR_MARK,                  PORT75_FN1),
+        PINMUX_DATA(MEMC_AD0_MARK,              PORT76_FN1),
+        PINMUX_DATA(MEMC_AD1_MARK,              PORT77_FN1),
+        PINMUX_DATA(MEMC_AD2_MARK,              PORT78_FN1),
+        PINMUX_DATA(MEMC_AD3_MARK,              PORT79_FN1),
+        PINMUX_DATA(MEMC_AD4_MARK,              PORT80_FN1),
+        PINMUX_DATA(MEMC_AD5_MARK,              PORT81_FN1),
+        PINMUX_DATA(MEMC_AD6_MARK,              PORT82_FN1),
+        PINMUX_DATA(MEMC_AD7_MARK,              PORT83_FN1),
+        PINMUX_DATA(MEMC_AD8_MARK,              PORT84_FN1),
+        PINMUX_DATA(MEMC_AD9_MARK,              PORT85_FN1),
+        PINMUX_DATA(MEMC_AD10_MARK,             PORT86_FN1),
+        PINMUX_DATA(MEMC_AD11_MARK,             PORT87_FN1),
+        PINMUX_DATA(MEMC_AD12_MARK,             PORT88_FN1),
+        PINMUX_DATA(MEMC_AD13_MARK,             PORT89_FN1),
+        PINMUX_DATA(MEMC_AD14_MARK,             PORT90_FN1),
+        PINMUX_DATA(MEMC_AD15_MARK,             PORT91_FN1),
+        PINMUX_DATA(MEMC_CS0_MARK,              PORT92_FN1),
+        PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK,   PORT93_FN1),
+        PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK,      PORT94_FN1),
+        PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK,   PORT95_FN1),
+        PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK,  PORT96_FN1),
+        PINMUX_DATA(MEMC_NOE_MARK,              PORT97_FN1),
+        PINMUX_DATA(MEMC_NWE_MARK,              PORT98_FN1),
+        PINMUX_DATA(MEMC_INT_MARK,              PORT99_FN1),
+        PINMUX_DATA(VIO_VD_MARK,                PORT100_FN1),
+        PINMUX_DATA(VIO_HD_MARK,                PORT101_FN1),
+        PINMUX_DATA(VIO_D0_MARK,                PORT102_FN1),
+        PINMUX_DATA(VIO_D1_MARK,                PORT103_FN1),
+        PINMUX_DATA(VIO_D2_MARK,                PORT104_FN1),
+        PINMUX_DATA(VIO_D3_MARK,                PORT105_FN1),
+        PINMUX_DATA(VIO_D4_MARK,                PORT106_FN1),
+        PINMUX_DATA(VIO_D5_MARK,                PORT107_FN1),
+        PINMUX_DATA(VIO_D6_MARK,                PORT108_FN1),
+        PINMUX_DATA(VIO_D7_MARK,                PORT109_FN1),
+        PINMUX_DATA(VIO_D8_MARK,                PORT110_FN1),
+        PINMUX_DATA(VIO_D9_MARK,                PORT111_FN1),
+        PINMUX_DATA(VIO_D10_MARK,               PORT112_FN1),
+        PINMUX_DATA(VIO_D11_MARK,               PORT113_FN1),
+        PINMUX_DATA(VIO_D12_MARK,               PORT114_FN1),
+        PINMUX_DATA(VIO_D13_MARK,               PORT115_FN1),
+        PINMUX_DATA(VIO_D14_MARK,               PORT116_FN1),
+        PINMUX_DATA(VIO_D15_MARK,               PORT117_FN1),
+        PINMUX_DATA(VIO_CLK_MARK,               PORT118_FN1),
+        PINMUX_DATA(VIO_FIELD_MARK,             PORT119_FN1),
+        PINMUX_DATA(VIO_CKO_MARK,               PORT120_FN1),
+        PINMUX_DATA(LCDD0_MARK,                 PORT121_FN1),
+        PINMUX_DATA(LCDD1_MARK,                 PORT122_FN1),
+        PINMUX_DATA(LCDD2_MARK,                 PORT123_FN1),
+        PINMUX_DATA(LCDD3_MARK,                 PORT124_FN1),
+        PINMUX_DATA(LCDD4_MARK,                 PORT125_FN1),
+        PINMUX_DATA(LCDD5_MARK,                 PORT126_FN1),
+        PINMUX_DATA(LCDD6_MARK,                 PORT127_FN1),
+        PINMUX_DATA(LCDD7_MARK,                 PORT128_FN1),
+        PINMUX_DATA(LCDD8_MARK,                 PORT129_FN1),
+        PINMUX_DATA(LCDD9_MARK,                 PORT130_FN1),
+        PINMUX_DATA(LCDD10_MARK,                PORT131_FN1),
+        PINMUX_DATA(LCDD11_MARK,                PORT132_FN1),
+        PINMUX_DATA(LCDD12_MARK,                PORT133_FN1),
+        PINMUX_DATA(LCDD13_MARK,                PORT134_FN1),
+        PINMUX_DATA(LCDD14_MARK,                PORT135_FN1),
+        PINMUX_DATA(LCDD15_MARK,                PORT136_FN1),
+        PINMUX_DATA(LCDD16_MARK,                PORT137_FN1),
+        PINMUX_DATA(LCDD17_MARK,                PORT138_FN1),
+        PINMUX_DATA(LCDD18_MARK,                PORT139_FN1),
+        PINMUX_DATA(LCDD19_MARK,                PORT140_FN1),
+        PINMUX_DATA(LCDD20_MARK,                PORT141_FN1),
+        PINMUX_DATA(LCDD21_MARK,                PORT142_FN1),
+        PINMUX_DATA(LCDD22_MARK,                PORT143_FN1),
+        PINMUX_DATA(LCDD23_MARK,                PORT144_FN1),
+        PINMUX_DATA(LCDHSYN_MARK,               PORT145_FN1),
+        PINMUX_DATA(LCDVSYN_MARK,               PORT146_FN1),
+        PINMUX_DATA(LCDDCK_MARK,                PORT147_FN1),
+        PINMUX_DATA(LCDRD_MARK,                 PORT148_FN1),
+        PINMUX_DATA(LCDDISP_MARK,               PORT149_FN1),
+        PINMUX_DATA(LCDLCLK_MARK,               PORT150_FN1),
+        PINMUX_DATA(LCDDON_MARK,                PORT151_FN1),
+        PINMUX_DATA(SCIFA0_TXD_MARK,            PORT152_FN1),
+        PINMUX_DATA(SCIFA0_RXD_MARK,            PORT153_FN1),
+        PINMUX_DATA(SCIFA1_TXD_MARK,            PORT154_FN1),
+        PINMUX_DATA(SCIFA1_RXD_MARK,            PORT155_FN1),
+        PINMUX_DATA(TS_SPSYNC1_MARK,            PORT156_FN1),
+        PINMUX_DATA(TS_SDAT1_MARK,              PORT157_FN1),
+        PINMUX_DATA(TS_SDEN1_MARK,              PORT158_FN1),
+        PINMUX_DATA(TS_SCK1_MARK,               PORT159_FN1),
+        PINMUX_DATA(TPU0TO0_MARK,               PORT160_FN1),
+        PINMUX_DATA(TPU0TO1_MARK,               PORT161_FN1),
+        PINMUX_DATA(SCIFB_SCK_MARK,             PORT162_FN1),
+        PINMUX_DATA(SCIFB_RTS_MARK,             PORT163_FN1),
+        PINMUX_DATA(SCIFB_CTS_MARK,             PORT164_FN1),
+        PINMUX_DATA(SCIFB_TXD_MARK,             PORT165_FN1),
+        PINMUX_DATA(SCIFB_RXD_MARK,             PORT166_FN1),
+        PINMUX_DATA(VBUS0_0_MARK,               PORT167_FN1),
+        PINMUX_DATA(VBUS0_1_MARK,               PORT168_FN1),
+        PINMUX_DATA(HDMI_HPD_MARK,              PORT169_FN1),
+        PINMUX_DATA(HDMI_CEC_MARK,              PORT170_FN1),
+        PINMUX_DATA(SDHICLK0_MARK,              PORT171_FN1),
+        PINMUX_DATA(SDHICD0_MARK,               PORT172_FN1),
+        PINMUX_DATA(SDHID0_0_MARK,              PORT173_FN1),
+        PINMUX_DATA(SDHID0_1_MARK,              PORT174_FN1),
+        PINMUX_DATA(SDHID0_2_MARK,              PORT175_FN1),
+        PINMUX_DATA(SDHID0_3_MARK,              PORT176_FN1),
+        PINMUX_DATA(SDHICMD0_MARK,              PORT177_FN1),
+        PINMUX_DATA(SDHIWP0_MARK,               PORT178_FN1),
+        PINMUX_DATA(SDHICLK1_MARK,              PORT179_FN1),
+        PINMUX_DATA(SDHID1_0_MARK,              PORT180_FN1),
+        PINMUX_DATA(SDHID1_1_MARK,              PORT181_FN1),
+        PINMUX_DATA(SDHID1_2_MARK,              PORT182_FN1),
+        PINMUX_DATA(SDHID1_3_MARK,              PORT183_FN1),
+        PINMUX_DATA(SDHICMD1_MARK,              PORT184_FN1),
+        PINMUX_DATA(SDHICLK2_MARK,              PORT185_FN1),
+        PINMUX_DATA(SDHID2_0_MARK,              PORT186_FN1),
+        PINMUX_DATA(SDHID2_1_MARK,              PORT187_FN1),
+        PINMUX_DATA(SDHID2_2_MARK,              PORT188_FN1),
+        PINMUX_DATA(SDHID2_3_MARK,              PORT189_FN1),
+        PINMUX_DATA(SDHICMD2_MARK,              PORT190_FN1),
+
+        /* Function 2 */
+        PINMUX_DATA(FSIBCK_MARK,                PORT4_FN2),
+        PINMUX_DATA(SCIFA4_RXD_MARK,            PORT5_FN2),
+        PINMUX_DATA(SCIFA4_TXD_MARK,            PORT6_FN2),
+        PINMUX_DATA(SCIFA5_RXD_MARK,            PORT8_FN2),
+        PINMUX_DATA(FSIASPDIF_11_MARK,          PORT11_FN2),
+        PINMUX_DATA(SCIFA5_TXD_MARK,            PORT12_FN2),
+        PINMUX_DATA(FMSIOLR_MARK,               PORT13_FN2),
+        PINMUX_DATA(FMSIOBT_MARK,               PORT14_FN2),
+        PINMUX_DATA(FSIASPDIF_15_MARK,          PORT15_FN2),
+        PINMUX_DATA(FMSIILR_MARK,               PORT16_FN2),
+        PINMUX_DATA(FMSIIBT_MARK,               PORT17_FN2),
+        PINMUX_DATA(BS_MARK,                    PORT19_FN2),
+        PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT36_FN2),
+        PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT37_FN2),
+        PINMUX_DATA(MSIOF0_RXD_MARK,            PORT38_FN2),
+        PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT39_FN2),
+        PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT40_FN2),
+        PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT41_FN2),
+        PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT42_FN2),
+        PINMUX_DATA(MSIOF0_SS1_MARK,            PORT43_FN2),
+        PINMUX_DATA(MSIOF0_SS2_MARK,            PORT44_FN2),
+        PINMUX_DATA(MSIOF0_TXD_MARK,            PORT45_FN2),
+        PINMUX_DATA(FMSICK_MARK,                PORT65_FN2),
+        PINMUX_DATA(FCE1_MARK,                  PORT66_FN2),
+        PINMUX_DATA(BBIF1_RXD_MARK,             PORT76_FN2),
+        PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT77_FN2),
+        PINMUX_DATA(BBIF1_TSCK_MARK,            PORT78_FN2),
+        PINMUX_DATA(BBIF1_TXD_MARK,             PORT79_FN2),
+        PINMUX_DATA(BBIF1_RSCK_MARK,            PORT80_FN2),
+        PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT81_FN2),
+        PINMUX_DATA(BBIF1_FLOW_MARK,            PORT82_FN2),
+        PINMUX_DATA(BB_RX_FLOW_N_MARK,          PORT83_FN2),
+        PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT84_FN2),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT85_FN2),
+        PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT86_FN2),
+        PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT87_FN2),
+        PINMUX_DATA(MSIOF1_TSCK_88_MARK,        PORT88_FN2, MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_TSYNC_89_MARK,       PORT89_FN2, MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_TXD_90_MARK,         PORT90_FN2, MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_RXD_91_MARK,         PORT91_FN2, MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_SS1_92_MARK,         PORT92_FN2, MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_SS2_93_MARK,         PORT93_FN2, MSEL4CR_10_1),
+        PINMUX_DATA(SCIFA2_CTS1_MARK,           PORT94_FN2),
+        PINMUX_DATA(SCIFA2_RTS1_MARK,           PORT95_FN2),
+        PINMUX_DATA(SCIFA2_TXD1_MARK,           PORT96_FN2),
+        PINMUX_DATA(SCIFA2_RXD1_MARK,           PORT97_FN2),
+        PINMUX_DATA(SCIFA2_SCK1_MARK,           PORT98_FN2),
+        PINMUX_DATA(I2C_SCL2_MARK,              PORT110_FN2),
+        PINMUX_DATA(I2C_SDA2_MARK,              PORT111_FN2),
+        PINMUX_DATA(I2C_SCL3_MARK,              PORT114_FN2, MSEL4CR_16_1),
+        PINMUX_DATA(I2C_SDA3_MARK,              PORT115_FN2, MSEL4CR_16_1),
+        PINMUX_DATA(I2C_SCL4_MARK,              PORT116_FN2, MSEL4CR_17_1),
+        PINMUX_DATA(I2C_SDA4_MARK,              PORT117_FN2, MSEL4CR_17_1),
+        PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT134_FN2),
+        PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT135_FN2),
+        PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT136_FN2),
+        PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT137_FN2),
+        PINMUX_DATA(MSIOF2_SS1_MARK,            PORT138_FN2),
+        PINMUX_DATA(MSIOF2_SS2_MARK,            PORT139_FN2),
+        PINMUX_DATA(SCIFA3_CTS_140_MARK,        PORT140_FN2, MSEL3CR_9_1),
+        PINMUX_DATA(SCIFA3_RTS_141_MARK,        PORT141_FN2),
+        PINMUX_DATA(SCIFA3_SCK_MARK,            PORT142_FN2),
+        PINMUX_DATA(SCIFA3_TXD_MARK,            PORT143_FN2),
+        PINMUX_DATA(SCIFA3_RXD_MARK,            PORT144_FN2),
+        PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT148_FN2),
+        PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT149_FN2),
+        PINMUX_DATA(MSIOF2_RXD_MARK,            PORT150_FN2),
+        PINMUX_DATA(MSIOF2_TXD_MARK,            PORT151_FN2),
+        PINMUX_DATA(SCIFA0_SCK_MARK,            PORT156_FN2),
+        PINMUX_DATA(SCIFA0_RTS_MARK,            PORT157_FN2),
+        PINMUX_DATA(SCIFA0_CTS_MARK,            PORT158_FN2),
+        PINMUX_DATA(SCIFA1_SCK_MARK,            PORT159_FN2),
+        PINMUX_DATA(SCIFA1_RTS_MARK,            PORT160_FN2),
+        PINMUX_DATA(SCIFA1_CTS_MARK,            PORT161_FN2),
+
+        /* Function 3 */
+        PINMUX_DATA(VIO_CKO1_MARK,              PORT16_FN3),
+        PINMUX_DATA(VIO_CKO2_MARK,              PORT17_FN3),
+        PINMUX_DATA(IDIN_1_18_MARK,             PORT18_FN3, MSEL4CR_14_1),
+        PINMUX_DATA(MSIOF1_TSCK_39_MARK,        PORT39_FN3, MSEL4CR_10_0),
+        PINMUX_DATA(MSIOF1_TSYNC_40_MARK,       PORT40_FN3, MSEL4CR_10_0),
+        PINMUX_DATA(MSIOF1_TXD_41_MARK,         PORT41_FN3, MSEL4CR_10_0),
+        PINMUX_DATA(MSIOF1_RXD_42_MARK,         PORT42_FN3, MSEL4CR_10_0),
+        PINMUX_DATA(MSIOF1_SS1_43_MARK,         PORT43_FN3, MSEL4CR_10_0),
+        PINMUX_DATA(MSIOF1_SS2_44_MARK,         PORT44_FN3, MSEL4CR_10_0),
+        PINMUX_DATA(MMCD1_0_MARK,               PORT54_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_1_MARK,               PORT55_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_2_MARK,               PORT56_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_3_MARK,               PORT57_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_4_MARK,               PORT58_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_5_MARK,               PORT59_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_6_MARK,               PORT60_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCD1_7_MARK,               PORT61_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(VINT_I_MARK,                PORT65_FN3),
+        PINMUX_DATA(MMCCLK1_MARK,               PORT66_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(MMCCMD1_MARK,               PORT67_FN3, MSEL4CR_15_1),
+        PINMUX_DATA(TPU0TO2_93_MARK,            PORT93_FN3),
+        PINMUX_DATA(TPU0TO2_99_MARK,            PORT99_FN3),
+        PINMUX_DATA(TPU0TO3_MARK,               PORT112_FN3),
+        PINMUX_DATA(IDIN_0_MARK,                PORT113_FN3),
+        PINMUX_DATA(EXTLP_0_MARK,               PORT114_FN3),
+        PINMUX_DATA(OVCN2_0_MARK,               PORT115_FN3),
+        PINMUX_DATA(PWEN_0_MARK,                PORT116_FN3),
+        PINMUX_DATA(OVCN_0_MARK,                PORT117_FN3),
+        PINMUX_DATA(KEYOUT7_MARK,               PORT121_FN3),
+        PINMUX_DATA(KEYOUT6_MARK,               PORT122_FN3),
+        PINMUX_DATA(KEYOUT5_MARK,               PORT123_FN3),
+        PINMUX_DATA(KEYOUT4_MARK,               PORT124_FN3),
+        PINMUX_DATA(KEYOUT3_MARK,               PORT125_FN3),
+        PINMUX_DATA(KEYOUT2_MARK,               PORT126_FN3),
+        PINMUX_DATA(KEYOUT1_MARK,               PORT127_FN3),
+        PINMUX_DATA(KEYOUT0_MARK,               PORT128_FN3),
+        PINMUX_DATA(KEYIN7_MARK,                PORT129_FN3),
+        PINMUX_DATA(KEYIN6_MARK,                PORT130_FN3),
+        PINMUX_DATA(KEYIN5_MARK,                PORT131_FN3),
+        PINMUX_DATA(KEYIN4_MARK,                PORT132_FN3),
+        PINMUX_DATA(KEYIN3_133_MARK,            PORT133_FN3, MSEL4CR_18_0),
+        PINMUX_DATA(KEYIN2_134_MARK,            PORT134_FN3, MSEL4CR_18_0),
+        PINMUX_DATA(KEYIN1_135_MARK,            PORT135_FN3, MSEL4CR_18_0),
+        PINMUX_DATA(KEYIN0_136_MARK,            PORT136_FN3, MSEL4CR_18_0),
+        PINMUX_DATA(TS_SPSYNC2_MARK,            PORT137_FN3),
+        PINMUX_DATA(IROUT_139_MARK,             PORT139_FN3),
+        PINMUX_DATA(IRDA_OUT_MARK,              PORT140_FN3),
+        PINMUX_DATA(IRDA_IN_MARK,               PORT141_FN3),
+        PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT142_FN3),
+        PINMUX_DATA(TS_SDAT2_MARK,              PORT145_FN3),
+        PINMUX_DATA(TS_SDEN2_MARK,              PORT146_FN3),
+        PINMUX_DATA(TS_SCK2_MARK,               PORT147_FN3),
+
+        /* Function 4 */
+        PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
+        PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
+        PINMUX_DATA(GP_RX_FLAG_MARK,    PORT76_FN4),
+        PINMUX_DATA(GP_RX_DATA_MARK,    PORT77_FN4),
+        PINMUX_DATA(GP_TX_READY_MARK,   PORT78_FN4),
+        PINMUX_DATA(GP_RX_WAKE_MARK,    PORT79_FN4),
+        PINMUX_DATA(MP_TX_FLAG_MARK,    PORT80_FN4),
+        PINMUX_DATA(MP_TX_DATA_MARK,    PORT81_FN4),
+        PINMUX_DATA(MP_RX_READY_MARK,   PORT82_FN4),
+        PINMUX_DATA(MP_TX_WAKE_MARK,    PORT83_FN4),
+        PINMUX_DATA(MMCD0_0_MARK,       PORT84_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_1_MARK,       PORT85_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_2_MARK,       PORT86_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_3_MARK,       PORT87_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_4_MARK,       PORT88_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_5_MARK,       PORT89_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_6_MARK,       PORT90_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCD0_7_MARK,       PORT91_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(MMCCMD0_MARK,       PORT92_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(SIM_RST_MARK,       PORT94_FN4),
+        PINMUX_DATA(SIM_CLK_MARK,       PORT95_FN4),
+        PINMUX_DATA(SIM_D_MARK,         PORT98_FN4),
+        PINMUX_DATA(MMCCLK0_MARK,       PORT99_FN4, MSEL4CR_15_0),
+        PINMUX_DATA(IDIN_1_113_MARK,    PORT113_FN4, MSEL4CR_14_0),
+        PINMUX_DATA(OVCN_1_114_MARK,    PORT114_FN4, MSEL4CR_14_0),
+        PINMUX_DATA(PWEN_1_115_MARK,    PORT115_FN4),
+        PINMUX_DATA(EXTLP_1_MARK,       PORT116_FN4),
+        PINMUX_DATA(OVCN2_1_MARK,       PORT117_FN4),
+        PINMUX_DATA(KEYIN0_121_MARK,    PORT121_FN4, MSEL4CR_18_1),
+        PINMUX_DATA(KEYIN1_122_MARK,    PORT122_FN4, MSEL4CR_18_1),
+        PINMUX_DATA(KEYIN2_123_MARK,    PORT123_FN4, MSEL4CR_18_1),
+        PINMUX_DATA(KEYIN3_124_MARK,    PORT124_FN4, MSEL4CR_18_1),
+        PINMUX_DATA(PWEN_1_138_MARK,    PORT138_FN4),
+        PINMUX_DATA(IROUT_140_MARK,     PORT140_FN4),
+        PINMUX_DATA(LCDCS_MARK,         PORT145_FN4),
+        PINMUX_DATA(LCDWR_MARK,         PORT147_FN4),
+        PINMUX_DATA(LCDRS_MARK,         PORT149_FN4),
+        PINMUX_DATA(OVCN_1_162_MARK,    PORT162_FN4, MSEL4CR_14_1),
+
+        /* Function 5 */
+        PINMUX_DATA(GPI0_MARK,          PORT41_FN5),
+        PINMUX_DATA(GPI1_MARK,          PORT42_FN5),
+        PINMUX_DATA(GPO0_MARK,          PORT43_FN5),
+        PINMUX_DATA(GPO1_MARK,          PORT44_FN5),
+        PINMUX_DATA(I2C_SCL3S_MARK,     PORT137_FN5, MSEL4CR_16_0),
+        PINMUX_DATA(I2C_SDA3S_MARK,     PORT145_FN5, MSEL4CR_16_0),
+        PINMUX_DATA(I2C_SCL4S_MARK,     PORT146_FN5, MSEL4CR_17_0),
+        PINMUX_DATA(I2C_SDA4S_MARK,     PORT147_FN5, MSEL4CR_17_0),
+
+        /* Function select */
+        PINMUX_DATA(LCDC0_SELECT_MARK,  MSEL3CR_6_0),
+        PINMUX_DATA(LCDC1_SELECT_MARK,  MSEL3CR_6_1),
+
+        PINMUX_DATA(TS0_1SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_0),
+        PINMUX_DATA(TS0_2SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_1),
+        PINMUX_DATA(TS1_1SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_0),
+        PINMUX_DATA(TS1_2SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_1),
+
+        PINMUX_DATA(SDENC_CPG_MARK,     MSEL4CR_19_0),
+        PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
+
+        PINMUX_DATA(MFIv6_MARK,         MSEL4CR_6_0),
+        PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
+};
+
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define GPIO_PORT_ALL() _190(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+static struct pinmux_gpio pinmux_gpios[] = {
+
+        /* PORT */
+        GPIO_PORT_ALL(),
+
+        /* IRQ */
+        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
+        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
+        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
+        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
+        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
+        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
+        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
+        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
+        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
+        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
+        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
+        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
+        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
+        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
+        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
+        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
+        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
+
+        /* MSIOF0 */
+        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
+        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
+        GPIO_FN(MSIOF0_TXD),
+
+        /* MSIOF1 */
+        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
+        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
+        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
+        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
+        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
+        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
+        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
+        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
+
+        /* MSIOF2 */
+        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
+        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
+        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
+        GPIO_FN(MSIOF2_TXD),
+
+        /* BBIF1 */
+        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
+        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
+        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
+
+        /* BBIF2 */
+        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
+        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
+
+        /* FSI */
+        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
+        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
+        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
+        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
+
+        /* FMSI */
+        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
+        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
+        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
+        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
+
+        /* SCIFA0 */
+        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
+        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
+
+        /* SCIFA1 */
+        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
+        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
+
+        /* SCIFA2 */
+        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
+        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
+
+        /* SCIFA3 */
+        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
+        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
+        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
+        GPIO_FN(SCIFA3_RXD),
+
+        /* SCIFA4 */
+        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
+
+        /* SCIFA5 */
+        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
+
+        /* SCIFB */
+        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
+        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
+
+        /* CEU */
+        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
+        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
+        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
+        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
+        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
+        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
+        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
+        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
+
+        /* USB0 */
+        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
+        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
+
+        /* USB1 */
+        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
+        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
+        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
+        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
+        GPIO_FN(VBUS0_1),
+
+        /* GPIO */
+        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
+
+        /* BSC */
+        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
+        GPIO_FN(WAIT),  GPIO_FN(RDWR),
+
+        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
+        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
+        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
+        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
+        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
+        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
+        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
+        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
+        GPIO_FN(A26),
+
+        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
+        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
+
+        /* BSC/FLCTL */
+        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
+        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
+        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
+        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
+        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
+        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
+        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
+
+        /* MMCIF(1) */
+        GPIO_FN(MMCD0_0),       GPIO_FN(MMCD0_1),       GPIO_FN(MMCD0_2),
+        GPIO_FN(MMCD0_3),       GPIO_FN(MMCD0_4),       GPIO_FN(MMCD0_5),
+        GPIO_FN(MMCD0_6),       GPIO_FN(MMCD0_7),       GPIO_FN(MMCCMD0),
+        GPIO_FN(MMCCLK0),
+
+        /* MMCIF(2) */
+        GPIO_FN(MMCD1_0),       GPIO_FN(MMCD1_1),       GPIO_FN(MMCD1_2),
+        GPIO_FN(MMCD1_3),       GPIO_FN(MMCD1_4),       GPIO_FN(MMCD1_5),
+        GPIO_FN(MMCD1_6),       GPIO_FN(MMCD1_7),       GPIO_FN(MMCCLK1),
+        GPIO_FN(MMCCMD1),
+
+        /* SPU2 */
+        GPIO_FN(VINT_I),
+
+        /* FLCTL */
+        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
+
+        /* HSI */
+        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
+        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
+        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
+
+        /* MFI */
+        GPIO_FN(MFIv6),
+        GPIO_FN(MFIv4),
+
+        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
+        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
+        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
+        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
+
+        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
+        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
+        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
+        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
+        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
+        GPIO_FN(MEMC_AD15),
+
+        /* SIM */
+        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
+
+        /* TPU */
+        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
+        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
+
+        /* I2C2 */
+        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
+
+        /* I2C3(1) */
+        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
+
+        /* I2C3(2) */
+        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
+
+        /* I2C4(2) */
+        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
+
+        /* I2C4(2) */
+        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
+
+        /* KEYSC */
+        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
+        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
+        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
+        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
+        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
+        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
+        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
+
+        /* LCDC */
+        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
+        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
+        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
+        GPIO_FN(LCDDON),
+
+        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
+        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
+        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
+        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
+        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
+        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
+        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
+        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
+
+        GPIO_FN(LCDC0_SELECT),
+        GPIO_FN(LCDC1_SELECT),
+
+        /* IRDA */
+        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
+        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
+
+        /* TSIF1 */
+        GPIO_FN(TS0_1SELECT),
+        GPIO_FN(TS0_2SELECT),
+        GPIO_FN(TS1_1SELECT),
+        GPIO_FN(TS1_2SELECT),
+
+        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
+        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
+
+        /* TSIF2 */
+        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
+        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
+
+        /* HDMI */
+        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
+
+        /* SDHI0 */
+        GPIO_FN(SDHICLK0),      GPIO_FN(SDHICD0),       GPIO_FN(SDHICMD0),
+        GPIO_FN(SDHIWP0),       GPIO_FN(SDHID0_0),      GPIO_FN(SDHID0_1),
+        GPIO_FN(SDHID0_2),      GPIO_FN(SDHID0_3),
+
+        /* SDHI1 */
+        GPIO_FN(SDHICLK1),      GPIO_FN(SDHICMD1),      GPIO_FN(SDHID1_0),
+        GPIO_FN(SDHID1_1),      GPIO_FN(SDHID1_2),      GPIO_FN(SDHID1_3),
+
+        /* SDHI2 */
+        GPIO_FN(SDHICLK2),      GPIO_FN(SDHICMD2),      GPIO_FN(SDHID2_0),
+        GPIO_FN(SDHID2_1),      GPIO_FN(SDHID2_2),      GPIO_FN(SDHID2_3),
+
+        /* SDENC */
+        GPIO_FN(SDENC_CPG),
+        GPIO_FN(SDENC_DV_CLKI),
+};
+
+/* helper for top 4 bits in PORTnCR */
+#define PCRH(in, in_pd, in_pu, out)             \
+        0, (out), (in), 0,                      \
+        0, 0, 0, 0,                             \
+        0, 0, (in_pd), 0,                       \
+        0, 0, (in_pu), 0
+
+#define PORTCR(nr, reg)                                         \
+        { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {           \
+                PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,           \
+                     PORT##nr##_IN_PU, PORT##nr##_OUT),         \
+                PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
+                PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
+                PORT##nr##_FN6, PORT##nr##_FN7 }                \
+        }
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        PORTCR(0,       0xE6051000), /* PORT0CR */
+        PORTCR(1,       0xE6051001), /* PORT1CR */
+        PORTCR(2,       0xE6051002), /* PORT2CR */
+        PORTCR(3,       0xE6051003), /* PORT3CR */
+        PORTCR(4,       0xE6051004), /* PORT4CR */
+        PORTCR(5,       0xE6051005), /* PORT5CR */
+        PORTCR(6,       0xE6051006), /* PORT6CR */
+        PORTCR(7,       0xE6051007), /* PORT7CR */
+        PORTCR(8,       0xE6051008), /* PORT8CR */
+        PORTCR(9,       0xE6051009), /* PORT9CR */
+        PORTCR(10,      0xE605100A), /* PORT10CR */
+        PORTCR(11,      0xE605100B), /* PORT11CR */
+        PORTCR(12,      0xE605100C), /* PORT12CR */
+        PORTCR(13,      0xE605100D), /* PORT13CR */
+        PORTCR(14,      0xE605100E), /* PORT14CR */
+        PORTCR(15,      0xE605100F), /* PORT15CR */
+        PORTCR(16,      0xE6051010), /* PORT16CR */
+        PORTCR(17,      0xE6051011), /* PORT17CR */
+        PORTCR(18,      0xE6051012), /* PORT18CR */
+        PORTCR(19,      0xE6051013), /* PORT19CR */
+        PORTCR(20,      0xE6051014), /* PORT20CR */
+        PORTCR(21,      0xE6051015), /* PORT21CR */
+        PORTCR(22,      0xE6051016), /* PORT22CR */
+        PORTCR(23,      0xE6051017), /* PORT23CR */
+        PORTCR(24,      0xE6051018), /* PORT24CR */
+        PORTCR(25,      0xE6051019), /* PORT25CR */
+        PORTCR(26,      0xE605101A), /* PORT26CR */
+        PORTCR(27,      0xE605101B), /* PORT27CR */
+        PORTCR(28,      0xE605101C), /* PORT28CR */
+        PORTCR(29,      0xE605101D), /* PORT29CR */
+        PORTCR(30,      0xE605101E), /* PORT30CR */
+        PORTCR(31,      0xE605101F), /* PORT31CR */
+        PORTCR(32,      0xE6051020), /* PORT32CR */
+        PORTCR(33,      0xE6051021), /* PORT33CR */
+        PORTCR(34,      0xE6051022), /* PORT34CR */
+        PORTCR(35,      0xE6051023), /* PORT35CR */
+        PORTCR(36,      0xE6051024), /* PORT36CR */
+        PORTCR(37,      0xE6051025), /* PORT37CR */
+        PORTCR(38,      0xE6051026), /* PORT38CR */
+        PORTCR(39,      0xE6051027), /* PORT39CR */
+        PORTCR(40,      0xE6051028), /* PORT40CR */
+        PORTCR(41,      0xE6051029), /* PORT41CR */
+        PORTCR(42,      0xE605102A), /* PORT42CR */
+        PORTCR(43,      0xE605102B), /* PORT43CR */
+        PORTCR(44,      0xE605102C), /* PORT44CR */
+        PORTCR(45,      0xE605102D), /* PORT45CR */
+        PORTCR(46,      0xE605202E), /* PORT46CR */
+        PORTCR(47,      0xE605202F), /* PORT47CR */
+        PORTCR(48,      0xE6052030), /* PORT48CR */
+        PORTCR(49,      0xE6052031), /* PORT49CR */
+        PORTCR(50,      0xE6052032), /* PORT50CR */
+        PORTCR(51,      0xE6052033), /* PORT51CR */
+        PORTCR(52,      0xE6052034), /* PORT52CR */
+        PORTCR(53,      0xE6052035), /* PORT53CR */
+        PORTCR(54,      0xE6052036), /* PORT54CR */
+        PORTCR(55,      0xE6052037), /* PORT55CR */
+        PORTCR(56,      0xE6052038), /* PORT56CR */
+        PORTCR(57,      0xE6052039), /* PORT57CR */
+        PORTCR(58,      0xE605203A), /* PORT58CR */
+        PORTCR(59,      0xE605203B), /* PORT59CR */
+        PORTCR(60,      0xE605203C), /* PORT60CR */
+        PORTCR(61,      0xE605203D), /* PORT61CR */
+        PORTCR(62,      0xE605203E), /* PORT62CR */
+        PORTCR(63,      0xE605203F), /* PORT63CR */
+        PORTCR(64,      0xE6052040), /* PORT64CR */
+        PORTCR(65,      0xE6052041), /* PORT65CR */
+        PORTCR(66,      0xE6052042), /* PORT66CR */
+        PORTCR(67,      0xE6052043), /* PORT67CR */
+        PORTCR(68,      0xE6052044), /* PORT68CR */
+        PORTCR(69,      0xE6052045), /* PORT69CR */
+        PORTCR(70,      0xE6052046), /* PORT70CR */
+        PORTCR(71,      0xE6052047), /* PORT71CR */
+        PORTCR(72,      0xE6052048), /* PORT72CR */
+        PORTCR(73,      0xE6052049), /* PORT73CR */
+        PORTCR(74,      0xE605204A), /* PORT74CR */
+        PORTCR(75,      0xE605204B), /* PORT75CR */
+        PORTCR(76,      0xE605004C), /* PORT76CR */
+        PORTCR(77,      0xE605004D), /* PORT77CR */
+        PORTCR(78,      0xE605004E), /* PORT78CR */
+        PORTCR(79,      0xE605004F), /* PORT79CR */
+        PORTCR(80,      0xE6050050), /* PORT80CR */
+        PORTCR(81,      0xE6050051), /* PORT81CR */
+        PORTCR(82,      0xE6050052), /* PORT82CR */
+        PORTCR(83,      0xE6050053), /* PORT83CR */
+        PORTCR(84,      0xE6050054), /* PORT84CR */
+        PORTCR(85,      0xE6050055), /* PORT85CR */
+        PORTCR(86,      0xE6050056), /* PORT86CR */
+        PORTCR(87,      0xE6050057), /* PORT87CR */
+        PORTCR(88,      0xE6050058), /* PORT88CR */
+        PORTCR(89,      0xE6050059), /* PORT89CR */
+        PORTCR(90,      0xE605005A), /* PORT90CR */
+        PORTCR(91,      0xE605005B), /* PORT91CR */
+        PORTCR(92,      0xE605005C), /* PORT92CR */
+        PORTCR(93,      0xE605005D), /* PORT93CR */
+        PORTCR(94,      0xE605005E), /* PORT94CR */
+        PORTCR(95,      0xE605005F), /* PORT95CR */
+        PORTCR(96,      0xE6050060), /* PORT96CR */
+        PORTCR(97,      0xE6050061), /* PORT97CR */
+        PORTCR(98,      0xE6050062), /* PORT98CR */
+        PORTCR(99,      0xE6050063), /* PORT99CR */
+        PORTCR(100,     0xE6053064), /* PORT100CR */
+        PORTCR(101,     0xE6053065), /* PORT101CR */
+        PORTCR(102,     0xE6053066), /* PORT102CR */
+        PORTCR(103,     0xE6053067), /* PORT103CR */
+        PORTCR(104,     0xE6053068), /* PORT104CR */
+        PORTCR(105,     0xE6053069), /* PORT105CR */
+        PORTCR(106,     0xE605306A), /* PORT106CR */
+        PORTCR(107,     0xE605306B), /* PORT107CR */
+        PORTCR(108,     0xE605306C), /* PORT108CR */
+        PORTCR(109,     0xE605306D), /* PORT109CR */
+        PORTCR(110,     0xE605306E), /* PORT110CR */
+        PORTCR(111,     0xE605306F), /* PORT111CR */
+        PORTCR(112,     0xE6053070), /* PORT112CR */
+        PORTCR(113,     0xE6053071), /* PORT113CR */
+        PORTCR(114,     0xE6053072), /* PORT114CR */
+        PORTCR(115,     0xE6053073), /* PORT115CR */
+        PORTCR(116,     0xE6053074), /* PORT116CR */
+        PORTCR(117,     0xE6053075), /* PORT117CR */
+        PORTCR(118,     0xE6053076), /* PORT118CR */
+        PORTCR(119,     0xE6053077), /* PORT119CR */
+        PORTCR(120,     0xE6053078), /* PORT120CR */
+        PORTCR(121,     0xE6050079), /* PORT121CR */
+        PORTCR(122,     0xE605007A), /* PORT122CR */
+        PORTCR(123,     0xE605007B), /* PORT123CR */
+        PORTCR(124,     0xE605007C), /* PORT124CR */
+        PORTCR(125,     0xE605007D), /* PORT125CR */
+        PORTCR(126,     0xE605007E), /* PORT126CR */
+        PORTCR(127,     0xE605007F), /* PORT127CR */
+        PORTCR(128,     0xE6050080), /* PORT128CR */
+        PORTCR(129,     0xE6050081), /* PORT129CR */
+        PORTCR(130,     0xE6050082), /* PORT130CR */
+        PORTCR(131,     0xE6050083), /* PORT131CR */
+        PORTCR(132,     0xE6050084), /* PORT132CR */
+        PORTCR(133,     0xE6050085), /* PORT133CR */
+        PORTCR(134,     0xE6050086), /* PORT134CR */
+        PORTCR(135,     0xE6050087), /* PORT135CR */
+        PORTCR(136,     0xE6050088), /* PORT136CR */
+        PORTCR(137,     0xE6050089), /* PORT137CR */
+        PORTCR(138,     0xE605008A), /* PORT138CR */
+        PORTCR(139,     0xE605008B), /* PORT139CR */
+        PORTCR(140,     0xE605008C), /* PORT140CR */
+        PORTCR(141,     0xE605008D), /* PORT141CR */
+        PORTCR(142,     0xE605008E), /* PORT142CR */
+        PORTCR(143,     0xE605008F), /* PORT143CR */
+        PORTCR(144,     0xE6050090), /* PORT144CR */
+        PORTCR(145,     0xE6050091), /* PORT145CR */
+        PORTCR(146,     0xE6050092), /* PORT146CR */
+        PORTCR(147,     0xE6050093), /* PORT147CR */
+        PORTCR(148,     0xE6050094), /* PORT148CR */
+        PORTCR(149,     0xE6050095), /* PORT149CR */
+        PORTCR(150,     0xE6050096), /* PORT150CR */
+        PORTCR(151,     0xE6050097), /* PORT151CR */
+        PORTCR(152,     0xE6053098), /* PORT152CR */
+        PORTCR(153,     0xE6053099), /* PORT153CR */
+        PORTCR(154,     0xE605309A), /* PORT154CR */
+        PORTCR(155,     0xE605309B), /* PORT155CR */
+        PORTCR(156,     0xE605009C), /* PORT156CR */
+        PORTCR(157,     0xE605009D), /* PORT157CR */
+        PORTCR(158,     0xE605009E), /* PORT158CR */
+        PORTCR(159,     0xE605009F), /* PORT159CR */
+        PORTCR(160,     0xE60500A0), /* PORT160CR */
+        PORTCR(161,     0xE60500A1), /* PORT161CR */
+        PORTCR(162,     0xE60500A2), /* PORT162CR */
+        PORTCR(163,     0xE60500A3), /* PORT163CR */
+        PORTCR(164,     0xE60500A4), /* PORT164CR */
+        PORTCR(165,     0xE60500A5), /* PORT165CR */
+        PORTCR(166,     0xE60500A6), /* PORT166CR */
+        PORTCR(167,     0xE60520A7), /* PORT167CR */
+        PORTCR(168,     0xE60520A8), /* PORT168CR */
+        PORTCR(169,     0xE60520A9), /* PORT169CR */
+        PORTCR(170,     0xE60520AA), /* PORT170CR */
+        PORTCR(171,     0xE60520AB), /* PORT171CR */
+        PORTCR(172,     0xE60520AC), /* PORT172CR */
+        PORTCR(173,     0xE60520AD), /* PORT173CR */
+        PORTCR(174,     0xE60520AE), /* PORT174CR */
+        PORTCR(175,     0xE60520AF), /* PORT175CR */
+        PORTCR(176,     0xE60520B0), /* PORT176CR */
+        PORTCR(177,     0xE60520B1), /* PORT177CR */
+        PORTCR(178,     0xE60520B2), /* PORT178CR */
+        PORTCR(179,     0xE60520B3), /* PORT179CR */
+        PORTCR(180,     0xE60520B4), /* PORT180CR */
+        PORTCR(181,     0xE60520B5), /* PORT181CR */
+        PORTCR(182,     0xE60520B6), /* PORT182CR */
+        PORTCR(183,     0xE60520B7), /* PORT183CR */
+        PORTCR(184,     0xE60520B8), /* PORT184CR */
+        PORTCR(185,     0xE60520B9), /* PORT185CR */
+        PORTCR(186,     0xE60520BA), /* PORT186CR */
+        PORTCR(187,     0xE60520BB), /* PORT187CR */
+        PORTCR(188,     0xE60520BC), /* PORT188CR */
+        PORTCR(189,     0xE60520BD), /* PORT189CR */
+        PORTCR(190,     0xE60520BE), /* PORT190CR */
+
+        { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
+                        MSEL1CR_31_0,   MSEL1CR_31_1,
+                        MSEL1CR_30_0,   MSEL1CR_30_1,
+                        MSEL1CR_29_0,   MSEL1CR_29_1,
+                        MSEL1CR_28_0,   MSEL1CR_28_1,
+                        MSEL1CR_27_0,   MSEL1CR_27_1,
+                        MSEL1CR_26_0,   MSEL1CR_26_1,
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        MSEL1CR_16_0,   MSEL1CR_16_1,
+                        MSEL1CR_15_0,   MSEL1CR_15_1,
+                        MSEL1CR_14_0,   MSEL1CR_14_1,
+                        MSEL1CR_13_0,   MSEL1CR_13_1,
+                        MSEL1CR_12_0,   MSEL1CR_12_1,
+                        0, 0, 0, 0,
+                        MSEL1CR_9_0,    MSEL1CR_9_1,
+                        MSEL1CR_8_0,    MSEL1CR_8_1,
+                        MSEL1CR_7_0,    MSEL1CR_7_1,
+                        MSEL1CR_6_0,    MSEL1CR_6_1,
+                        0, 0,
+                        MSEL1CR_4_0,    MSEL1CR_4_1,
+                        MSEL1CR_3_0,    MSEL1CR_3_1,
+                        MSEL1CR_2_0,    MSEL1CR_2_1,
+                        0, 0,
+                        MSEL1CR_0_0,    MSEL1CR_0_1,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        MSEL3CR_27_0,   MSEL3CR_27_1,
+                        MSEL3CR_26_0,   MSEL3CR_26_1,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        MSEL3CR_21_0,   MSEL3CR_21_1,
+                        MSEL3CR_20_0,   MSEL3CR_20_1,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        MSEL3CR_15_0,   MSEL3CR_15_1,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0,
+                        MSEL3CR_9_0,    MSEL3CR_9_1,
+                        0, 0, 0, 0,
+                        MSEL3CR_6_0,    MSEL3CR_6_1,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        }
+        },
+        { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        MSEL4CR_19_0,   MSEL4CR_19_1,
+                        MSEL4CR_18_0,   MSEL4CR_18_1,
+                        MSEL4CR_17_0,   MSEL4CR_17_1,
+                        MSEL4CR_16_0,   MSEL4CR_16_1,
+                        MSEL4CR_15_0,   MSEL4CR_15_1,
+                        MSEL4CR_14_0,   MSEL4CR_14_1,
+                        0, 0, 0, 0,
+                        0, 0,
+                        MSEL4CR_10_0,   MSEL4CR_10_1,
+                        0, 0, 0, 0,
+                        0, 0,
+                        MSEL4CR_6_0,    MSEL4CR_6_1,
+                        0, 0,
+                        MSEL4CR_4_0,    MSEL4CR_4_1,
+                        0, 0, 0, 0,
+                        MSEL4CR_1_0,    MSEL4CR_1_1,
+                        0, 0,
+                }
+        },
+        { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
+                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                }
+        },
+        { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
+                        PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+                        PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        PORT99_DATA,  PORT98_DATA,  PORT97_DATA,  PORT96_DATA,
+                }
+        },
+        { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
+                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+                        0, 0, 0, 0,
+                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
+                }
+        },
+        { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0,            PORT166_DATA, PORT165_DATA, PORT164_DATA,
+                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
+                }
+        },
+        { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
+                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+                        PORT11_DATA, PORT10_DATA, PORT9_DATA,  PORT8_DATA,
+                        PORT7_DATA,  PORT6_DATA,  PORT5_DATA,  PORT4_DATA,
+                        PORT3_DATA,  PORT2_DATA,  PORT1_DATA,  PORT0_DATA,
+                }
+        },
+        { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0,           0,           PORT45_DATA, PORT44_DATA,
+                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
+                }
+        },
+        { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
+                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+                        PORT47_DATA, PORT46_DATA, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                }
+        },
+        { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
+                }
+        },
+        { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
+                        0,            PORT190_DATA, PORT189_DATA, PORT188_DATA,
+                        PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
+                        PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
+                        PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+                        PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+                        PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+                        PORT167_DATA, 0, 0, 0,
+                        0, 0, 0, 0,
+                }
+        },
+        { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, PORT120_DATA,
+                        PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+                        0, 0, 0, 0,
+                }
+        },
+        { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
+                        0, 0, 0, 0,
+                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                }
+        },
+        { },
+};
+
+static struct pinmux_info sh7372_pinmux_info = {
+        .name = "sh7372_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PORT0,
+        .last_gpio = GPIO_FN_SDENC_DV_CLKI,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void sh7372_pinmux_init(void)
+{
+        register_pinmux(&sh7372_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
new file mode 100644
index 000000000000..613e6842ad05
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh7377.c
@@ -0,0 +1,1767 @@
+/*
+ * sh7377 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010  NISHIMOTO Hiroki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/sh7377.h>
+
+#define _1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define _10(fn, pfx, sfx)                               \
+        _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx),       \
+        _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx),       \
+        _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx),       \
+        _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx),       \
+        _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
+
+#define _90(fn, pfx, sfx)                               \
+        _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx),     \
+        _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx),     \
+        _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx),     \
+        _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx),     \
+        _10(fn, pfx##9, sfx)
+
+#define _265(fn, pfx, sfx)                              \
+        _10(fn, pfx, sfx), _90(fn, pfx, sfx),           \
+        _10(fn, pfx##10, sfx),                          \
+        _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx),   \
+        _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx),   \
+        _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx),   \
+        _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx),   \
+        _1(fn, pfx##118, sfx),                          \
+        _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx),   \
+        _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx),   \
+        _10(fn, pfx##15, sfx),                          \
+        _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx),   \
+        _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx),   \
+        _1(fn, pfx##164, sfx),                          \
+        _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx),   \
+        _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx),   \
+        _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx),   \
+        _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx),   \
+        _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx),   \
+        _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx),   \
+        _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx),   \
+        _1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx),   \
+        _1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx),   \
+        _1(fn, pfx##264, sfx)
+
+#define _PORT(pfx, sfx) pfx##_##sfx
+#define PORT_265(str) _265(_PORT, PORT, str)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PORT_265(IN), /* PORT0_IN -> PORT264_IN */
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
+        PINMUX_INPUT_PULLDOWN_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
+        PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
+        PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */
+        PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */
+        PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */
+        PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */
+        PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */
+        PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */
+        PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */
+        PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */
+
+        MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
+        MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* Special Pull-up / Pull-down Functions */
+        PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK,
+        PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK,
+        PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK,
+        PORT72_KEYIN6_PU_MARK,
+
+        /* 55-1 */
+        VBUS_0_MARK,
+        CPORT0_MARK,
+        CPORT1_MARK,
+        CPORT2_MARK,
+        CPORT3_MARK,
+        CPORT4_MARK,
+        CPORT5_MARK,
+        CPORT6_MARK,
+        CPORT7_MARK,
+        CPORT8_MARK,
+        CPORT9_MARK,
+        CPORT10_MARK,
+        CPORT11_MARK, SIN2_MARK,
+        CPORT12_MARK, XCTS2_MARK,
+        CPORT13_MARK, RFSPO4_MARK,
+        CPORT14_MARK, RFSPO5_MARK,
+        CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK,
+        CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK,
+        CPORT17_IC_OE_MARK, SOUT2_MARK,
+        CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK,
+        CPORT19_MPORT1_MARK,
+        CPORT20_MARK, RFSPO6_MARK,
+        CPORT21_MARK, STATUS0_MARK,
+        CPORT22_MARK, STATUS1_MARK,
+        CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
+        B_SYNLD1_MARK,
+        B_SYNLD2_MARK, SYSENMSK_MARK,
+        XMAINPS_MARK,
+        XDIVPS_MARK,
+        XIDRST_MARK,
+        IDCLK_MARK, IC_DP_MARK,
+        IDIO_MARK, IC_DM_MARK,
+        SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK,
+        SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
+        XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
+        XCTS1_MARK, SCIFA4_CTS_MARK,
+        PCMCLKO_MARK,
+        SYNC8KO_MARK,
+
+        /* 55-2 */
+        DNPCM_A_MARK,
+        UPPCM_A_MARK,
+        VACK_MARK,
+        XTALB1L_MARK,
+        GPS_AGC1_MARK, SCIFA0_RTS_MARK,
+        GPS_AGC4_MARK, SCIFA0_RXD_MARK,
+        GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK,
+        GPS_IM_MARK,
+        GPS_IS_MARK,
+        GPS_QM_MARK,
+        GPS_QS_MARK,
+        FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK,
+        FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK,
+        FMSIOLR_MARK,
+        FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK,
+        FMSIOBT_MARK,
+        FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK,
+        FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK,
+        FMSIILR_MARK,
+        FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK,
+        FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK,
+        A0_EA0_MARK, BS_MARK,
+        A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK,
+        A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK,
+        A14_EA14_MARK, PORT60_KEYOUT5_MARK,
+        A15_EA15_MARK, PORT61_KEYOUT4_MARK,
+        A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK,
+        A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+        A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+        A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK,
+        A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK,
+        A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+        A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK,
+        A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK,
+        A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK,
+        A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK,
+        A26_MARK, PORT72_KEYIN6_MARK,
+        D0_ED0_NAF0_MARK,
+        D1_ED1_NAF1_MARK,
+        D2_ED2_NAF2_MARK,
+        D3_ED3_NAF3_MARK,
+        D4_ED4_NAF4_MARK,
+        D5_ED5_NAF5_MARK,
+        D6_ED6_NAF6_MARK,
+        D7_ED7_NAF7_MARK,
+        D8_ED8_NAF8_MARK,
+        D9_ED9_NAF9_MARK,
+        D10_ED10_NAF10_MARK,
+        D11_ED11_NAF11_MARK,
+        D12_ED12_NAF12_MARK,
+        D13_ED13_NAF13_MARK,
+        D14_ED14_NAF14_MARK,
+        D15_ED15_NAF15_MARK,
+        CS4_MARK,
+        CS5A_MARK, FMSICK_MARK,
+        CS5B_MARK, FCE1_MARK,
+
+        /* 55-3 */
+        CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK,
+        FCE0_MARK,
+        WAIT_MARK, DREQ0_MARK,
+        RD_XRD_MARK,
+        WE0_XWR0_FWE_MARK,
+        WE1_XWR1_MARK,
+        FRB_MARK,
+        CKO_MARK,
+        NBRSTOUT_MARK,
+        NBRST_MARK,
+        GPS_EPPSIN_MARK,
+        LATCHPULSE_MARK,
+        LTESIGNAL_MARK,
+        LEGACYSTATE_MARK,
+        TCKON_MARK,
+        VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK,
+        VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK,
+        VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK,
+        VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK,
+        VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK,
+        VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK,
+        VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK,
+        VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK,
+        VIO_D6_MARK, PORT136_KEYIN2_MARK,
+        VIO_D7_MARK, PORT137_KEYIN3_MARK,
+        VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK,
+        VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK,
+        VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK,
+        VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK,
+        VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK,
+        VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK,
+        VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK,
+        VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK,
+        VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK,
+        VIO_FIELD_MARK, PORT147_KEYIN5_MARK,
+        VIO_CKO_MARK, PORT148_KEYIN6_MARK,
+        A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK,
+        MFG0_IN2_MARK,
+        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+        SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+        SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+        XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK,
+        XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK,
+
+        /* 55-4 */
+        DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK,
+        PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK,
+        MFG3_IN2_MARK,
+        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK,
+        MFG3_IN1_MARK,
+        PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK,
+        MFG3_OUT1_MARK, TPU3TO0_MARK,
+        LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK,
+        LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK,
+        BBIF2_TSYNC1_MARK,
+        LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK,
+        BBIF2_TSCK1_MARK,
+        LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK,
+        BBIF2_TXD1_MARK,
+        LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK,
+        LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK,
+        MFG2_OUT2_MARK,
+        TPU2TO1_MARK,
+        LCDD6_MARK, XWR2_MARK,
+        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK,
+        LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK,
+        LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK,
+        LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK,
+        LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK,
+        LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK,
+        LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK,
+        LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK,
+        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK,
+        VIO_DR7_MARK, D23_MARK, ED23_MARK,
+        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK,
+        VIO_VDR_MARK, D24_MARK, ED24_MARK,
+        LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK,
+        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK,
+        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK,
+        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK,
+        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK,
+        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK,
+        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK,
+        LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK,
+        LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK,
+        LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
+        PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK,
+        LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK,
+        LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK,
+        LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK,
+        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK,
+        SCIFA1_TXD_MARK, OVCN2_MARK,
+        EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK,
+        SCIFA1_RTS_MARK, IDIN_MARK,
+        SCIFA1_RXD_MARK,
+        SCIFA1_CTS_MARK, MFG1_IN1_MARK,
+        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK,
+        MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK,
+        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK,
+        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK,
+        PORT233_FSIACK_MARK,
+        MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK,
+        MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK,
+        MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK,
+        MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK,
+        MSIOF1_SS1_MARK, EDBGREQ3_MARK,
+
+        /* 55-5 */
+        MSIOF1_SS2_MARK,
+        SCIFA6_TXD_MARK,
+        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK,
+        TPU4TO0_MARK,
+        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+        PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK,
+        PORT244_MSIOF2_RXD_MARK,
+        PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK,
+        PORT245_MSIOF2_TXD_MARK,
+        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK,
+        TPU1TO0_MARK,
+        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK,
+        TPU3TO1_MARK,
+        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK,
+        TPU2TO0_MARK,
+        PORT248_MSIOF2_TSCK_MARK,
+        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK,
+        SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK,
+        SDHICD0_MARK,
+        SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK,
+        SDHID0_1_MARK, TDO2_SWO0_MC0_MARK,
+        SDHID0_2_MARK, TDI2_MARK,
+        SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK,
+        SDHICMD0_MARK, TRST2_MARK,
+        SDHIWP0_MARK, EDBGREQ2_MARK,
+        SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK,
+        SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK,
+        TMS3_SWDIO_MC1_MARK,
+        SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK,
+        SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK,
+        SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK,
+        SDHICMD1_MARK, TRST3_MARK,
+        RESETOUTS_MARK,
+        PINMUX_MARK_END,
+};
+
+#define PORT_DATA_I(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr)      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr)      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr)   \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PD,        \
+                                PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr)        \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr)     \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr)     \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr)  \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+static pinmux_enum_t pinmux_data[] = {
+        /* specify valid pin states for each pin in GPIO mode */
+        /* 55-1 (GPIO) */
+        PORT_DATA_I_PD(0), PORT_DATA_I_PU(1),
+        PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
+        PORT_DATA_I_PU(4), PORT_DATA_I_PU(5),
+        PORT_DATA_I_PU(6), PORT_DATA_I_PU(7),
+        PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
+        PORT_DATA_I_PU(10), PORT_DATA_I_PU(11),
+        PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13),
+        PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
+        PORT_DATA_O(16), PORT_DATA_IO(17),
+        PORT_DATA_O(18), PORT_DATA_O(19),
+        PORT_DATA_O(20), PORT_DATA_O(21),
+        PORT_DATA_O(22), PORT_DATA_O(23),
+        PORT_DATA_O(24), PORT_DATA_I_PD(25),
+        PORT_DATA_I_PD(26), PORT_DATA_O(27),
+        PORT_DATA_O(28), PORT_DATA_O(29),
+        PORT_DATA_IO(30), PORT_DATA_IO_PU(31),
+        PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33),
+        PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35),
+        PORT_DATA_O(36), PORT_DATA_IO(37),
+
+        /* 55-2 (GPIO) */
+        PORT_DATA_O(38), PORT_DATA_I_PU(39),
+        PORT_DATA_I_PU_PD(40), PORT_DATA_O(41),
+        PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43),
+        PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45),
+        PORT_DATA_I_PD(46), PORT_DATA_I_PD(47),
+        PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49),
+        PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51),
+        PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53),
+        PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55),
+        PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57),
+        PORT_DATA_IO(58), PORT_DATA_IO(59),
+        PORT_DATA_IO(60), PORT_DATA_IO(61),
+        PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
+        PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
+        PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
+        PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
+        PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
+        PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73),
+        PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75),
+        PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77),
+        PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79),
+        PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81),
+        PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83),
+        PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85),
+        PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87),
+        PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89),
+        PORT_DATA_O(90), PORT_DATA_IO_PU(91),
+        PORT_DATA_O(92),
+
+        /* 55-3 (GPIO) */
+        PORT_DATA_IO_PU(93),
+        PORT_DATA_O(94),
+        PORT_DATA_I_PU_PD(95),
+        PORT_DATA_IO(96), PORT_DATA_IO(97),
+        PORT_DATA_IO(98), PORT_DATA_I_PU(99),
+        PORT_DATA_O(100), PORT_DATA_O(101),
+        PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103),
+        PORT_DATA_I_PD(104), PORT_DATA_I_PD(105),
+        PORT_DATA_I_PD(106), PORT_DATA_I_PD(107),
+        PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109),
+        PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111),
+        PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
+        PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115),
+        PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117),
+        PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128),
+        PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130),
+        PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132),
+        PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134),
+        PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136),
+        PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138),
+        PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140),
+        PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142),
+        PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144),
+        PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146),
+        PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148),
+        PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150),
+        PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152),
+        PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154),
+        PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156),
+        PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158),
+
+        /* 55-4 (GPIO) */
+        PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160),
+        PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162),
+        PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164),
+        PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193),
+        PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
+        PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197),
+        PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199),
+        PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
+        PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
+        PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
+        PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207),
+        PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209),
+        PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
+        PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213),
+        PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215),
+        PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217),
+        PORT_DATA_O(218), PORT_DATA_IO_PD(219),
+        PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221),
+        PORT_DATA_IO_PU_PD(222),
+        PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224),
+        PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226),
+        PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228),
+        PORT_DATA_I_PD(229), PORT_DATA_IO(230),
+        PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232),
+        PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234),
+        PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236),
+        PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238),
+
+        /* 55-5 (GPIO) */
+        PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240),
+        PORT_DATA_O(241), PORT_DATA_I_PD(242),
+        PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244),
+        PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246),
+        PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248),
+        PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250),
+        PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252),
+        PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254),
+        PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256),
+        PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258),
+        PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260),
+        PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262),
+        PORT_DATA_IO_PU_PD(263),
+
+        /* Special Pull-up / Pull-down Functions */
+        PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT66_FN2, PORT66_IN_PU),
+        PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT67_FN2, PORT67_IN_PU),
+        PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT68_FN2, PORT68_IN_PU),
+        PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT69_FN2, PORT69_IN_PU),
+        PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT70_FN2, PORT70_IN_PU),
+        PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT71_FN2, PORT71_IN_PU),
+        PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
+                                PORT72_FN2, PORT72_IN_PU),
+
+
+        /* 55-1 (FN) */
+        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+        PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
+        PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
+        PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
+        PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
+        PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
+        PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
+        PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
+        PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
+        PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
+        PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
+        PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
+        PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
+        PINMUX_DATA(SIN2_MARK, PORT12_FN2),
+        PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
+        PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
+        PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
+        PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
+        PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
+        PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
+        PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
+        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2),
+        PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3),
+        PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
+        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+        PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3),
+        PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1),
+        PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
+        PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
+        PINMUX_DATA(XRTS2_MARK, PORT19_FN2),
+        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+        PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1),
+        PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
+        PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
+        PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
+        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+        PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
+        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+        PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
+        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+        PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
+        PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1),
+        PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1),
+        PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2),
+        PINMUX_DATA(XMAINPS_MARK, PORT27_FN1),
+        PINMUX_DATA(XDIVPS_MARK, PORT28_FN1),
+        PINMUX_DATA(XIDRST_MARK, PORT29_FN1),
+        PINMUX_DATA(IDCLK_MARK, PORT30_FN1),
+        PINMUX_DATA(IC_DP_MARK, PORT30_FN2),
+        PINMUX_DATA(IDIO_MARK, PORT31_FN1),
+        PINMUX_DATA(IC_DM_MARK, PORT31_FN2),
+        PINMUX_DATA(SOUT1_MARK, PORT32_FN1),
+        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+        PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3),
+        PINMUX_DATA(SIN1_MARK, PORT33_FN1),
+        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2),
+        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+        PINMUX_DATA(XRTS1_MARK, PORT34_FN1),
+        PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2),
+        PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3),
+        PINMUX_DATA(XCTS1_MARK, PORT35_FN1),
+        PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2),
+        PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1),
+        PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1),
+
+        /* 55-2 (FN) */
+        PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1),
+        PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1),
+        PINMUX_DATA(VACK_MARK, PORT40_FN1),
+        PINMUX_DATA(XTALB1L_MARK, PORT41_FN1),
+        PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1),
+        PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2),
+        PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1),
+        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+        PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1),
+        PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2),
+        PINMUX_DATA(GPS_IM_MARK, PORT45_FN1),
+        PINMUX_DATA(GPS_IS_MARK, PORT46_FN1),
+        PINMUX_DATA(GPS_QM_MARK, PORT47_FN1),
+        PINMUX_DATA(GPS_QS_MARK, PORT48_FN1),
+        PINMUX_DATA(FMSOCK_MARK, PORT49_FN1),
+        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2),
+        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3),
+        PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1),
+        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2),
+        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3),
+        PINMUX_DATA(IPORT3_MARK, PORT50_FN4),
+        PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5),
+        PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1),
+        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2),
+        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3),
+        PINMUX_DATA(OPORT1_MARK, PORT51_FN4),
+        PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5),
+        PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1),
+        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+        PINMUX_DATA(OPORT2_MARK, PORT52_FN3),
+        PINMUX_DATA(FMSOILR_MARK, PORT53_FN1),
+        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2),
+        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3),
+        PINMUX_DATA(OPORT3_MARK, PORT53_FN4),
+        PINMUX_DATA(FMSIILR_MARK, PORT53_FN5),
+        PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1),
+        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2),
+        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3),
+        PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4),
+        PINMUX_DATA(FMSISLD_MARK, PORT55_FN1),
+        PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2),
+        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+        PINMUX_DATA(A0_EA0_MARK, PORT57_FN1),
+        PINMUX_DATA(BS_MARK, PORT57_FN2),
+        PINMUX_DATA(A12_EA12_MARK, PORT58_FN1),
+        PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2),
+        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3),
+        PINMUX_DATA(A13_EA13_MARK, PORT59_FN1),
+        PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2),
+        PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3),
+        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+        PINMUX_DATA(A14_EA14_MARK, PORT60_FN1),
+        PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2),
+        PINMUX_DATA(A15_EA15_MARK, PORT61_FN1),
+        PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2),
+        PINMUX_DATA(A16_EA16_MARK, PORT62_FN1),
+        PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2),
+        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3),
+        PINMUX_DATA(A17_EA17_MARK, PORT63_FN1),
+        PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2),
+        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3),
+        PINMUX_DATA(A18_EA18_MARK, PORT64_FN1),
+        PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2),
+        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3),
+        PINMUX_DATA(A19_EA19_MARK, PORT65_FN1),
+        PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2),
+        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3),
+        PINMUX_DATA(A20_EA20_MARK, PORT66_FN1),
+        PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2),
+        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3),
+        PINMUX_DATA(A21_EA21_MARK, PORT67_FN1),
+        PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2),
+        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3),
+        PINMUX_DATA(A22_EA22_MARK, PORT68_FN1),
+        PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2),
+        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3),
+        PINMUX_DATA(A23_EA23_MARK, PORT69_FN1),
+        PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2),
+        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3),
+        PINMUX_DATA(A24_EA24_MARK, PORT70_FN1),
+        PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2),
+        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3),
+        PINMUX_DATA(A25_EA25_MARK, PORT71_FN1),
+        PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2),
+        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3),
+        PINMUX_DATA(A26_MARK, PORT72_FN1),
+        PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2),
+        PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1),
+        PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1),
+        PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1),
+        PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1),
+        PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1),
+        PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1),
+        PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1),
+        PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1),
+        PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1),
+        PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1),
+        PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1),
+        PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1),
+        PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1),
+        PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1),
+        PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1),
+        PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1),
+        PINMUX_DATA(CS4_MARK, PORT90_FN1),
+        PINMUX_DATA(CS5A_MARK, PORT91_FN1),
+        PINMUX_DATA(FMSICK_MARK, PORT91_FN2),
+        PINMUX_DATA(CS5B_MARK, PORT92_FN1),
+        PINMUX_DATA(FCE1_MARK, PORT92_FN2),
+
+        /* 55-3 (FN) */
+        PINMUX_DATA(CS6B_MARK, PORT93_FN1),
+        PINMUX_DATA(XCS2_MARK, PORT93_FN2),
+        PINMUX_DATA(CS6A_MARK, PORT93_FN3),
+        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+        PINMUX_DATA(FCE0_MARK, PORT94_FN1),
+        PINMUX_DATA(WAIT_MARK, PORT95_FN1),
+        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+        PINMUX_DATA(RD_XRD_MARK, PORT96_FN1),
+        PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1),
+        PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1),
+        PINMUX_DATA(FRB_MARK, PORT99_FN1),
+        PINMUX_DATA(CKO_MARK, PORT100_FN1),
+        PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1),
+        PINMUX_DATA(NBRST_MARK, PORT102_FN1),
+        PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1),
+        PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1),
+        PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1),
+        PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1),
+        PINMUX_DATA(TCKON_MARK, PORT118_FN1),
+        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1),
+        PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2),
+        PINMUX_DATA(IPORT0_MARK, PORT128_FN3),
+        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1),
+        PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2),
+        PINMUX_DATA(IPORT1_MARK, PORT129_FN3),
+        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1),
+        PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2),
+        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3),
+        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1),
+        PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2),
+        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3),
+        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1),
+        PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2),
+        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3),
+        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1),
+        PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2),
+        PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3),
+        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1),
+        PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2),
+        PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3),
+        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1),
+        PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2),
+        PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3),
+        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1),
+        PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2),
+        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1),
+        PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2),
+        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1),
+        PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2),
+        PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3),
+        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1),
+        PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2),
+        PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3),
+        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1),
+        PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2),
+        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3),
+        PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4),
+        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1),
+        PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2),
+        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3),
+        PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4),
+        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1),
+        PINMUX_DATA(M13_BSW_MARK, PORT142_FN2),
+        PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3),
+        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1),
+        PINMUX_DATA(M14_GSW_MARK, PORT143_FN2),
+        PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3),
+        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1),
+        PINMUX_DATA(M15_RSW_MARK, PORT144_FN2),
+        PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3),
+        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1),
+        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2),
+        PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3),
+        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1),
+        PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2),
+        PINMUX_DATA(IPORT2_MARK, PORT146_FN3),
+        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1),
+        PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2),
+        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+        PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2),
+        PINMUX_DATA(A27_MARK, PORT149_FN1),
+        PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2),
+        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3),
+        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1),
+        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1),
+        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2),
+        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1),
+        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2),
+        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1),
+        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2),
+        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3),
+        PINMUX_DATA(SOUT3_MARK, PORT154_FN1),
+        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2),
+        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3),
+        PINMUX_DATA(SIN3_MARK, PORT155_FN1),
+        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2),
+        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3),
+        PINMUX_DATA(XRTS3_MARK, PORT156_FN1),
+        PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2),
+        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3),
+        PINMUX_DATA(XCTS3_MARK, PORT157_FN1),
+        PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2),
+        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3),
+
+        /* 55-4 (FN) */
+        PINMUX_DATA(DINT_MARK, PORT158_FN1),
+        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2),
+        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3),
+        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1),
+        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2),
+        PINMUX_DATA(NMI_MARK, PORT159_FN3),
+        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1),
+        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2),
+        PINMUX_DATA(SOUT0_MARK, PORT160_FN3),
+        PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1),
+        PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2),
+        PINMUX_DATA(XCTS0_MARK, PORT161_FN3),
+        PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4),
+        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1),
+        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2),
+        PINMUX_DATA(SIN0_MARK, PORT162_FN3),
+        PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4),
+        PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1),
+        PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2),
+        PINMUX_DATA(XRTS0_MARK, PORT163_FN3),
+        PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4),
+        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+        PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2),
+        PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3),
+        PINMUX_DATA(LCDD1_MARK, PORT193_FN1),
+        PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2),
+        PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3),
+        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4),
+        PINMUX_DATA(LCDD2_MARK, PORT194_FN1),
+        PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2),
+        PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3),
+        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4),
+        PINMUX_DATA(LCDD3_MARK, PORT195_FN1),
+        PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2),
+        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3),
+        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4),
+        PINMUX_DATA(LCDD4_MARK, PORT196_FN1),
+        PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2),
+        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3),
+        PINMUX_DATA(LCDD5_MARK, PORT197_FN1),
+        PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2),
+        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3),
+        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4),
+        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+        PINMUX_DATA(LCDD7_MARK, PORT199_FN1),
+        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2),
+        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3),
+        PINMUX_DATA(LCDD8_MARK, PORT200_FN1),
+        PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2),
+        PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3),
+        PINMUX_DATA(D16_MARK, PORT200_FN4),
+        PINMUX_DATA(LCDD9_MARK, PORT201_FN1),
+        PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2),
+        PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3),
+        PINMUX_DATA(D17_MARK, PORT201_FN4),
+        PINMUX_DATA(LCDD10_MARK, PORT202_FN1),
+        PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2),
+        PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3),
+        PINMUX_DATA(D18_MARK, PORT202_FN4),
+        PINMUX_DATA(LCDD11_MARK, PORT203_FN1),
+        PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2),
+        PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3),
+        PINMUX_DATA(D19_MARK, PORT203_FN4),
+        PINMUX_DATA(LCDD12_MARK, PORT204_FN1),
+        PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2),
+        PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3),
+        PINMUX_DATA(D20_MARK, PORT204_FN4),
+        PINMUX_DATA(LCDD13_MARK, PORT205_FN1),
+        PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2),
+        PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3),
+        PINMUX_DATA(D21_MARK, PORT205_FN4),
+        PINMUX_DATA(LCDD14_MARK, PORT206_FN1),
+        PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2),
+        PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3),
+        PINMUX_DATA(D22_MARK, PORT206_FN4),
+        PINMUX_DATA(LCDD15_MARK, PORT207_FN1),
+        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2),
+        PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3),
+        PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4),
+        PINMUX_DATA(D23_MARK, PORT207_FN5),
+        PINMUX_DATA(LCDD16_MARK, PORT208_FN1),
+        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2),
+        PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3),
+        PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4),
+        PINMUX_DATA(D24_MARK, PORT208_FN5),
+        PINMUX_DATA(LCDD17_MARK, PORT209_FN1),
+        PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2),
+        PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3),
+        PINMUX_DATA(D25_MARK, PORT209_FN4),
+        PINMUX_DATA(LCDD18_MARK, PORT210_FN1),
+        PINMUX_DATA(DREQ2_MARK, PORT210_FN2),
+        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3),
+        PINMUX_DATA(D26_MARK, PORT210_FN4),
+        PINMUX_DATA(LCDD19_MARK, PORT211_FN1),
+        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2),
+        PINMUX_DATA(D27_MARK, PORT211_FN3),
+        PINMUX_DATA(LCDD20_MARK, PORT212_FN1),
+        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2),
+        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3),
+        PINMUX_DATA(D28_MARK, PORT212_FN4),
+        PINMUX_DATA(LCDD21_MARK, PORT213_FN1),
+        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2),
+        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3),
+        PINMUX_DATA(D29_MARK, PORT213_FN4),
+        PINMUX_DATA(LCDD22_MARK, PORT214_FN1),
+        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2),
+        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3),
+        PINMUX_DATA(D30_MARK, PORT214_FN4),
+        PINMUX_DATA(LCDD23_MARK, PORT215_FN1),
+        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2),
+        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3),
+        PINMUX_DATA(D31_MARK, PORT215_FN4),
+        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1),
+        PINMUX_DATA(LCDWR_MARK, PORT216_FN2),
+        PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3),
+        PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4),
+        PINMUX_DATA(LCDRD_MARK, PORT217_FN1),
+        PINMUX_DATA(DACK2_MARK, PORT217_FN2),
+        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3),
+        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1),
+        PINMUX_DATA(LCDCS_MARK, PORT218_FN2),
+        PINMUX_DATA(LCDCS2_MARK, PORT218_FN3),
+        PINMUX_DATA(DACK3_MARK, PORT218_FN4),
+        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+        PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6),
+        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1),
+        PINMUX_DATA(LCDRS_MARK, PORT219_FN2),
+        PINMUX_DATA(DREQ3_MARK, PORT219_FN3),
+        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4),
+        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1),
+        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+        PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3),
+        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1),
+        PINMUX_DATA(DREQ1_MARK, PORT221_FN2),
+        PINMUX_DATA(PWEN_MARK, PORT221_FN3),
+        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4),
+        PINMUX_DATA(LCDDON_MARK, PORT222_FN1),
+        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2),
+        PINMUX_DATA(DACK1_MARK, PORT222_FN3),
+        PINMUX_DATA(OVCN_MARK, PORT222_FN4),
+        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5),
+        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1),
+        PINMUX_DATA(OVCN2_MARK, PORT225_FN2),
+        PINMUX_DATA(EXTLP_MARK, PORT226_FN1),
+        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2),
+        PINMUX_DATA(USBTERM_MARK, PORT226_FN3),
+        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4),
+        PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1),
+        PINMUX_DATA(IDIN_MARK, PORT227_FN2),
+        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1),
+        PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1),
+        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2),
+        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1),
+        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2),
+        PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1),
+        PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2),
+        PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3),
+        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1),
+        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2),
+        PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3),
+        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1),
+        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2),
+        PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3),
+        PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4),
+        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1),
+        PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2),
+        PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1),
+        PINMUX_DATA(OPORT0_MARK, PORT235_FN2),
+        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3),
+        PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4),
+        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1),
+        PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2),
+        PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3),
+        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1),
+        PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2),
+        PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3),
+        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1),
+        PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2),
+
+        /* 55-5 (FN) */
+        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1),
+        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1),
+        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2),
+        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3),
+        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1),
+        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2),
+        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1),
+        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+        PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1),
+        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2),
+        PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3),
+        PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1),
+        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2),
+        PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3),
+        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1),
+        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2),
+        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3),
+        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1),
+        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2),
+        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3),
+        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1),
+        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2),
+        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3),
+        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4),
+        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1),
+        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2),
+        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+        PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2),
+        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+        PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2),
+        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+        PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2),
+        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+        PINMUX_DATA(TDI2_MARK, PORT254_FN2),
+        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+        PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2),
+        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+        PINMUX_DATA(TRST2_MARK, PORT256_FN2),
+        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+        PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2),
+        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+        PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2),
+        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1),
+        PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2),
+        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+        PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4),
+        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1),
+        PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2),
+        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+        PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4),
+        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1),
+        PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2),
+        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+        PINMUX_DATA(TDI3_MARK, PORT261_FN4),
+        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1),
+        PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2),
+        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+        PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4),
+        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+        PINMUX_DATA(TRST3_MARK, PORT263_FN2),
+        PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
+};
+
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define GPIO_PORT_265() _265(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* 55-1 -> 55-5 (GPIO) */
+        GPIO_PORT_265(),
+
+        /* Special Pull-up / Pull-down Functions */
+        GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
+        GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU),
+        GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU),
+        GPIO_FN(PORT72_KEYIN6_PU),
+
+        /* 55-1 (FN) */
+        GPIO_FN(VBUS_0),
+        GPIO_FN(CPORT0),
+        GPIO_FN(CPORT1),
+        GPIO_FN(CPORT2),
+        GPIO_FN(CPORT3),
+        GPIO_FN(CPORT4),
+        GPIO_FN(CPORT5),
+        GPIO_FN(CPORT6),
+        GPIO_FN(CPORT7),
+        GPIO_FN(CPORT8),
+        GPIO_FN(CPORT9),
+        GPIO_FN(CPORT10),
+        GPIO_FN(CPORT11), GPIO_FN(SIN2),
+        GPIO_FN(CPORT12), GPIO_FN(XCTS2),
+        GPIO_FN(CPORT13), GPIO_FN(RFSPO4),
+        GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
+        GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2),
+        GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3),
+        GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2),
+        GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2),
+        GPIO_FN(CPORT19_MPORT1),
+        GPIO_FN(CPORT20), GPIO_FN(RFSPO6),
+        GPIO_FN(CPORT21), GPIO_FN(STATUS0),
+        GPIO_FN(CPORT22), GPIO_FN(STATUS1),
+        GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
+        GPIO_FN(B_SYNLD1),
+        GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK),
+        GPIO_FN(XMAINPS),
+        GPIO_FN(XDIVPS),
+        GPIO_FN(XIDRST),
+        GPIO_FN(IDCLK), GPIO_FN(IC_DP),
+        GPIO_FN(IDIO), GPIO_FN(IC_DM),
+        GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT),
+        GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
+        GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
+        GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
+        GPIO_FN(PCMCLKO),
+        GPIO_FN(SYNC8KO),
+
+        /* 55-2 (FN) */
+        GPIO_FN(DNPCM_A),
+        GPIO_FN(UPPCM_A),
+        GPIO_FN(VACK),
+        GPIO_FN(XTALB1L),
+        GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
+        GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
+        GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS),
+        GPIO_FN(GPS_IM),
+        GPIO_FN(GPS_IS),
+        GPIO_FN(GPS_QM),
+        GPIO_FN(GPS_QS),
+        GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT),
+        GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2),
+        GPIO_FN(IPORT3), GPIO_FN(FMSIOLR),
+        GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3),
+        GPIO_FN(OPORT1), GPIO_FN(FMSIOBT),
+        GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2),
+        GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3),
+        GPIO_FN(OPORT3), GPIO_FN(FMSIILR),
+        GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2),
+        GPIO_FN(FMSIIBT),
+        GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0),
+        GPIO_FN(A0_EA0), GPIO_FN(BS),
+        GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2),
+        GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2),
+        GPIO_FN(TPU0TO1),
+        GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5),
+        GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4),
+        GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1),
+        GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC),
+        GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK),
+        GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD),
+        GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK),
+        GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC),
+        GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0),
+        GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1),
+        GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2),
+        GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6),
+        GPIO_FN(D0_ED0_NAF0),
+        GPIO_FN(D1_ED1_NAF1),
+        GPIO_FN(D2_ED2_NAF2),
+        GPIO_FN(D3_ED3_NAF3),
+        GPIO_FN(D4_ED4_NAF4),
+        GPIO_FN(D5_ED5_NAF5),
+        GPIO_FN(D6_ED6_NAF6),
+        GPIO_FN(D7_ED7_NAF7),
+        GPIO_FN(D8_ED8_NAF8),
+        GPIO_FN(D9_ED9_NAF9),
+        GPIO_FN(D10_ED10_NAF10),
+        GPIO_FN(D11_ED11_NAF11),
+        GPIO_FN(D12_ED12_NAF12),
+        GPIO_FN(D13_ED13_NAF13),
+        GPIO_FN(D14_ED14_NAF14),
+        GPIO_FN(D15_ED15_NAF15),
+        GPIO_FN(CS4),
+        GPIO_FN(CS5A), GPIO_FN(FMSICK),
+
+        /* 55-3 (FN) */
+        GPIO_FN(CS5B), GPIO_FN(FCE1),
+        GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0),
+        GPIO_FN(FCE0),
+        GPIO_FN(WAIT), GPIO_FN(DREQ0),
+        GPIO_FN(RD_XRD),
+        GPIO_FN(WE0_XWR0_FWE),
+        GPIO_FN(WE1_XWR1),
+        GPIO_FN(FRB),
+        GPIO_FN(CKO),
+        GPIO_FN(NBRSTOUT),
+        GPIO_FN(NBRST),
+        GPIO_FN(GPS_EPPSIN),
+        GPIO_FN(LATCHPULSE),
+        GPIO_FN(LTESIGNAL),
+        GPIO_FN(LEGACYSTATE),
+        GPIO_FN(TCKON),
+        GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0),
+        GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1),
+        GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD),
+        GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1),
+        GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2),
+        GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5),
+        GPIO_FN(PORT133_MSIOF2_TSYNC),
+        GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD),
+        GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK),
+        GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2),
+        GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3),
+        GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC),
+        GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR),
+        GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2),
+        GPIO_FN(PORT140_FSIAOBT),
+        GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3),
+        GPIO_FN(PORT141_FSIAOSLD),
+        GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK),
+        GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR),
+        GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT),
+        GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD),
+        GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2),
+        GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5),
+        GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6),
+        GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1),
+        GPIO_FN(MFG0_IN2),
+        GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK),
+        GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC),
+        GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1),
+        GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0),
+        GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1),
+        GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2),
+        GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD),
+
+        /* 55-4 (FN) */
+        GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
+        GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI),
+        GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0),
+        GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0),
+        GPIO_FN(MFG3_IN2),
+        GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0),
+        GPIO_FN(MFG3_IN1),
+        GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0),
+        GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0),
+        GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI),
+        GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS),
+        GPIO_FN(BBIF2_TSYNC1),
+        GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS),
+        GPIO_FN(BBIF2_TSCK1),
+        GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD),
+        GPIO_FN(BBIF2_TXD1),
+        GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD),
+        GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK),
+        GPIO_FN(MFG2_OUT2),
+        GPIO_FN(LCDD6),
+        GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2),
+        GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0),
+        GPIO_FN(D16),
+        GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1),
+        GPIO_FN(D17),
+        GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2),
+        GPIO_FN(D18),
+        GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3),
+        GPIO_FN(D19),
+        GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4),
+        GPIO_FN(D20),
+        GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5),
+        GPIO_FN(D21),
+        GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6),
+        GPIO_FN(D22),
+        GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0),
+        GPIO_FN(VIO_DR7), GPIO_FN(D23),
+        GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1),
+        GPIO_FN(VIO_VDR), GPIO_FN(D24),
+        GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR),
+        GPIO_FN(D25),
+        GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1),
+        GPIO_FN(D26),
+        GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27),
+        GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
+        GPIO_FN(D28),
+        GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
+        GPIO_FN(D29),
+        GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK),
+        GPIO_FN(D30),
+        GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC),
+        GPIO_FN(D31),
+        GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3),
+        GPIO_FN(VIO_CLKR),
+        GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC),
+        GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
+        GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4),
+        GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK),
+        GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5),
+        GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD),
+        GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN),
+        GPIO_FN(MSIOF0L_TXD),
+        GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2),
+        GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM),
+        GPIO_FN(PORT226_VIO_CKO2),
+        GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN),
+        GPIO_FN(SCIFA1_RXD),
+        GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1),
+        GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC),
+        GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR),
+        GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT),
+        GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG),
+        GPIO_FN(PORT233_FSIACK),
+        GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD),
+        GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2),
+        GPIO_FN(PORT235_FSIAILR),
+        GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT),
+        GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD),
+        GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
+
+        /* 55-5 (FN) */
+        GPIO_FN(MSIOF1_SS2),
+        GPIO_FN(SCIFA6_TXD),
+        GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1),
+        GPIO_FN(TPU4TO0),
+        GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2),
+        GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2),
+        GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1),
+        GPIO_FN(PORT244_SCIFB_CTS),
+        GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2),
+        GPIO_FN(PORT245_SCIFB_RTS),
+        GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1),
+        GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0),
+        GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2),
+        GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1),
+        GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1),
+        GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0),
+        GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1),
+        GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0),
+        GPIO_FN(SDHICD0),
+        GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0),
+        GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0),
+        GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
+        GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0),
+        GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
+        GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
+        GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1),
+        GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2),
+        GPIO_FN(TMS3_SWDIO_MC1),
+        GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2),
+        GPIO_FN(TDO3_SWO0_MC1),
+        GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2),
+        GPIO_FN(TDI3),
+        GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2),
+        GPIO_FN(RTCK3_SWO1_MC1),
+        GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
+        GPIO_FN(RESETOUTS),
+};
+
+/* helper for top 4 bits in PORTnCR */
+#define PCRH(in, in_pd, in_pu, out)     \
+        0, (out), (in), 0,      \
+                0, 0, 0, 0,     \
+                0, 0, (in_pd), 0,       \
+                0, 0, (in_pu), 0
+
+#define PORTCR(nr, reg) \
+        { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {   \
+                        PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,   \
+                                 PORT##nr##_IN_PU, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1, \
+                                PORT##nr##_FN2, PORT##nr##_FN3, \
+                                PORT##nr##_FN4, PORT##nr##_FN5, \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        PORTCR(0, 0xe6050000), /* PORT0CR */
+        PORTCR(1, 0xe6050001), /* PORT1CR */
+        PORTCR(2, 0xe6050002), /* PORT2CR */
+        PORTCR(3, 0xe6050003), /* PORT3CR */
+        PORTCR(4, 0xe6050004), /* PORT4CR */
+        PORTCR(5, 0xe6050005), /* PORT5CR */
+        PORTCR(6, 0xe6050006), /* PORT6CR */
+        PORTCR(7, 0xe6050007), /* PORT7CR */
+        PORTCR(8, 0xe6050008), /* PORT8CR */
+        PORTCR(9, 0xe6050009), /* PORT9CR */
+
+        PORTCR(10, 0xe605000a), /* PORT10CR */
+        PORTCR(11, 0xe605000b), /* PORT11CR */
+        PORTCR(12, 0xe605000c), /* PORT12CR */
+        PORTCR(13, 0xe605000d), /* PORT13CR */
+        PORTCR(14, 0xe605000e), /* PORT14CR */
+        PORTCR(15, 0xe605000f), /* PORT15CR */
+        PORTCR(16, 0xe6050010), /* PORT16CR */
+        PORTCR(17, 0xe6050011), /* PORT17CR */
+        PORTCR(18, 0xe6050012), /* PORT18CR */
+        PORTCR(19, 0xe6050013), /* PORT19CR */
+
+        PORTCR(20, 0xe6050014), /* PORT20CR */
+        PORTCR(21, 0xe6050015), /* PORT21CR */
+        PORTCR(22, 0xe6050016), /* PORT22CR */
+        PORTCR(23, 0xe6050017), /* PORT23CR */
+        PORTCR(24, 0xe6050018), /* PORT24CR */
+        PORTCR(25, 0xe6050019), /* PORT25CR */
+        PORTCR(26, 0xe605001a), /* PORT26CR */
+        PORTCR(27, 0xe605001b), /* PORT27CR */
+        PORTCR(28, 0xe605001c), /* PORT28CR */
+        PORTCR(29, 0xe605001d), /* PORT29CR */
+
+        PORTCR(30, 0xe605001e), /* PORT30CR */
+        PORTCR(31, 0xe605001f), /* PORT31CR */
+        PORTCR(32, 0xe6050020), /* PORT32CR */
+        PORTCR(33, 0xe6050021), /* PORT33CR */
+        PORTCR(34, 0xe6050022), /* PORT34CR */
+        PORTCR(35, 0xe6050023), /* PORT35CR */
+        PORTCR(36, 0xe6050024), /* PORT36CR */
+        PORTCR(37, 0xe6050025), /* PORT37CR */
+        PORTCR(38, 0xe6050026), /* PORT38CR */
+        PORTCR(39, 0xe6050027), /* PORT39CR */
+
+        PORTCR(40, 0xe6050028), /* PORT40CR */
+        PORTCR(41, 0xe6050029), /* PORT41CR */
+        PORTCR(42, 0xe605002a), /* PORT42CR */
+        PORTCR(43, 0xe605002b), /* PORT43CR */
+        PORTCR(44, 0xe605002c), /* PORT44CR */
+        PORTCR(45, 0xe605002d), /* PORT45CR */
+        PORTCR(46, 0xe605002e), /* PORT46CR */
+        PORTCR(47, 0xe605002f), /* PORT47CR */
+        PORTCR(48, 0xe6050030), /* PORT48CR */
+        PORTCR(49, 0xe6050031), /* PORT49CR */
+
+        PORTCR(50, 0xe6050032), /* PORT50CR */
+        PORTCR(51, 0xe6050033), /* PORT51CR */
+        PORTCR(52, 0xe6050034), /* PORT52CR */
+        PORTCR(53, 0xe6050035), /* PORT53CR */
+        PORTCR(54, 0xe6050036), /* PORT54CR */
+        PORTCR(55, 0xe6050037), /* PORT55CR */
+        PORTCR(56, 0xe6050038), /* PORT56CR */
+        PORTCR(57, 0xe6050039), /* PORT57CR */
+        PORTCR(58, 0xe605003a), /* PORT58CR */
+        PORTCR(59, 0xe605003b), /* PORT59CR */
+
+        PORTCR(60, 0xe605003c), /* PORT60CR */
+        PORTCR(61, 0xe605003d), /* PORT61CR */
+        PORTCR(62, 0xe605003e), /* PORT62CR */
+        PORTCR(63, 0xe605003f), /* PORT63CR */
+        PORTCR(64, 0xe6050040), /* PORT64CR */
+        PORTCR(65, 0xe6050041), /* PORT65CR */
+        PORTCR(66, 0xe6050042), /* PORT66CR */
+        PORTCR(67, 0xe6050043), /* PORT67CR */
+        PORTCR(68, 0xe6050044), /* PORT68CR */
+        PORTCR(69, 0xe6050045), /* PORT69CR */
+
+        PORTCR(70, 0xe6050046), /* PORT70CR */
+        PORTCR(71, 0xe6050047), /* PORT71CR */
+        PORTCR(72, 0xe6050048), /* PORT72CR */
+        PORTCR(73, 0xe6050049), /* PORT73CR */
+        PORTCR(74, 0xe605004a), /* PORT74CR */
+        PORTCR(75, 0xe605004b), /* PORT75CR */
+        PORTCR(76, 0xe605004c), /* PORT76CR */
+        PORTCR(77, 0xe605004d), /* PORT77CR */
+        PORTCR(78, 0xe605004e), /* PORT78CR */
+        PORTCR(79, 0xe605004f), /* PORT79CR */
+
+        PORTCR(80, 0xe6050050), /* PORT80CR */
+        PORTCR(81, 0xe6050051), /* PORT81CR */
+        PORTCR(82, 0xe6050052), /* PORT82CR */
+        PORTCR(83, 0xe6050053), /* PORT83CR */
+        PORTCR(84, 0xe6050054), /* PORT84CR */
+        PORTCR(85, 0xe6050055), /* PORT85CR */
+        PORTCR(86, 0xe6050056), /* PORT86CR */
+        PORTCR(87, 0xe6050057), /* PORT87CR */
+        PORTCR(88, 0xe6050058), /* PORT88CR */
+        PORTCR(89, 0xe6050059), /* PORT89CR */
+
+        PORTCR(90, 0xe605005a), /* PORT90CR */
+        PORTCR(91, 0xe605005b), /* PORT91CR */
+        PORTCR(92, 0xe605005c), /* PORT92CR */
+        PORTCR(93, 0xe605005d), /* PORT93CR */
+        PORTCR(94, 0xe605005e), /* PORT94CR */
+        PORTCR(95, 0xe605005f), /* PORT95CR */
+        PORTCR(96, 0xe6050060), /* PORT96CR */
+        PORTCR(97, 0xe6050061), /* PORT97CR */
+        PORTCR(98, 0xe6050062), /* PORT98CR */
+        PORTCR(99, 0xe6050063), /* PORT99CR */
+
+        PORTCR(100, 0xe6050064), /* PORT100CR */
+        PORTCR(101, 0xe6050065), /* PORT101CR */
+        PORTCR(102, 0xe6050066), /* PORT102CR */
+        PORTCR(103, 0xe6050067), /* PORT103CR */
+        PORTCR(104, 0xe6050068), /* PORT104CR */
+        PORTCR(105, 0xe6050069), /* PORT105CR */
+        PORTCR(106, 0xe605006a), /* PORT106CR */
+        PORTCR(107, 0xe605006b), /* PORT107CR */
+        PORTCR(108, 0xe605006c), /* PORT108CR */
+        PORTCR(109, 0xe605006d), /* PORT109CR */
+
+        PORTCR(110, 0xe605006e), /* PORT110CR */
+        PORTCR(111, 0xe605006f), /* PORT111CR */
+        PORTCR(112, 0xe6050070), /* PORT112CR */
+        PORTCR(113, 0xe6050071), /* PORT113CR */
+        PORTCR(114, 0xe6050072), /* PORT114CR */
+        PORTCR(115, 0xe6050073), /* PORT115CR */
+        PORTCR(116, 0xe6050074), /* PORT116CR */
+        PORTCR(117, 0xe6050075), /* PORT117CR */
+        PORTCR(118, 0xe6050076), /* PORT118CR */
+
+        PORTCR(128, 0xe6051080), /* PORT128CR */
+        PORTCR(129, 0xe6051081), /* PORT129CR */
+
+        PORTCR(130, 0xe6051082), /* PORT130CR */
+        PORTCR(131, 0xe6051083), /* PORT131CR */
+        PORTCR(132, 0xe6051084), /* PORT132CR */
+        PORTCR(133, 0xe6051085), /* PORT133CR */
+        PORTCR(134, 0xe6051086), /* PORT134CR */
+        PORTCR(135, 0xe6051087), /* PORT135CR */
+        PORTCR(136, 0xe6051088), /* PORT136CR */
+        PORTCR(137, 0xe6051089), /* PORT137CR */
+        PORTCR(138, 0xe605108a), /* PORT138CR */
+        PORTCR(139, 0xe605108b), /* PORT139CR */
+
+        PORTCR(140, 0xe605108c), /* PORT140CR */
+        PORTCR(141, 0xe605108d), /* PORT141CR */
+        PORTCR(142, 0xe605108e), /* PORT142CR */
+        PORTCR(143, 0xe605108f), /* PORT143CR */
+        PORTCR(144, 0xe6051090), /* PORT144CR */
+        PORTCR(145, 0xe6051091), /* PORT145CR */
+        PORTCR(146, 0xe6051092), /* PORT146CR */
+        PORTCR(147, 0xe6051093), /* PORT147CR */
+        PORTCR(148, 0xe6051094), /* PORT148CR */
+        PORTCR(149, 0xe6051095), /* PORT149CR */
+
+        PORTCR(150, 0xe6051096), /* PORT150CR */
+        PORTCR(151, 0xe6051097), /* PORT151CR */
+        PORTCR(152, 0xe6051098), /* PORT152CR */
+        PORTCR(153, 0xe6051099), /* PORT153CR */
+        PORTCR(154, 0xe605109a), /* PORT154CR */
+        PORTCR(155, 0xe605109b), /* PORT155CR */
+        PORTCR(156, 0xe605109c), /* PORT156CR */
+        PORTCR(157, 0xe605109d), /* PORT157CR */
+        PORTCR(158, 0xe605109e), /* PORT158CR */
+        PORTCR(159, 0xe605109f), /* PORT159CR */
+
+        PORTCR(160, 0xe60510a0), /* PORT160CR */
+        PORTCR(161, 0xe60510a1), /* PORT161CR */
+        PORTCR(162, 0xe60510a2), /* PORT162CR */
+        PORTCR(163, 0xe60510a3), /* PORT163CR */
+        PORTCR(164, 0xe60510a4), /* PORT164CR */
+
+        PORTCR(192, 0xe60520c0), /* PORT192CR */
+        PORTCR(193, 0xe60520c1), /* PORT193CR */
+        PORTCR(194, 0xe60520c2), /* PORT194CR */
+        PORTCR(195, 0xe60520c3), /* PORT195CR */
+        PORTCR(196, 0xe60520c4), /* PORT196CR */
+        PORTCR(197, 0xe60520c5), /* PORT197CR */
+        PORTCR(198, 0xe60520c6), /* PORT198CR */
+        PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+        PORTCR(200, 0xe60520c8), /* PORT200CR */
+        PORTCR(201, 0xe60520c9), /* PORT201CR */
+        PORTCR(202, 0xe60520ca), /* PORT202CR */
+        PORTCR(203, 0xe60520cb), /* PORT203CR */
+        PORTCR(204, 0xe60520cc), /* PORT204CR */
+        PORTCR(205, 0xe60520cd), /* PORT205CR */
+        PORTCR(206, 0xe60520ce), /* PORT206CR */
+        PORTCR(207, 0xe60520cf), /* PORT207CR */
+        PORTCR(208, 0xe60520d0), /* PORT208CR */
+        PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+        PORTCR(210, 0xe60520d2), /* PORT210CR */
+        PORTCR(211, 0xe60520d3), /* PORT211CR */
+        PORTCR(212, 0xe60520d4), /* PORT212CR */
+        PORTCR(213, 0xe60520d5), /* PORT213CR */
+        PORTCR(214, 0xe60520d6), /* PORT214CR */
+        PORTCR(215, 0xe60520d7), /* PORT215CR */
+        PORTCR(216, 0xe60520d8), /* PORT216CR */
+        PORTCR(217, 0xe60520d9), /* PORT217CR */
+        PORTCR(218, 0xe60520da), /* PORT218CR */
+        PORTCR(219, 0xe60520db), /* PORT219CR */
+
+        PORTCR(220, 0xe60520dc), /* PORT220CR */
+        PORTCR(221, 0xe60520dd), /* PORT221CR */
+        PORTCR(222, 0xe60520de), /* PORT222CR */
+        PORTCR(223, 0xe60520df), /* PORT223CR */
+        PORTCR(224, 0xe60520e0), /* PORT224CR */
+        PORTCR(225, 0xe60520e1), /* PORT225CR */
+        PORTCR(226, 0xe60520e2), /* PORT226CR */
+        PORTCR(227, 0xe60520e3), /* PORT227CR */
+        PORTCR(228, 0xe60520e4), /* PORT228CR */
+        PORTCR(229, 0xe60520e5), /* PORT229CR */
+
+        PORTCR(230, 0xe60520e6), /* PORT230CR */
+        PORTCR(231, 0xe60520e7), /* PORT231CR */
+        PORTCR(232, 0xe60520e8), /* PORT232CR */
+        PORTCR(233, 0xe60520e9), /* PORT233CR */
+        PORTCR(234, 0xe60520ea), /* PORT234CR */
+        PORTCR(235, 0xe60520eb), /* PORT235CR */
+        PORTCR(236, 0xe60520ec), /* PORT236CR */
+        PORTCR(237, 0xe60520ed), /* PORT237CR */
+        PORTCR(238, 0xe60520ee), /* PORT238CR */
+        PORTCR(239, 0xe60520ef), /* PORT239CR */
+
+        PORTCR(240, 0xe60520f0), /* PORT240CR */
+        PORTCR(241, 0xe60520f1), /* PORT241CR */
+        PORTCR(242, 0xe60520f2), /* PORT242CR */
+        PORTCR(243, 0xe60520f3), /* PORT243CR */
+        PORTCR(244, 0xe60520f4), /* PORT244CR */
+        PORTCR(245, 0xe60520f5), /* PORT245CR */
+        PORTCR(246, 0xe60520f6), /* PORT246CR */
+        PORTCR(247, 0xe60520f7), /* PORT247CR */
+        PORTCR(248, 0xe60520f8), /* PORT248CR */
+        PORTCR(249, 0xe60520f9), /* PORT249CR */
+
+        PORTCR(250, 0xe60520fa), /* PORT250CR */
+        PORTCR(251, 0xe60520fb), /* PORT251CR */
+        PORTCR(252, 0xe60520fc), /* PORT252CR */
+        PORTCR(253, 0xe60520fd), /* PORT253CR */
+        PORTCR(254, 0xe60520fe), /* PORT254CR */
+        PORTCR(255, 0xe60520ff), /* PORT255CR */
+        PORTCR(256, 0xe6052100), /* PORT256CR */
+        PORTCR(257, 0xe6052101), /* PORT257CR */
+        PORTCR(258, 0xe6052102), /* PORT258CR */
+        PORTCR(259, 0xe6052103), /* PORT259CR */
+
+        PORTCR(260, 0xe6052104), /* PORT260CR */
+        PORTCR(261, 0xe6052105), /* PORT261CR */
+        PORTCR(262, 0xe6052106), /* PORT262CR */
+        PORTCR(263, 0xe6052107), /* PORT263CR */
+        PORTCR(264, 0xe6052108), /* PORT264CR */
+
+        { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                        MSELBCR_MSEL17_0, MSELBCR_MSEL17_1,
+                        MSELBCR_MSEL16_0, MSELBCR_MSEL16_1,
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+        },
+        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
+                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+        },
+        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
+                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) {
+                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, PORT164_DATA,
+                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) {
+                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) {
+                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, PORT264_DATA,
+                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7377_pinmux_info = {
+        .name = "sh7377_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PORT0,
+        .last_gpio = GPIO_FN_RESETOUTS,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void sh7377_pinmux_init(void)
+{
+        register_pinmux(&sh7377_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
new file mode 100644
index 000000000000..3eed44eb98b4
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -0,0 +1,2746 @@
+/*
+ * sh73a0 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Copyright (C) 2010 NISHIMOTO Hiroki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/sh73a0.h>
+
+#define _1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define _10(fn, pfx, sfx)                               \
+        _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx),       \
+        _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx),       \
+        _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx),       \
+        _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx),       \
+        _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
+
+#define _310(fn, pfx, sfx)                              \
+        _10(fn, pfx,    sfx), _10(fn, pfx##1, sfx),     \
+        _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx),     \
+        _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx),     \
+        _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx),     \
+        _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx),     \
+        _10(fn, pfx##10, sfx),                          \
+        _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx),   \
+        _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx),   \
+        _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx),   \
+        _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx),   \
+        _1(fn, pfx##118, sfx),                          \
+        _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx),   \
+        _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx),   \
+        _10(fn, pfx##15, sfx),                          \
+        _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx),   \
+        _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx),   \
+        _1(fn, pfx##164, sfx),                          \
+        _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx),   \
+        _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx),   \
+        _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx),   \
+        _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx),   \
+        _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx),   \
+        _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx),   \
+        _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx),   \
+        _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx),   \
+        _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx),   \
+        _1(fn, pfx##282, sfx),                          \
+        _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx),   \
+        _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
+
+#define _PORT(pfx, sfx) pfx##_##sfx
+#define PORT_310(str) _310(_PORT, PORT, str)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PORT_310(DATA),                 /* PORT0_DATA -> PORT309_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PORT_310(IN),                   /* PORT0_IN -> PORT309_IN */
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PORT_310(IN_PU),                /* PORT0_IN_PU -> PORT309_IN_PU */
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PORT_310(IN_PD),                /* PORT0_IN_PD -> PORT309_IN_PD */
+        PINMUX_INPUT_PULLDOWN_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PORT_310(OUT),                  /* PORT0_OUT -> PORT309_OUT */
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PORT_310(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
+        PORT_310(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
+        PORT_310(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
+        PORT_310(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
+        PORT_310(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
+        PORT_310(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
+        PORT_310(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
+        PORT_310(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
+        PORT_310(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
+        PORT_310(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
+
+        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* Hardware manual Table 25-1 (Function 0-7) */
+        VBUS_0_MARK,
+        GPI0_MARK,
+        GPI1_MARK,
+        GPI2_MARK,
+        GPI3_MARK,
+        GPI4_MARK,
+        GPI5_MARK,
+        GPI6_MARK,
+        GPI7_MARK,
+        SCIFA7_RXD_MARK,
+        SCIFA7_CTS__MARK,
+        GPO7_MARK, MFG0_OUT2_MARK,
+        GPO6_MARK, MFG1_OUT2_MARK,
+        GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
+        SCIFA0_TXD_MARK,
+        SCIFA7_TXD_MARK,
+        SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
+        GPO0_MARK,
+        GPO1_MARK,
+        GPO2_MARK, STATUS0_MARK,
+        GPO3_MARK, STATUS1_MARK,
+        GPO4_MARK, STATUS2_MARK,
+        VINT_MARK,
+        TCKON_MARK,
+        XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
+        MFG0_OUT1_MARK, PORT27_IROUT_MARK,
+        XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
+        PORT28_TPU1TO1_MARK,
+        SIM_RST_MARK, PORT29_TPU1TO1_MARK,
+        SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
+        SIM_D_MARK, PORT31_IROUT_MARK,
+        SCIFA4_TXD_MARK,
+        SCIFA4_RXD_MARK, XWUP_MARK,
+        SCIFA4_RTS__MARK,
+        SCIFA4_CTS__MARK,
+        FSIBOBT_MARK, FSIBIBT_MARK,
+        FSIBOLR_MARK, FSIBILR_MARK,
+        FSIBOSLD_MARK,
+        FSIBISLD_MARK,
+        VACK_MARK,
+        XTAL1L_MARK,
+        SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
+        SCIFA0_RXD_MARK,
+        SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
+        FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
+        FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
+        FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
+        FSICISLD_MARK, FSIDISLD_MARK,
+        FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
+        FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
+
+        FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
+        FSIAOSLD_MARK, BBIF2_TXD2_MARK,
+        FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
+        PORT53_FSICSPDIF_MARK,
+        FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
+        FSICCK_MARK, FSICOMC_MARK,
+        FSIAISLD_MARK, TPU0TO0_MARK,
+        A0_MARK, BS__MARK,
+        A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
+        A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
+        A14_MARK, KEYOUT5_MARK,
+        A15_MARK, KEYOUT4_MARK,
+        A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
+        A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+        A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+        A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
+        A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
+        A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+        A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
+        A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
+        A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
+        A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
+        A26_MARK, KEYIN6_MARK,
+        KEYIN7_MARK,
+        D0_NAF0_MARK,
+        D1_NAF1_MARK,
+        D2_NAF2_MARK,
+        D3_NAF3_MARK,
+        D4_NAF4_MARK,
+        D5_NAF5_MARK,
+        D6_NAF6_MARK,
+        D7_NAF7_MARK,
+        D8_NAF8_MARK,
+        D9_NAF9_MARK,
+        D10_NAF10_MARK,
+        D11_NAF11_MARK,
+        D12_NAF12_MARK,
+        D13_NAF13_MARK,
+        D14_NAF14_MARK,
+        D15_NAF15_MARK,
+        CS4__MARK,
+        CS5A__MARK, PORT91_RDWR_MARK,
+        CS5B__MARK, FCE1__MARK,
+        CS6B__MARK, DACK0_MARK,
+        FCE0__MARK, CS6A__MARK,
+        WAIT__MARK, DREQ0_MARK,
+        RD__FSC_MARK,
+        WE0__FWE_MARK, RDWR_FWE_MARK,
+        WE1__MARK,
+        FRB_MARK,
+        CKO_MARK,
+        NBRSTOUT__MARK,
+        NBRST__MARK,
+        BBIF2_TXD_MARK,
+        BBIF2_RXD_MARK,
+        BBIF2_SYNC_MARK,
+        BBIF2_SCK_MARK,
+        SCIFA3_CTS__MARK, MFG3_IN2_MARK,
+        SCIFA3_RXD_MARK, MFG3_IN1_MARK,
+        BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
+        SCIFA3_TXD_MARK,
+        HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
+        HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
+        HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
+        HSI_TX_READY_MARK, BBIF1_TXD_MARK,
+        HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
+        PORT115_I2C_SCL3_MARK,
+        HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
+        PORT116_I2C_SDA3_MARK,
+        HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
+        HSI_TX_FLAG_MARK,
+        VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
+
+        VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
+        VIO2_HD_MARK, LCD2D1_MARK,
+        VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
+        VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
+        PORT131_KEYOUT11_MARK, LCD2D11_MARK,
+        VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
+        PORT132_KEYOUT10_MARK, LCD2D12_MARK,
+        VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
+        VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
+        VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
+        VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
+        VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
+        VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
+        VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
+        VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
+        VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
+        VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
+        VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
+        VIO2_D5_MARK, LCD2D3_MARK,
+        VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
+        VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
+        PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
+        VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
+        LCD2D18_MARK,
+        VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
+        VIO_CKO_MARK,
+        A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
+        MFG0_IN2_MARK,
+        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+        SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+        SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+        SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
+        SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
+        DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
+        PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
+        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
+        PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
+        LCDD0_MARK,
+        LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
+        LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
+        LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
+        LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
+        LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
+        LCDD6_MARK,
+        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
+        LCDD8_MARK, D16_MARK,
+        LCDD9_MARK, D17_MARK,
+        LCDD10_MARK, D18_MARK,
+        LCDD11_MARK, D19_MARK,
+        LCDD12_MARK, D20_MARK,
+        LCDD13_MARK, D21_MARK,
+        LCDD14_MARK, D22_MARK,
+        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
+        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
+        LCDD17_MARK, D25_MARK,
+        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
+        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
+        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
+        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
+        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
+        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
+        LCDDCK_MARK, LCDWR__MARK,
+        LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
+        VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
+        LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
+        PORT218_VIO_CKOR_MARK,
+        LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
+        MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
+        LCDVSYN_MARK, LCDVSYN2_MARK,
+        LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
+        MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
+        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
+        VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
+
+        SCIFA1_TXD_MARK, OVCN2_MARK,
+        EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
+        SCIFA1_RTS__MARK, IDIN_MARK,
+        SCIFA1_RXD_MARK,
+        SCIFA1_CTS__MARK, MFG1_IN1_MARK,
+        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
+        MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
+        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
+        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
+        MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
+        MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
+        MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
+        MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
+        MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
+        MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
+        SCIFA6_TXD_MARK,
+        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
+        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+        PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
+        MSIOF2R_RXD_MARK,
+        PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
+        MSIOF2R_TXD_MARK,
+        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
+        TPU1TO0_MARK,
+        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
+        TPU3TO1_MARK,
+        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
+        TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
+        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
+        MSIOF2R_TSYNC_MARK,
+        SDHICLK0_MARK,
+        SDHICD0_MARK,
+        SDHID0_0_MARK,
+        SDHID0_1_MARK,
+        SDHID0_2_MARK,
+        SDHID0_3_MARK,
+        SDHICMD0_MARK,
+        SDHIWP0_MARK,
+        SDHICLK1_MARK,
+        SDHID1_0_MARK, TS_SPSYNC2_MARK,
+        SDHID1_1_MARK, TS_SDAT2_MARK,
+        SDHID1_2_MARK, TS_SDEN2_MARK,
+        SDHID1_3_MARK, TS_SCK2_MARK,
+        SDHICMD1_MARK,
+        SDHICLK2_MARK,
+        SDHID2_0_MARK, TS_SPSYNC4_MARK,
+        SDHID2_1_MARK, TS_SDAT4_MARK,
+        SDHID2_2_MARK, TS_SDEN4_MARK,
+        SDHID2_3_MARK, TS_SCK4_MARK,
+        SDHICMD2_MARK,
+        MMCCLK0_MARK,
+        MMCD0_0_MARK,
+        MMCD0_1_MARK,
+        MMCD0_2_MARK,
+        MMCD0_3_MARK,
+        MMCD0_4_MARK, TS_SPSYNC5_MARK,
+        MMCD0_5_MARK, TS_SDAT5_MARK,
+        MMCD0_6_MARK, TS_SDEN5_MARK,
+        MMCD0_7_MARK, TS_SCK5_MARK,
+        MMCCMD0_MARK,
+        RESETOUTS__MARK, EXTAL2OUT_MARK,
+        MCP_WAIT__MCP_FRB_MARK,
+        MCP_CKO_MARK, MMCCLK1_MARK,
+        MCP_D15_MCP_NAF15_MARK,
+        MCP_D14_MCP_NAF14_MARK,
+        MCP_D13_MCP_NAF13_MARK,
+        MCP_D12_MCP_NAF12_MARK,
+        MCP_D11_MCP_NAF11_MARK,
+        MCP_D10_MCP_NAF10_MARK,
+        MCP_D9_MCP_NAF9_MARK,
+        MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
+        MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
+
+        MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
+        MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
+        MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
+        MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
+        MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
+        MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
+        MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
+        MCP_NBRSTOUT__MARK,
+        MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
+
+        /* MSEL2 special cases */
+        TSIF2_TS_XX1_MARK,
+        TSIF2_TS_XX2_MARK,
+        TSIF2_TS_XX3_MARK,
+        TSIF2_TS_XX4_MARK,
+        TSIF2_TS_XX5_MARK,
+        TSIF1_TS_XX1_MARK,
+        TSIF1_TS_XX2_MARK,
+        TSIF1_TS_XX3_MARK,
+        TSIF1_TS_XX4_MARK,
+        TSIF1_TS_XX5_MARK,
+        TSIF0_TS_XX1_MARK,
+        TSIF0_TS_XX2_MARK,
+        TSIF0_TS_XX3_MARK,
+        TSIF0_TS_XX4_MARK,
+        TSIF0_TS_XX5_MARK,
+        MST1_TS_XX1_MARK,
+        MST1_TS_XX2_MARK,
+        MST1_TS_XX3_MARK,
+        MST1_TS_XX4_MARK,
+        MST1_TS_XX5_MARK,
+        MST0_TS_XX1_MARK,
+        MST0_TS_XX2_MARK,
+        MST0_TS_XX3_MARK,
+        MST0_TS_XX4_MARK,
+        MST0_TS_XX5_MARK,
+
+        /* MSEL3 special cases */
+        SDHI0_VCCQ_MC0_ON_MARK,
+        SDHI0_VCCQ_MC0_OFF_MARK,
+        DEBUG_MON_VIO_MARK,
+        DEBUG_MON_LCDD_MARK,
+        LCDC_LCDC0_MARK,
+        LCDC_LCDC1_MARK,
+
+        /* MSEL4 special cases */
+        IRQ9_MEM_INT_MARK,
+        IRQ9_MCP_INT_MARK,
+        A11_MARK,
+        KEYOUT8_MARK,
+        TPU4TO3_MARK,
+        RESETA_N_PU_ON_MARK,
+        RESETA_N_PU_OFF_MARK,
+        EDBGREQ_PD_MARK,
+        EDBGREQ_PU_MARK,
+
+        /* Functions with pull-ups */
+        KEYIN0_PU_MARK,
+        KEYIN1_PU_MARK,
+        KEYIN2_PU_MARK,
+        KEYIN3_PU_MARK,
+        KEYIN4_PU_MARK,
+        KEYIN5_PU_MARK,
+        KEYIN6_PU_MARK,
+        KEYIN7_PU_MARK,
+        SDHID1_0_PU_MARK,
+        SDHID1_1_PU_MARK,
+        SDHID1_2_PU_MARK,
+        SDHID1_3_PU_MARK,
+        SDHICMD1_PU_MARK,
+        MMCCMD0_PU_MARK,
+        MMCCMD1_PU_MARK,
+        FSIACK_PU_MARK,
+        FSIAILR_PU_MARK,
+        FSIAIBT_PU_MARK,
+        FSIAISLD_PU_MARK,
+
+        PINMUX_MARK_END,
+};
+
+#define PORT_DATA_I(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr)      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr)      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr)   \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PD,        \
+                                PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr)        \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr)     \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr)     \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr)  \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+static pinmux_enum_t pinmux_data[] = {
+        /* specify valid pin states for each pin in GPIO mode */
+
+        /* Table 25-1 (I/O and Pull U/D) */
+        PORT_DATA_I_PD(0),
+        PORT_DATA_I_PU(1),
+        PORT_DATA_I_PU(2),
+        PORT_DATA_I_PU(3),
+        PORT_DATA_I_PU(4),
+        PORT_DATA_I_PU(5),
+        PORT_DATA_I_PU(6),
+        PORT_DATA_I_PU(7),
+        PORT_DATA_I_PU(8),
+        PORT_DATA_I_PD(9),
+        PORT_DATA_I_PD(10),
+        PORT_DATA_I_PU_PD(11),
+        PORT_DATA_IO_PU_PD(12),
+        PORT_DATA_IO_PU_PD(13),
+        PORT_DATA_IO_PU_PD(14),
+        PORT_DATA_IO_PU_PD(15),
+        PORT_DATA_IO_PD(16),
+        PORT_DATA_IO_PD(17),
+        PORT_DATA_IO_PU(18),
+        PORT_DATA_IO_PU(19),
+        PORT_DATA_O(20),
+        PORT_DATA_O(21),
+        PORT_DATA_O(22),
+        PORT_DATA_O(23),
+        PORT_DATA_O(24),
+        PORT_DATA_I_PD(25),
+        PORT_DATA_I_PD(26),
+        PORT_DATA_IO_PU(27),
+        PORT_DATA_IO_PU(28),
+        PORT_DATA_IO_PD(29),
+        PORT_DATA_IO_PD(30),
+        PORT_DATA_IO_PU(31),
+        PORT_DATA_IO_PD(32),
+        PORT_DATA_I_PU_PD(33),
+        PORT_DATA_IO_PD(34),
+        PORT_DATA_I_PU_PD(35),
+        PORT_DATA_IO_PD(36),
+        PORT_DATA_IO(37),
+        PORT_DATA_O(38),
+        PORT_DATA_I_PU(39),
+        PORT_DATA_I_PU_PD(40),
+        PORT_DATA_O(41),
+        PORT_DATA_IO_PD(42),
+        PORT_DATA_IO_PU_PD(43),
+        PORT_DATA_IO_PU_PD(44),
+        PORT_DATA_IO_PD(45),
+        PORT_DATA_IO_PD(46),
+        PORT_DATA_IO_PD(47),
+        PORT_DATA_I_PD(48),
+        PORT_DATA_IO_PU_PD(49),
+        PORT_DATA_IO_PD(50),
+
+        PORT_DATA_IO_PD(51),
+        PORT_DATA_O(52),
+        PORT_DATA_IO_PU_PD(53),
+        PORT_DATA_IO_PU_PD(54),
+        PORT_DATA_IO_PD(55),
+        PORT_DATA_I_PU_PD(56),
+        PORT_DATA_IO(57),
+        PORT_DATA_IO(58),
+        PORT_DATA_IO(59),
+        PORT_DATA_IO(60),
+        PORT_DATA_IO(61),
+        PORT_DATA_IO_PD(62),
+        PORT_DATA_IO_PD(63),
+        PORT_DATA_IO_PU_PD(64),
+        PORT_DATA_IO_PD(65),
+        PORT_DATA_IO_PU_PD(66),
+        PORT_DATA_IO_PU_PD(67),
+        PORT_DATA_IO_PU_PD(68),
+        PORT_DATA_IO_PU_PD(69),
+        PORT_DATA_IO_PU_PD(70),
+        PORT_DATA_IO_PU_PD(71),
+        PORT_DATA_IO_PU_PD(72),
+        PORT_DATA_I_PU_PD(73),
+        PORT_DATA_IO_PU(74),
+        PORT_DATA_IO_PU(75),
+        PORT_DATA_IO_PU(76),
+        PORT_DATA_IO_PU(77),
+        PORT_DATA_IO_PU(78),
+        PORT_DATA_IO_PU(79),
+        PORT_DATA_IO_PU(80),
+        PORT_DATA_IO_PU(81),
+        PORT_DATA_IO_PU(82),
+        PORT_DATA_IO_PU(83),
+        PORT_DATA_IO_PU(84),
+        PORT_DATA_IO_PU(85),
+        PORT_DATA_IO_PU(86),
+        PORT_DATA_IO_PU(87),
+        PORT_DATA_IO_PU(88),
+        PORT_DATA_IO_PU(89),
+        PORT_DATA_O(90),
+        PORT_DATA_IO_PU(91),
+        PORT_DATA_O(92),
+        PORT_DATA_IO_PU(93),
+        PORT_DATA_O(94),
+        PORT_DATA_I_PU_PD(95),
+        PORT_DATA_IO(96),
+        PORT_DATA_IO(97),
+        PORT_DATA_IO(98),
+        PORT_DATA_I_PU(99),
+        PORT_DATA_O(100),
+        PORT_DATA_O(101),
+        PORT_DATA_I_PU(102),
+        PORT_DATA_IO_PD(103),
+        PORT_DATA_I_PU_PD(104),
+        PORT_DATA_I_PD(105),
+        PORT_DATA_I_PD(106),
+        PORT_DATA_I_PU_PD(107),
+        PORT_DATA_I_PU_PD(108),
+        PORT_DATA_IO_PD(109),
+        PORT_DATA_IO_PD(110),
+        PORT_DATA_IO_PU_PD(111),
+        PORT_DATA_IO_PU_PD(112),
+        PORT_DATA_IO_PU_PD(113),
+        PORT_DATA_IO_PD(114),
+        PORT_DATA_IO_PU(115),
+        PORT_DATA_IO_PU(116),
+        PORT_DATA_IO_PU_PD(117),
+        PORT_DATA_IO_PU_PD(118),
+        PORT_DATA_IO_PD(128),
+
+        PORT_DATA_IO_PD(129),
+        PORT_DATA_IO_PU_PD(130),
+        PORT_DATA_IO_PD(131),
+        PORT_DATA_IO_PD(132),
+        PORT_DATA_IO_PD(133),
+        PORT_DATA_IO_PU_PD(134),
+        PORT_DATA_IO_PU_PD(135),
+        PORT_DATA_IO_PU_PD(136),
+        PORT_DATA_IO_PU_PD(137),
+        PORT_DATA_IO_PD(138),
+        PORT_DATA_IO_PD(139),
+        PORT_DATA_IO_PD(140),
+        PORT_DATA_IO_PD(141),
+        PORT_DATA_IO_PD(142),
+        PORT_DATA_IO_PD(143),
+        PORT_DATA_IO_PU_PD(144),
+        PORT_DATA_IO_PD(145),
+        PORT_DATA_IO_PU_PD(146),
+        PORT_DATA_IO_PU_PD(147),
+        PORT_DATA_IO_PU_PD(148),
+        PORT_DATA_IO_PU_PD(149),
+        PORT_DATA_I_PU_PD(150),
+        PORT_DATA_IO_PU_PD(151),
+        PORT_DATA_IO_PU_PD(152),
+        PORT_DATA_IO_PD(153),
+        PORT_DATA_IO_PD(154),
+        PORT_DATA_I_PU_PD(155),
+        PORT_DATA_IO_PU_PD(156),
+        PORT_DATA_I_PD(157),
+        PORT_DATA_IO_PD(158),
+        PORT_DATA_IO_PU_PD(159),
+        PORT_DATA_IO_PU_PD(160),
+        PORT_DATA_I_PU_PD(161),
+        PORT_DATA_I_PU_PD(162),
+        PORT_DATA_IO_PU_PD(163),
+        PORT_DATA_I_PU_PD(164),
+        PORT_DATA_IO_PD(192),
+        PORT_DATA_IO_PU_PD(193),
+        PORT_DATA_IO_PD(194),
+        PORT_DATA_IO_PU_PD(195),
+        PORT_DATA_IO_PD(196),
+        PORT_DATA_IO_PD(197),
+        PORT_DATA_IO_PD(198),
+        PORT_DATA_IO_PD(199),
+        PORT_DATA_IO_PU_PD(200),
+        PORT_DATA_IO_PU_PD(201),
+        PORT_DATA_IO_PU_PD(202),
+        PORT_DATA_IO_PU_PD(203),
+        PORT_DATA_IO_PU_PD(204),
+        PORT_DATA_IO_PU_PD(205),
+        PORT_DATA_IO_PU_PD(206),
+        PORT_DATA_IO_PD(207),
+        PORT_DATA_IO_PD(208),
+        PORT_DATA_IO_PD(209),
+        PORT_DATA_IO_PD(210),
+        PORT_DATA_IO_PD(211),
+        PORT_DATA_IO_PD(212),
+        PORT_DATA_IO_PD(213),
+        PORT_DATA_IO_PU_PD(214),
+        PORT_DATA_IO_PU_PD(215),
+        PORT_DATA_IO_PD(216),
+        PORT_DATA_IO_PD(217),
+        PORT_DATA_O(218),
+        PORT_DATA_IO_PD(219),
+        PORT_DATA_IO_PD(220),
+        PORT_DATA_IO_PU_PD(221),
+        PORT_DATA_IO_PU_PD(222),
+        PORT_DATA_I_PU_PD(223),
+        PORT_DATA_I_PU_PD(224),
+
+        PORT_DATA_IO_PU_PD(225),
+        PORT_DATA_O(226),
+        PORT_DATA_IO_PU_PD(227),
+        PORT_DATA_I_PU_PD(228),
+        PORT_DATA_I_PD(229),
+        PORT_DATA_IO(230),
+        PORT_DATA_IO_PU_PD(231),
+        PORT_DATA_IO_PU_PD(232),
+        PORT_DATA_I_PU_PD(233),
+        PORT_DATA_IO_PU_PD(234),
+        PORT_DATA_IO_PU_PD(235),
+        PORT_DATA_IO_PU_PD(236),
+        PORT_DATA_IO_PD(237),
+        PORT_DATA_IO_PU_PD(238),
+        PORT_DATA_IO_PU_PD(239),
+        PORT_DATA_IO_PU_PD(240),
+        PORT_DATA_O(241),
+        PORT_DATA_I_PD(242),
+        PORT_DATA_IO_PU_PD(243),
+        PORT_DATA_IO_PU_PD(244),
+        PORT_DATA_IO_PU_PD(245),
+        PORT_DATA_IO_PU_PD(246),
+        PORT_DATA_IO_PU_PD(247),
+        PORT_DATA_IO_PU_PD(248),
+        PORT_DATA_IO_PU_PD(249),
+        PORT_DATA_IO_PU_PD(250),
+        PORT_DATA_IO_PU_PD(251),
+        PORT_DATA_IO_PU_PD(252),
+        PORT_DATA_IO_PU_PD(253),
+        PORT_DATA_IO_PU_PD(254),
+        PORT_DATA_IO_PU_PD(255),
+        PORT_DATA_IO_PU_PD(256),
+        PORT_DATA_IO_PU_PD(257),
+        PORT_DATA_IO_PU_PD(258),
+        PORT_DATA_IO_PU_PD(259),
+        PORT_DATA_IO_PU_PD(260),
+        PORT_DATA_IO_PU_PD(261),
+        PORT_DATA_IO_PU_PD(262),
+        PORT_DATA_IO_PU_PD(263),
+        PORT_DATA_IO_PU_PD(264),
+        PORT_DATA_IO_PU_PD(265),
+        PORT_DATA_IO_PU_PD(266),
+        PORT_DATA_IO_PU_PD(267),
+        PORT_DATA_IO_PU_PD(268),
+        PORT_DATA_IO_PU_PD(269),
+        PORT_DATA_IO_PU_PD(270),
+        PORT_DATA_IO_PU_PD(271),
+        PORT_DATA_IO_PU_PD(272),
+        PORT_DATA_IO_PU_PD(273),
+        PORT_DATA_IO_PU_PD(274),
+        PORT_DATA_IO_PU_PD(275),
+        PORT_DATA_IO_PU_PD(276),
+        PORT_DATA_IO_PU_PD(277),
+        PORT_DATA_IO_PU_PD(278),
+        PORT_DATA_IO_PU_PD(279),
+        PORT_DATA_IO_PU_PD(280),
+        PORT_DATA_O(281),
+        PORT_DATA_O(282),
+        PORT_DATA_I_PU(288),
+        PORT_DATA_IO_PU_PD(289),
+        PORT_DATA_IO_PU_PD(290),
+        PORT_DATA_IO_PU_PD(291),
+        PORT_DATA_IO_PU_PD(292),
+        PORT_DATA_IO_PU_PD(293),
+        PORT_DATA_IO_PU_PD(294),
+        PORT_DATA_IO_PU_PD(295),
+        PORT_DATA_IO_PU_PD(296),
+        PORT_DATA_IO_PU_PD(297),
+        PORT_DATA_IO_PU_PD(298),
+
+        PORT_DATA_IO_PU_PD(299),
+        PORT_DATA_IO_PU_PD(300),
+        PORT_DATA_IO_PU_PD(301),
+        PORT_DATA_IO_PU_PD(302),
+        PORT_DATA_IO_PU_PD(303),
+        PORT_DATA_IO_PU_PD(304),
+        PORT_DATA_IO_PU_PD(305),
+        PORT_DATA_O(306),
+        PORT_DATA_O(307),
+        PORT_DATA_I_PU(308),
+        PORT_DATA_O(309),
+
+        /* Table 25-1 (Function 0-7) */
+        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+        PINMUX_DATA(GPI0_MARK, PORT1_FN1),
+        PINMUX_DATA(GPI1_MARK, PORT2_FN1),
+        PINMUX_DATA(GPI2_MARK, PORT3_FN1),
+        PINMUX_DATA(GPI3_MARK, PORT4_FN1),
+        PINMUX_DATA(GPI4_MARK, PORT5_FN1),
+        PINMUX_DATA(GPI5_MARK, PORT6_FN1),
+        PINMUX_DATA(GPI6_MARK, PORT7_FN1),
+        PINMUX_DATA(GPI7_MARK, PORT8_FN1),
+        PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
+        PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
+        PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
+        PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
+        PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
+        PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
+        PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
+        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
+        PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
+        PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
+        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+        PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
+        PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
+        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+        PINMUX_DATA(GPO0_MARK, PORT20_FN1),
+        PINMUX_DATA(GPO1_MARK, PORT21_FN1),
+        PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
+        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+        PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
+        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+        PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
+        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+        PINMUX_DATA(VINT_MARK, PORT25_FN1),
+        PINMUX_DATA(TCKON_MARK, PORT26_FN1),
+        PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
+        PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_1), \
+        PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
+        PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
+        PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
+        PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_1), \
+        PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
+        PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
+        PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
+        PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
+        PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
+        PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
+        PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
+        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
+        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+        PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
+        PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
+        PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
+        PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
+        PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
+        PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
+        PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
+        PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
+        PINMUX_DATA(VACK_MARK, PORT40_FN1),
+        PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
+        PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
+        PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
+        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+        PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
+        PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
+        PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
+        PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
+        PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
+        PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
+        PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
+        PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
+        PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
+        PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
+        PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
+        PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
+        PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
+        PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
+        PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
+        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
+        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
+        PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
+        PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
+        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
+        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
+        PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
+
+        PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
+        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
+        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
+        PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
+        PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
+        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+        PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
+        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
+        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
+        PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
+        PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
+        PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
+        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
+        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
+        PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
+        PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
+        PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
+        PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
+        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+        PINMUX_DATA(A0_MARK, PORT57_FN1), \
+        PINMUX_DATA(BS__MARK, PORT57_FN2),
+        PINMUX_DATA(A12_MARK, PORT58_FN1), \
+        PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
+        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
+        PINMUX_DATA(A13_MARK, PORT59_FN1), \
+        PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
+        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+        PINMUX_DATA(A14_MARK, PORT60_FN1), \
+        PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
+        PINMUX_DATA(A15_MARK, PORT61_FN1), \
+        PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
+        PINMUX_DATA(A16_MARK, PORT62_FN1), \
+        PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
+        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A17_MARK, PORT63_FN1), \
+        PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
+        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A18_MARK, PORT64_FN1), \
+        PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
+        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A19_MARK, PORT65_FN1), \
+        PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
+        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A20_MARK, PORT66_FN1), \
+        PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
+        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A21_MARK, PORT67_FN1), \
+        PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
+        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A22_MARK, PORT68_FN1), \
+        PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
+        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A23_MARK, PORT69_FN1), \
+        PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
+        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A24_MARK, PORT70_FN1), \
+        PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
+        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A25_MARK, PORT71_FN1), \
+        PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
+        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A26_MARK, PORT72_FN1), \
+        PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
+        PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
+        PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
+        PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
+        PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
+        PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
+        PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
+        PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
+        PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
+        PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
+        PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
+        PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
+        PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
+        PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
+        PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
+        PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
+        PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
+        PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
+        PINMUX_DATA(CS4__MARK, PORT90_FN1),
+        PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
+        PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
+        PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
+        PINMUX_DATA(FCE1__MARK, PORT92_FN2),
+        PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
+        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+        PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
+        PINMUX_DATA(CS6A__MARK, PORT94_FN2),
+        PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
+        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+        PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
+        PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
+        PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
+        PINMUX_DATA(WE1__MARK, PORT98_FN1),
+        PINMUX_DATA(FRB_MARK, PORT99_FN1),
+        PINMUX_DATA(CKO_MARK, PORT100_FN1),
+        PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
+        PINMUX_DATA(NBRST__MARK, PORT102_FN1),
+        PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
+        PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
+        PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
+        PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
+        PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
+        PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
+        PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
+        PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
+        PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
+        PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
+        PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
+        PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
+        PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
+        PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
+        PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
+        PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
+        PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
+        PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
+        PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
+        PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
+        PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
+        PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
+        PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
+        PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
+        PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
+        PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
+        PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
+        PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
+        PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
+        PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
+        PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
+        PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
+        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
+        PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
+        PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
+
+        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
+        PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
+        PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
+        PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
+        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
+        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
+                MSEL4CR_MSEL10_1), \
+        PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
+        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
+        PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
+        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
+        PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
+        PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
+        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
+        PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
+        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
+        PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
+        PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
+        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
+        PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
+        PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
+        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
+        PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
+        PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
+        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
+        PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
+        PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
+        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
+        PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
+        PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
+        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
+        PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
+        PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
+        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
+        PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
+        PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
+        PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
+        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
+        PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
+        PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
+        PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
+        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
+        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
+        PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
+        PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
+        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
+        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
+        PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
+        PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
+        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
+        PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
+        PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
+        PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
+        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
+        PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
+        PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
+        PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
+        PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
+        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
+        PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
+        PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
+        PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
+        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
+        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
+        PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
+        PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
+        PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
+        PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
+        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
+        PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
+        PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
+        PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
+        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
+        PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
+        PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
+        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+        PINMUX_DATA(A27_MARK, PORT149_FN1), \
+        PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
+        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
+        PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
+        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
+        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
+        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
+        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
+        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
+        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
+        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
+        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
+        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
+        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
+        PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
+        PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
+                MSEL4CR_MSEL10_0),
+        PINMUX_DATA(DINT__MARK, PORT158_FN1), \
+        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
+        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
+        PINMUX_DATA(NMI_MARK, PORT159_FN3),
+        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
+        PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
+        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
+        PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
+        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+        PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
+        PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
+        PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
+        PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
+        PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
+        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
+        PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
+        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1),
+        PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
+        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
+        PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
+        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+        PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
+        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
+        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
+        PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
+        PINMUX_DATA(D16_MARK, PORT200_FN6),
+        PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
+        PINMUX_DATA(D17_MARK, PORT201_FN6),
+        PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
+        PINMUX_DATA(D18_MARK, PORT202_FN6),
+        PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
+        PINMUX_DATA(D19_MARK, PORT203_FN6),
+        PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
+        PINMUX_DATA(D20_MARK, PORT204_FN6),
+        PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
+        PINMUX_DATA(D21_MARK, PORT205_FN6),
+        PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
+        PINMUX_DATA(D22_MARK, PORT206_FN6),
+        PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
+        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D23_MARK, PORT207_FN6),
+        PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
+        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D24_MARK, PORT208_FN6),
+        PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
+        PINMUX_DATA(D25_MARK, PORT209_FN6),
+        PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
+        PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
+        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D26_MARK, PORT210_FN6),
+        PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
+        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D27_MARK, PORT211_FN6),
+        PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
+        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
+        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D28_MARK, PORT212_FN6),
+        PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
+        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
+        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D29_MARK, PORT213_FN6),
+        PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
+        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
+        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D30_MARK, PORT214_FN6),
+        PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
+        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
+        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D31_MARK, PORT215_FN6),
+        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
+        PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
+        PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
+        PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
+        PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
+        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
+        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
+        PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
+        PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
+        PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
+        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
+        PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
+        PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
+        PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
+        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
+        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
+        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
+        PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
+        PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
+        PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
+        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
+        PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
+        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
+        PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
+        PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
+        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
+
+        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
+        PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
+        PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
+        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
+        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
+        PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
+        PINMUX_DATA(IDIN_MARK, PORT227_FN4),
+        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
+        PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
+        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
+        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
+        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
+        PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
+        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
+        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
+        PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
+        PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
+        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
+        PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
+        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
+        PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_0),
+        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
+        PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_0),
+        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
+        PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
+        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
+        PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
+        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
+        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
+        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
+        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
+        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
+        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
+        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+        PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
+        PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
+        PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
+        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
+        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
+        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
+        PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
+        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
+        PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
+        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
+        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
+        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
+        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+        PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
+        PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
+        PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
+        PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
+        PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
+        PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
+        PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
+        PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
+        PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
+        PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
+        PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
+        PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
+        PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
+        PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
+        PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
+        PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
+        PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
+        PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
+        PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
+        PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
+        PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
+        PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
+        PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
+        PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
+        PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
+        PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
+        PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
+        PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
+
+        PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
+        PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
+        PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
+        PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
+        PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
+        PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
+        PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
+        PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
+        PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
+        PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
+
+        /* MSEL2 special cases */
+        PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+                MSEL2CR_MSEL12_0),
+        PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+                MSEL2CR_MSEL12_1),
+        PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+                MSEL2CR_MSEL12_0),
+        PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+                MSEL2CR_MSEL12_1),
+        PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
+                MSEL2CR_MSEL12_0),
+        PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+                MSEL2CR_MSEL9_0),
+        PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+                MSEL2CR_MSEL9_1),
+        PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+                MSEL2CR_MSEL9_0),
+        PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+                MSEL2CR_MSEL9_1),
+        PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
+                MSEL2CR_MSEL9_0),
+        PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+                MSEL2CR_MSEL6_0),
+        PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+                MSEL2CR_MSEL6_1),
+        PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+                MSEL2CR_MSEL6_0),
+        PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+                MSEL2CR_MSEL6_1),
+        PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
+                MSEL2CR_MSEL6_0),
+        PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+                MSEL2CR_MSEL3_0),
+        PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+                MSEL2CR_MSEL3_1),
+        PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+                MSEL2CR_MSEL3_0),
+        PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+                MSEL2CR_MSEL3_1),
+        PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
+                MSEL2CR_MSEL3_0),
+        PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+                MSEL2CR_MSEL0_0),
+        PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+                MSEL2CR_MSEL0_1),
+        PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+                MSEL2CR_MSEL0_0),
+        PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+                MSEL2CR_MSEL0_1),
+        PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
+                MSEL2CR_MSEL0_0),
+
+        /* MSEL3 special cases */
+        PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
+        PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
+        PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
+        PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
+        PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
+        PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
+
+        /* MSEL4 special cases */
+        PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
+        PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
+        PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
+        PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
+        PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
+        PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
+        PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
+        PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
+        PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+
+        /* Functions with pull-ups */
+        PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
+        PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
+        PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
+        PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
+        PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
+        PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
+        PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
+        PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
+
+        PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1),
+        PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1),
+        PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1),
+        PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1),
+        PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1),
+
+        PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
+                MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU,
+                MSEL4CR_MSEL15_1),
+        PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
+        PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
+        PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
+        PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
+};
+
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        GPIO_PORT_310(),
+
+        /* Table 25-1 (Functions 0-7) */
+        GPIO_FN(VBUS_0),
+        GPIO_FN(GPI0),
+        GPIO_FN(GPI1),
+        GPIO_FN(GPI2),
+        GPIO_FN(GPI3),
+        GPIO_FN(GPI4),
+        GPIO_FN(GPI5),
+        GPIO_FN(GPI6),
+        GPIO_FN(GPI7),
+        GPIO_FN(SCIFA7_RXD),
+        GPIO_FN(SCIFA7_CTS_),
+        GPIO_FN(GPO7), \
+        GPIO_FN(MFG0_OUT2),
+        GPIO_FN(GPO6), \
+        GPIO_FN(MFG1_OUT2),
+        GPIO_FN(GPO5), \
+        GPIO_FN(SCIFA0_SCK), \
+        GPIO_FN(FSICOSLDT3), \
+        GPIO_FN(PORT16_VIO_CKOR),
+        GPIO_FN(SCIFA0_TXD),
+        GPIO_FN(SCIFA7_TXD),
+        GPIO_FN(SCIFA7_RTS_), \
+        GPIO_FN(PORT19_VIO_CKO2),
+        GPIO_FN(GPO0),
+        GPIO_FN(GPO1),
+        GPIO_FN(GPO2), \
+        GPIO_FN(STATUS0),
+        GPIO_FN(GPO3), \
+        GPIO_FN(STATUS1),
+        GPIO_FN(GPO4), \
+        GPIO_FN(STATUS2),
+        GPIO_FN(VINT),
+        GPIO_FN(TCKON),
+        GPIO_FN(XDVFS1), \
+        GPIO_FN(PORT27_I2C_SCL2), \
+        GPIO_FN(PORT27_I2C_SCL3), \
+        GPIO_FN(MFG0_OUT1), \
+        GPIO_FN(PORT27_IROUT),
+        GPIO_FN(XDVFS2), \
+        GPIO_FN(PORT28_I2C_SDA2), \
+        GPIO_FN(PORT28_I2C_SDA3), \
+        GPIO_FN(PORT28_TPU1TO1),
+        GPIO_FN(SIM_RST), \
+        GPIO_FN(PORT29_TPU1TO1),
+        GPIO_FN(SIM_CLK), \
+        GPIO_FN(PORT30_VIO_CKOR),
+        GPIO_FN(SIM_D), \
+        GPIO_FN(PORT31_IROUT),
+        GPIO_FN(SCIFA4_TXD),
+        GPIO_FN(SCIFA4_RXD), \
+        GPIO_FN(XWUP),
+        GPIO_FN(SCIFA4_RTS_),
+        GPIO_FN(SCIFA4_CTS_),
+        GPIO_FN(FSIBOBT), \
+        GPIO_FN(FSIBIBT),
+        GPIO_FN(FSIBOLR), \
+        GPIO_FN(FSIBILR),
+        GPIO_FN(FSIBOSLD),
+        GPIO_FN(FSIBISLD),
+        GPIO_FN(VACK),
+        GPIO_FN(XTAL1L),
+        GPIO_FN(SCIFA0_RTS_), \
+        GPIO_FN(FSICOSLDT2),
+        GPIO_FN(SCIFA0_RXD),
+        GPIO_FN(SCIFA0_CTS_), \
+        GPIO_FN(FSICOSLDT1),
+        GPIO_FN(FSICOBT), \
+        GPIO_FN(FSICIBT), \
+        GPIO_FN(FSIDOBT), \
+        GPIO_FN(FSIDIBT),
+        GPIO_FN(FSICOLR), \
+        GPIO_FN(FSICILR), \
+        GPIO_FN(FSIDOLR), \
+        GPIO_FN(FSIDILR),
+        GPIO_FN(FSICOSLD), \
+        GPIO_FN(PORT47_FSICSPDIF),
+        GPIO_FN(FSICISLD), \
+        GPIO_FN(FSIDISLD),
+        GPIO_FN(FSIACK), \
+        GPIO_FN(PORT49_IRDA_OUT), \
+        GPIO_FN(PORT49_IROUT), \
+        GPIO_FN(FSIAOMC),
+        GPIO_FN(FSIAOLR), \
+        GPIO_FN(BBIF2_TSYNC2), \
+        GPIO_FN(TPU2TO2), \
+        GPIO_FN(FSIAILR),
+
+        GPIO_FN(FSIAOBT), \
+        GPIO_FN(BBIF2_TSCK2), \
+        GPIO_FN(TPU2TO3), \
+        GPIO_FN(FSIAIBT),
+        GPIO_FN(FSIAOSLD), \
+        GPIO_FN(BBIF2_TXD2),
+        GPIO_FN(FSIASPDIF), \
+        GPIO_FN(PORT53_IRDA_IN), \
+        GPIO_FN(TPU3TO3), \
+        GPIO_FN(FSIBSPDIF), \
+        GPIO_FN(PORT53_FSICSPDIF),
+        GPIO_FN(FSIBCK), \
+        GPIO_FN(PORT54_IRDA_FIRSEL), \
+        GPIO_FN(TPU3TO2), \
+        GPIO_FN(FSIBOMC), \
+        GPIO_FN(FSICCK), \
+        GPIO_FN(FSICOMC),
+        GPIO_FN(FSIAISLD), \
+        GPIO_FN(TPU0TO0),
+        GPIO_FN(A0), \
+        GPIO_FN(BS_),
+        GPIO_FN(A12), \
+        GPIO_FN(PORT58_KEYOUT7), \
+        GPIO_FN(TPU4TO2),
+        GPIO_FN(A13), \
+        GPIO_FN(PORT59_KEYOUT6), \
+        GPIO_FN(TPU0TO1),
+        GPIO_FN(A14), \
+        GPIO_FN(KEYOUT5),
+        GPIO_FN(A15), \
+        GPIO_FN(KEYOUT4),
+        GPIO_FN(A16), \
+        GPIO_FN(KEYOUT3), \
+        GPIO_FN(MSIOF0_SS1),
+        GPIO_FN(A17), \
+        GPIO_FN(KEYOUT2), \
+        GPIO_FN(MSIOF0_TSYNC),
+        GPIO_FN(A18), \
+        GPIO_FN(KEYOUT1), \
+        GPIO_FN(MSIOF0_TSCK),
+        GPIO_FN(A19), \
+        GPIO_FN(KEYOUT0), \
+        GPIO_FN(MSIOF0_TXD),
+        GPIO_FN(A20), \
+        GPIO_FN(KEYIN0), \
+        GPIO_FN(MSIOF0_RSCK),
+        GPIO_FN(A21), \
+        GPIO_FN(KEYIN1), \
+        GPIO_FN(MSIOF0_RSYNC),
+        GPIO_FN(A22), \
+        GPIO_FN(KEYIN2), \
+        GPIO_FN(MSIOF0_MCK0),
+        GPIO_FN(A23), \
+        GPIO_FN(KEYIN3), \
+        GPIO_FN(MSIOF0_MCK1),
+        GPIO_FN(A24), \
+        GPIO_FN(KEYIN4), \
+        GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(A25), \
+        GPIO_FN(KEYIN5), \
+        GPIO_FN(MSIOF0_SS2),
+        GPIO_FN(A26), \
+        GPIO_FN(KEYIN6),
+        GPIO_FN(KEYIN7),
+        GPIO_FN(D0_NAF0),
+        GPIO_FN(D1_NAF1),
+        GPIO_FN(D2_NAF2),
+        GPIO_FN(D3_NAF3),
+        GPIO_FN(D4_NAF4),
+        GPIO_FN(D5_NAF5),
+        GPIO_FN(D6_NAF6),
+        GPIO_FN(D7_NAF7),
+        GPIO_FN(D8_NAF8),
+        GPIO_FN(D9_NAF9),
+        GPIO_FN(D10_NAF10),
+        GPIO_FN(D11_NAF11),
+        GPIO_FN(D12_NAF12),
+        GPIO_FN(D13_NAF13),
+        GPIO_FN(D14_NAF14),
+        GPIO_FN(D15_NAF15),
+        GPIO_FN(CS4_),
+        GPIO_FN(CS5A_), \
+        GPIO_FN(PORT91_RDWR),
+        GPIO_FN(CS5B_), \
+        GPIO_FN(FCE1_),
+        GPIO_FN(CS6B_), \
+        GPIO_FN(DACK0),
+        GPIO_FN(FCE0_), \
+        GPIO_FN(CS6A_),
+        GPIO_FN(WAIT_), \
+        GPIO_FN(DREQ0),
+        GPIO_FN(RD__FSC),
+        GPIO_FN(WE0__FWE), \
+        GPIO_FN(RDWR_FWE),
+        GPIO_FN(WE1_),
+        GPIO_FN(FRB),
+        GPIO_FN(CKO),
+        GPIO_FN(NBRSTOUT_),
+        GPIO_FN(NBRST_),
+        GPIO_FN(BBIF2_TXD),
+        GPIO_FN(BBIF2_RXD),
+        GPIO_FN(BBIF2_SYNC),
+        GPIO_FN(BBIF2_SCK),
+        GPIO_FN(SCIFA3_CTS_), \
+        GPIO_FN(MFG3_IN2),
+        GPIO_FN(SCIFA3_RXD), \
+        GPIO_FN(MFG3_IN1),
+        GPIO_FN(BBIF1_SS2), \
+        GPIO_FN(SCIFA3_RTS_), \
+        GPIO_FN(MFG3_OUT1),
+        GPIO_FN(SCIFA3_TXD),
+        GPIO_FN(HSI_RX_DATA), \
+        GPIO_FN(BBIF1_RXD),
+        GPIO_FN(HSI_TX_WAKE), \
+        GPIO_FN(BBIF1_TSCK),
+        GPIO_FN(HSI_TX_DATA), \
+        GPIO_FN(BBIF1_TSYNC),
+        GPIO_FN(HSI_TX_READY), \
+        GPIO_FN(BBIF1_TXD),
+        GPIO_FN(HSI_RX_READY), \
+        GPIO_FN(BBIF1_RSCK), \
+        GPIO_FN(PORT115_I2C_SCL2), \
+        GPIO_FN(PORT115_I2C_SCL3),
+        GPIO_FN(HSI_RX_WAKE), \
+        GPIO_FN(BBIF1_RSYNC), \
+        GPIO_FN(PORT116_I2C_SDA2), \
+        GPIO_FN(PORT116_I2C_SDA3),
+        GPIO_FN(HSI_RX_FLAG), \
+        GPIO_FN(BBIF1_SS1), \
+        GPIO_FN(BBIF1_FLOW),
+        GPIO_FN(HSI_TX_FLAG),
+        GPIO_FN(VIO_VD), \
+        GPIO_FN(PORT128_LCD2VSYN), \
+        GPIO_FN(VIO2_VD), \
+        GPIO_FN(LCD2D0),
+
+        GPIO_FN(VIO_HD), \
+        GPIO_FN(PORT129_LCD2HSYN), \
+        GPIO_FN(PORT129_LCD2CS_), \
+        GPIO_FN(VIO2_HD), \
+        GPIO_FN(LCD2D1),
+        GPIO_FN(VIO_D0), \
+        GPIO_FN(PORT130_MSIOF2_RXD), \
+        GPIO_FN(LCD2D10),
+        GPIO_FN(VIO_D1), \
+        GPIO_FN(PORT131_KEYOUT6), \
+        GPIO_FN(PORT131_MSIOF2_SS1), \
+        GPIO_FN(PORT131_KEYOUT11), \
+        GPIO_FN(LCD2D11),
+        GPIO_FN(VIO_D2), \
+        GPIO_FN(PORT132_KEYOUT7), \
+        GPIO_FN(PORT132_MSIOF2_SS2), \
+        GPIO_FN(PORT132_KEYOUT10), \
+        GPIO_FN(LCD2D12),
+        GPIO_FN(VIO_D3), \
+        GPIO_FN(MSIOF2_TSYNC), \
+        GPIO_FN(LCD2D13),
+        GPIO_FN(VIO_D4), \
+        GPIO_FN(MSIOF2_TXD), \
+        GPIO_FN(LCD2D14),
+        GPIO_FN(VIO_D5), \
+        GPIO_FN(MSIOF2_TSCK), \
+        GPIO_FN(LCD2D15),
+        GPIO_FN(VIO_D6), \
+        GPIO_FN(PORT136_KEYOUT8), \
+        GPIO_FN(LCD2D16),
+        GPIO_FN(VIO_D7), \
+        GPIO_FN(PORT137_KEYOUT9), \
+        GPIO_FN(LCD2D17),
+        GPIO_FN(VIO_D8), \
+        GPIO_FN(PORT138_KEYOUT8), \
+        GPIO_FN(VIO2_D0), \
+        GPIO_FN(LCD2D6),
+        GPIO_FN(VIO_D9), \
+        GPIO_FN(PORT139_KEYOUT9), \
+        GPIO_FN(VIO2_D1), \
+        GPIO_FN(LCD2D7),
+        GPIO_FN(VIO_D10), \
+        GPIO_FN(TPU0TO2), \
+        GPIO_FN(VIO2_D2), \
+        GPIO_FN(LCD2D8),
+        GPIO_FN(VIO_D11), \
+        GPIO_FN(TPU0TO3), \
+        GPIO_FN(VIO2_D3), \
+        GPIO_FN(LCD2D9),
+        GPIO_FN(VIO_D12), \
+        GPIO_FN(PORT142_KEYOUT10), \
+        GPIO_FN(VIO2_D4), \
+        GPIO_FN(LCD2D2),
+        GPIO_FN(VIO_D13), \
+        GPIO_FN(PORT143_KEYOUT11), \
+        GPIO_FN(PORT143_KEYOUT6), \
+        GPIO_FN(VIO2_D5), \
+        GPIO_FN(LCD2D3),
+        GPIO_FN(VIO_D14), \
+        GPIO_FN(PORT144_KEYOUT7), \
+        GPIO_FN(VIO2_D6), \
+        GPIO_FN(LCD2D4),
+        GPIO_FN(VIO_D15), \
+        GPIO_FN(TPU1TO3), \
+        GPIO_FN(PORT145_LCD2DISP), \
+        GPIO_FN(PORT145_LCD2RS), \
+        GPIO_FN(VIO2_D7), \
+        GPIO_FN(LCD2D5),
+        GPIO_FN(VIO_CLK), \
+        GPIO_FN(LCD2DCK), \
+        GPIO_FN(PORT146_LCD2WR_), \
+        GPIO_FN(VIO2_CLK), \
+        GPIO_FN(LCD2D18),
+        GPIO_FN(VIO_FIELD), \
+        GPIO_FN(LCD2RD_), \
+        GPIO_FN(VIO2_FIELD), \
+        GPIO_FN(LCD2D19),
+        GPIO_FN(VIO_CKO),
+        GPIO_FN(A27), \
+        GPIO_FN(PORT149_RDWR), \
+        GPIO_FN(MFG0_IN1), \
+        GPIO_FN(PORT149_KEYOUT9),
+        GPIO_FN(MFG0_IN2),
+        GPIO_FN(TS_SPSYNC3), \
+        GPIO_FN(MSIOF2_RSCK),
+        GPIO_FN(TS_SDAT3), \
+        GPIO_FN(MSIOF2_RSYNC),
+        GPIO_FN(TPU1TO2), \
+        GPIO_FN(TS_SDEN3), \
+        GPIO_FN(PORT153_MSIOF2_SS1),
+        GPIO_FN(SCIFA2_TXD1), \
+        GPIO_FN(MSIOF2_MCK0),
+        GPIO_FN(SCIFA2_RXD1), \
+        GPIO_FN(MSIOF2_MCK1),
+        GPIO_FN(SCIFA2_RTS1_), \
+        GPIO_FN(PORT156_MSIOF2_SS2),
+        GPIO_FN(SCIFA2_CTS1_), \
+        GPIO_FN(PORT157_MSIOF2_RXD),
+        GPIO_FN(DINT_), \
+        GPIO_FN(SCIFA2_SCK1), \
+        GPIO_FN(TS_SCK3),
+        GPIO_FN(PORT159_SCIFB_SCK), \
+        GPIO_FN(PORT159_SCIFA5_SCK), \
+        GPIO_FN(NMI),
+        GPIO_FN(PORT160_SCIFB_TXD), \
+        GPIO_FN(PORT160_SCIFA5_TXD),
+        GPIO_FN(PORT161_SCIFB_CTS_), \
+        GPIO_FN(PORT161_SCIFA5_CTS_),
+        GPIO_FN(PORT162_SCIFB_RXD), \
+        GPIO_FN(PORT162_SCIFA5_RXD),
+        GPIO_FN(PORT163_SCIFB_RTS_), \
+        GPIO_FN(PORT163_SCIFA5_RTS_), \
+        GPIO_FN(TPU3TO0),
+        GPIO_FN(LCDD0),
+        GPIO_FN(LCDD1), \
+        GPIO_FN(PORT193_SCIFA5_CTS_), \
+        GPIO_FN(BBIF2_TSYNC1),
+        GPIO_FN(LCDD2), \
+        GPIO_FN(PORT194_SCIFA5_RTS_), \
+        GPIO_FN(BBIF2_TSCK1),
+        GPIO_FN(LCDD3), \
+        GPIO_FN(PORT195_SCIFA5_RXD), \
+        GPIO_FN(BBIF2_TXD1),
+        GPIO_FN(LCDD4), \
+        GPIO_FN(PORT196_SCIFA5_TXD),
+        GPIO_FN(LCDD5), \
+        GPIO_FN(PORT197_SCIFA5_SCK), \
+        GPIO_FN(MFG2_OUT2), \
+        GPIO_FN(TPU2TO1),
+        GPIO_FN(LCDD6),
+        GPIO_FN(LCDD7), \
+        GPIO_FN(TPU4TO1), \
+        GPIO_FN(MFG4_OUT2),
+        GPIO_FN(LCDD8), \
+        GPIO_FN(D16),
+        GPIO_FN(LCDD9), \
+        GPIO_FN(D17),
+        GPIO_FN(LCDD10), \
+        GPIO_FN(D18),
+        GPIO_FN(LCDD11), \
+        GPIO_FN(D19),
+        GPIO_FN(LCDD12), \
+        GPIO_FN(D20),
+        GPIO_FN(LCDD13), \
+        GPIO_FN(D21),
+        GPIO_FN(LCDD14), \
+        GPIO_FN(D22),
+        GPIO_FN(LCDD15), \
+        GPIO_FN(PORT207_MSIOF0L_SS1), \
+        GPIO_FN(D23),
+        GPIO_FN(LCDD16), \
+        GPIO_FN(PORT208_MSIOF0L_SS2), \
+        GPIO_FN(D24),
+        GPIO_FN(LCDD17), \
+        GPIO_FN(D25),
+        GPIO_FN(LCDD18), \
+        GPIO_FN(DREQ2), \
+        GPIO_FN(PORT210_MSIOF0L_SS1), \
+        GPIO_FN(D26),
+        GPIO_FN(LCDD19), \
+        GPIO_FN(PORT211_MSIOF0L_SS2), \
+        GPIO_FN(D27),
+        GPIO_FN(LCDD20), \
+        GPIO_FN(TS_SPSYNC1), \
+        GPIO_FN(MSIOF0L_MCK0), \
+        GPIO_FN(D28),
+        GPIO_FN(LCDD21), \
+        GPIO_FN(TS_SDAT1), \
+        GPIO_FN(MSIOF0L_MCK1), \
+        GPIO_FN(D29),
+        GPIO_FN(LCDD22), \
+        GPIO_FN(TS_SDEN1), \
+        GPIO_FN(MSIOF0L_RSCK), \
+        GPIO_FN(D30),
+        GPIO_FN(LCDD23), \
+        GPIO_FN(TS_SCK1), \
+        GPIO_FN(MSIOF0L_RSYNC), \
+        GPIO_FN(D31),
+        GPIO_FN(LCDDCK), \
+        GPIO_FN(LCDWR_),
+        GPIO_FN(LCDRD_), \
+        GPIO_FN(DACK2), \
+        GPIO_FN(PORT217_LCD2RS), \
+        GPIO_FN(MSIOF0L_TSYNC), \
+        GPIO_FN(VIO2_FIELD3), \
+        GPIO_FN(PORT217_LCD2DISP),
+        GPIO_FN(LCDHSYN), \
+        GPIO_FN(LCDCS_), \
+        GPIO_FN(LCDCS2_), \
+        GPIO_FN(DACK3), \
+        GPIO_FN(PORT218_VIO_CKOR),
+        GPIO_FN(LCDDISP), \
+        GPIO_FN(LCDRS), \
+        GPIO_FN(PORT219_LCD2WR_), \
+        GPIO_FN(DREQ3), \
+        GPIO_FN(MSIOF0L_TSCK), \
+        GPIO_FN(VIO2_CLK3), \
+        GPIO_FN(LCD2DCK_2),
+        GPIO_FN(LCDVSYN), \
+        GPIO_FN(LCDVSYN2),
+        GPIO_FN(LCDLCLK), \
+        GPIO_FN(DREQ1), \
+        GPIO_FN(PORT221_LCD2CS_), \
+        GPIO_FN(PWEN), \
+        GPIO_FN(MSIOF0L_RXD), \
+        GPIO_FN(VIO2_HD3), \
+        GPIO_FN(PORT221_LCD2HSYN),
+        GPIO_FN(LCDDON), \
+        GPIO_FN(LCDDON2), \
+        GPIO_FN(DACK1), \
+        GPIO_FN(OVCN), \
+        GPIO_FN(MSIOF0L_TXD), \
+        GPIO_FN(VIO2_VD3), \
+        GPIO_FN(PORT222_LCD2VSYN),
+
+        GPIO_FN(SCIFA1_TXD), \
+        GPIO_FN(OVCN2),
+        GPIO_FN(EXTLP), \
+        GPIO_FN(SCIFA1_SCK), \
+        GPIO_FN(PORT226_VIO_CKO2),
+        GPIO_FN(SCIFA1_RTS_), \
+        GPIO_FN(IDIN),
+        GPIO_FN(SCIFA1_RXD),
+        GPIO_FN(SCIFA1_CTS_), \
+        GPIO_FN(MFG1_IN1),
+        GPIO_FN(MSIOF1_TXD), \
+        GPIO_FN(SCIFA2_TXD2),
+        GPIO_FN(MSIOF1_TSYNC), \
+        GPIO_FN(SCIFA2_CTS2_),
+        GPIO_FN(MSIOF1_TSCK), \
+        GPIO_FN(SCIFA2_SCK2),
+        GPIO_FN(MSIOF1_RXD), \
+        GPIO_FN(SCIFA2_RXD2),
+        GPIO_FN(MSIOF1_RSCK), \
+        GPIO_FN(SCIFA2_RTS2_), \
+        GPIO_FN(VIO2_CLK2), \
+        GPIO_FN(LCD2D20),
+        GPIO_FN(MSIOF1_RSYNC), \
+        GPIO_FN(MFG1_IN2), \
+        GPIO_FN(VIO2_VD2), \
+        GPIO_FN(LCD2D21),
+        GPIO_FN(MSIOF1_MCK0), \
+        GPIO_FN(PORT236_I2C_SDA2),
+        GPIO_FN(MSIOF1_MCK1), \
+        GPIO_FN(PORT237_I2C_SCL2),
+        GPIO_FN(MSIOF1_SS1), \
+        GPIO_FN(VIO2_FIELD2), \
+        GPIO_FN(LCD2D22),
+        GPIO_FN(MSIOF1_SS2), \
+        GPIO_FN(VIO2_HD2), \
+        GPIO_FN(LCD2D23),
+        GPIO_FN(SCIFA6_TXD),
+        GPIO_FN(PORT241_IRDA_OUT), \
+        GPIO_FN(PORT241_IROUT), \
+        GPIO_FN(MFG4_OUT1), \
+        GPIO_FN(TPU4TO0),
+        GPIO_FN(PORT242_IRDA_IN), \
+        GPIO_FN(MFG4_IN2),
+        GPIO_FN(PORT243_IRDA_FIRSEL), \
+        GPIO_FN(PORT243_VIO_CKO2),
+        GPIO_FN(PORT244_SCIFA5_CTS_), \
+        GPIO_FN(MFG2_IN1), \
+        GPIO_FN(PORT244_SCIFB_CTS_), \
+        GPIO_FN(MSIOF2R_RXD),
+        GPIO_FN(PORT245_SCIFA5_RTS_), \
+        GPIO_FN(MFG2_IN2), \
+        GPIO_FN(PORT245_SCIFB_RTS_), \
+        GPIO_FN(MSIOF2R_TXD),
+        GPIO_FN(PORT246_SCIFA5_RXD), \
+        GPIO_FN(MFG1_OUT1), \
+        GPIO_FN(PORT246_SCIFB_RXD), \
+        GPIO_FN(TPU1TO0),
+        GPIO_FN(PORT247_SCIFA5_TXD), \
+        GPIO_FN(MFG3_OUT2), \
+        GPIO_FN(PORT247_SCIFB_TXD), \
+        GPIO_FN(TPU3TO1),
+        GPIO_FN(PORT248_SCIFA5_SCK), \
+        GPIO_FN(MFG2_OUT1), \
+        GPIO_FN(PORT248_SCIFB_SCK), \
+        GPIO_FN(TPU2TO0), \
+        GPIO_FN(PORT248_I2C_SCL3), \
+        GPIO_FN(MSIOF2R_TSCK),
+        GPIO_FN(PORT249_IROUT), \
+        GPIO_FN(MFG4_IN1), \
+        GPIO_FN(PORT249_I2C_SDA3), \
+        GPIO_FN(MSIOF2R_TSYNC),
+        GPIO_FN(SDHICLK0),
+        GPIO_FN(SDHICD0),
+        GPIO_FN(SDHID0_0),
+        GPIO_FN(SDHID0_1),
+        GPIO_FN(SDHID0_2),
+        GPIO_FN(SDHID0_3),
+        GPIO_FN(SDHICMD0),
+        GPIO_FN(SDHIWP0),
+        GPIO_FN(SDHICLK1),
+        GPIO_FN(SDHID1_0), \
+        GPIO_FN(TS_SPSYNC2),
+        GPIO_FN(SDHID1_1), \
+        GPIO_FN(TS_SDAT2),
+        GPIO_FN(SDHID1_2), \
+        GPIO_FN(TS_SDEN2),
+        GPIO_FN(SDHID1_3), \
+        GPIO_FN(TS_SCK2),
+        GPIO_FN(SDHICMD1),
+        GPIO_FN(SDHICLK2),
+        GPIO_FN(SDHID2_0), \
+        GPIO_FN(TS_SPSYNC4),
+        GPIO_FN(SDHID2_1), \
+        GPIO_FN(TS_SDAT4),
+        GPIO_FN(SDHID2_2), \
+        GPIO_FN(TS_SDEN4),
+        GPIO_FN(SDHID2_3), \
+        GPIO_FN(TS_SCK4),
+        GPIO_FN(SDHICMD2),
+        GPIO_FN(MMCCLK0),
+        GPIO_FN(MMCD0_0),
+        GPIO_FN(MMCD0_1),
+        GPIO_FN(MMCD0_2),
+        GPIO_FN(MMCD0_3),
+        GPIO_FN(MMCD0_4), \
+        GPIO_FN(TS_SPSYNC5),
+        GPIO_FN(MMCD0_5), \
+        GPIO_FN(TS_SDAT5),
+        GPIO_FN(MMCD0_6), \
+        GPIO_FN(TS_SDEN5),
+        GPIO_FN(MMCD0_7), \
+        GPIO_FN(TS_SCK5),
+        GPIO_FN(MMCCMD0),
+        GPIO_FN(RESETOUTS_), \
+        GPIO_FN(EXTAL2OUT),
+        GPIO_FN(MCP_WAIT__MCP_FRB),
+        GPIO_FN(MCP_CKO), \
+        GPIO_FN(MMCCLK1),
+        GPIO_FN(MCP_D15_MCP_NAF15),
+        GPIO_FN(MCP_D14_MCP_NAF14),
+        GPIO_FN(MCP_D13_MCP_NAF13),
+        GPIO_FN(MCP_D12_MCP_NAF12),
+        GPIO_FN(MCP_D11_MCP_NAF11),
+        GPIO_FN(MCP_D10_MCP_NAF10),
+        GPIO_FN(MCP_D9_MCP_NAF9),
+        GPIO_FN(MCP_D8_MCP_NAF8), \
+        GPIO_FN(MMCCMD1),
+        GPIO_FN(MCP_D7_MCP_NAF7), \
+        GPIO_FN(MMCD1_7),
+
+        GPIO_FN(MCP_D6_MCP_NAF6), \
+        GPIO_FN(MMCD1_6),
+        GPIO_FN(MCP_D5_MCP_NAF5), \
+        GPIO_FN(MMCD1_5),
+        GPIO_FN(MCP_D4_MCP_NAF4), \
+        GPIO_FN(MMCD1_4),
+        GPIO_FN(MCP_D3_MCP_NAF3), \
+        GPIO_FN(MMCD1_3),
+        GPIO_FN(MCP_D2_MCP_NAF2), \
+        GPIO_FN(MMCD1_2),
+        GPIO_FN(MCP_D1_MCP_NAF1), \
+        GPIO_FN(MMCD1_1),
+        GPIO_FN(MCP_D0_MCP_NAF0), \
+        GPIO_FN(MMCD1_0),
+        GPIO_FN(MCP_NBRSTOUT_),
+        GPIO_FN(MCP_WE0__MCP_FWE), \
+        GPIO_FN(MCP_RDWR_MCP_FWE),
+
+        /* MSEL2 special cases */
+        GPIO_FN(TSIF2_TS_XX1),
+        GPIO_FN(TSIF2_TS_XX2),
+        GPIO_FN(TSIF2_TS_XX3),
+        GPIO_FN(TSIF2_TS_XX4),
+        GPIO_FN(TSIF2_TS_XX5),
+        GPIO_FN(TSIF1_TS_XX1),
+        GPIO_FN(TSIF1_TS_XX2),
+        GPIO_FN(TSIF1_TS_XX3),
+        GPIO_FN(TSIF1_TS_XX4),
+        GPIO_FN(TSIF1_TS_XX5),
+        GPIO_FN(TSIF0_TS_XX1),
+        GPIO_FN(TSIF0_TS_XX2),
+        GPIO_FN(TSIF0_TS_XX3),
+        GPIO_FN(TSIF0_TS_XX4),
+        GPIO_FN(TSIF0_TS_XX5),
+        GPIO_FN(MST1_TS_XX1),
+        GPIO_FN(MST1_TS_XX2),
+        GPIO_FN(MST1_TS_XX3),
+        GPIO_FN(MST1_TS_XX4),
+        GPIO_FN(MST1_TS_XX5),
+        GPIO_FN(MST0_TS_XX1),
+        GPIO_FN(MST0_TS_XX2),
+        GPIO_FN(MST0_TS_XX3),
+        GPIO_FN(MST0_TS_XX4),
+        GPIO_FN(MST0_TS_XX5),
+
+        /* MSEL3 special cases */
+        GPIO_FN(SDHI0_VCCQ_MC0_ON),
+        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
+        GPIO_FN(DEBUG_MON_VIO),
+        GPIO_FN(DEBUG_MON_LCDD),
+        GPIO_FN(LCDC_LCDC0),
+        GPIO_FN(LCDC_LCDC1),
+
+        /* MSEL4 special cases */
+        GPIO_FN(IRQ9_MEM_INT),
+        GPIO_FN(IRQ9_MCP_INT),
+        GPIO_FN(A11),
+        GPIO_FN(KEYOUT8),
+        GPIO_FN(TPU4TO3),
+        GPIO_FN(RESETA_N_PU_ON),
+        GPIO_FN(RESETA_N_PU_OFF),
+        GPIO_FN(EDBGREQ_PD),
+        GPIO_FN(EDBGREQ_PU),
+
+        /* Functions with pull-ups */
+        GPIO_FN(KEYIN0_PU),
+        GPIO_FN(KEYIN1_PU),
+        GPIO_FN(KEYIN2_PU),
+        GPIO_FN(KEYIN3_PU),
+        GPIO_FN(KEYIN4_PU),
+        GPIO_FN(KEYIN5_PU),
+        GPIO_FN(KEYIN6_PU),
+        GPIO_FN(KEYIN7_PU),
+        GPIO_FN(SDHID1_0_PU),
+        GPIO_FN(SDHID1_1_PU),
+        GPIO_FN(SDHID1_2_PU),
+        GPIO_FN(SDHID1_3_PU),
+        GPIO_FN(SDHICMD1_PU),
+        GPIO_FN(MMCCMD0_PU),
+        GPIO_FN(MMCCMD1_PU),
+        GPIO_FN(FSIACK_PU),
+        GPIO_FN(FSIAILR_PU),
+        GPIO_FN(FSIAIBT_PU),
+        GPIO_FN(FSIAISLD_PU),
+};
+
+#define PORTCR(nr, reg) \
+        { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
+                0, \
+                /*0001*/ PORT##nr##_OUT , \
+                /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
+                /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
+                /*1110*/ PORT##nr##_IN_PU, 0, \
+                PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
+                PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
+                PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
+        }
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        PORTCR(0, 0xe6050000), /* PORT0CR */
+        PORTCR(1, 0xe6050001), /* PORT1CR */
+        PORTCR(2, 0xe6050002), /* PORT2CR */
+        PORTCR(3, 0xe6050003), /* PORT3CR */
+        PORTCR(4, 0xe6050004), /* PORT4CR */
+        PORTCR(5, 0xe6050005), /* PORT5CR */
+        PORTCR(6, 0xe6050006), /* PORT6CR */
+        PORTCR(7, 0xe6050007), /* PORT7CR */
+        PORTCR(8, 0xe6050008), /* PORT8CR */
+        PORTCR(9, 0xe6050009), /* PORT9CR */
+
+        PORTCR(10, 0xe605000a), /* PORT10CR */
+        PORTCR(11, 0xe605000b), /* PORT11CR */
+        PORTCR(12, 0xe605000c), /* PORT12CR */
+        PORTCR(13, 0xe605000d), /* PORT13CR */
+        PORTCR(14, 0xe605000e), /* PORT14CR */
+        PORTCR(15, 0xe605000f), /* PORT15CR */
+        PORTCR(16, 0xe6050010), /* PORT16CR */
+        PORTCR(17, 0xe6050011), /* PORT17CR */
+        PORTCR(18, 0xe6050012), /* PORT18CR */
+        PORTCR(19, 0xe6050013), /* PORT19CR */
+
+        PORTCR(20, 0xe6050014), /* PORT20CR */
+        PORTCR(21, 0xe6050015), /* PORT21CR */
+        PORTCR(22, 0xe6050016), /* PORT22CR */
+        PORTCR(23, 0xe6050017), /* PORT23CR */
+        PORTCR(24, 0xe6050018), /* PORT24CR */
+        PORTCR(25, 0xe6050019), /* PORT25CR */
+        PORTCR(26, 0xe605001a), /* PORT26CR */
+        PORTCR(27, 0xe605001b), /* PORT27CR */
+        PORTCR(28, 0xe605001c), /* PORT28CR */
+        PORTCR(29, 0xe605001d), /* PORT29CR */
+
+        PORTCR(30, 0xe605001e), /* PORT30CR */
+        PORTCR(31, 0xe605001f), /* PORT31CR */
+        PORTCR(32, 0xe6051020), /* PORT32CR */
+        PORTCR(33, 0xe6051021), /* PORT33CR */
+        PORTCR(34, 0xe6051022), /* PORT34CR */
+        PORTCR(35, 0xe6051023), /* PORT35CR */
+        PORTCR(36, 0xe6051024), /* PORT36CR */
+        PORTCR(37, 0xe6051025), /* PORT37CR */
+        PORTCR(38, 0xe6051026), /* PORT38CR */
+        PORTCR(39, 0xe6051027), /* PORT39CR */
+
+        PORTCR(40, 0xe6051028), /* PORT40CR */
+        PORTCR(41, 0xe6051029), /* PORT41CR */
+        PORTCR(42, 0xe605102a), /* PORT42CR */
+        PORTCR(43, 0xe605102b), /* PORT43CR */
+        PORTCR(44, 0xe605102c), /* PORT44CR */
+        PORTCR(45, 0xe605102d), /* PORT45CR */
+        PORTCR(46, 0xe605102e), /* PORT46CR */
+        PORTCR(47, 0xe605102f), /* PORT47CR */
+        PORTCR(48, 0xe6051030), /* PORT48CR */
+        PORTCR(49, 0xe6051031), /* PORT49CR */
+
+        PORTCR(50, 0xe6051032), /* PORT50CR */
+        PORTCR(51, 0xe6051033), /* PORT51CR */
+        PORTCR(52, 0xe6051034), /* PORT52CR */
+        PORTCR(53, 0xe6051035), /* PORT53CR */
+        PORTCR(54, 0xe6051036), /* PORT54CR */
+        PORTCR(55, 0xe6051037), /* PORT55CR */
+        PORTCR(56, 0xe6051038), /* PORT56CR */
+        PORTCR(57, 0xe6051039), /* PORT57CR */
+        PORTCR(58, 0xe605103a), /* PORT58CR */
+        PORTCR(59, 0xe605103b), /* PORT59CR */
+
+        PORTCR(60, 0xe605103c), /* PORT60CR */
+        PORTCR(61, 0xe605103d), /* PORT61CR */
+        PORTCR(62, 0xe605103e), /* PORT62CR */
+        PORTCR(63, 0xe605103f), /* PORT63CR */
+        PORTCR(64, 0xe6051040), /* PORT64CR */
+        PORTCR(65, 0xe6051041), /* PORT65CR */
+        PORTCR(66, 0xe6051042), /* PORT66CR */
+        PORTCR(67, 0xe6051043), /* PORT67CR */
+        PORTCR(68, 0xe6051044), /* PORT68CR */
+        PORTCR(69, 0xe6051045), /* PORT69CR */
+
+        PORTCR(70, 0xe6051046), /* PORT70CR */
+        PORTCR(71, 0xe6051047), /* PORT71CR */
+        PORTCR(72, 0xe6051048), /* PORT72CR */
+        PORTCR(73, 0xe6051049), /* PORT73CR */
+        PORTCR(74, 0xe605104a), /* PORT74CR */
+        PORTCR(75, 0xe605104b), /* PORT75CR */
+        PORTCR(76, 0xe605104c), /* PORT76CR */
+        PORTCR(77, 0xe605104d), /* PORT77CR */
+        PORTCR(78, 0xe605104e), /* PORT78CR */
+        PORTCR(79, 0xe605104f), /* PORT79CR */
+
+        PORTCR(80, 0xe6051050), /* PORT80CR */
+        PORTCR(81, 0xe6051051), /* PORT81CR */
+        PORTCR(82, 0xe6051052), /* PORT82CR */
+        PORTCR(83, 0xe6051053), /* PORT83CR */
+        PORTCR(84, 0xe6051054), /* PORT84CR */
+        PORTCR(85, 0xe6051055), /* PORT85CR */
+        PORTCR(86, 0xe6051056), /* PORT86CR */
+        PORTCR(87, 0xe6051057), /* PORT87CR */
+        PORTCR(88, 0xe6051058), /* PORT88CR */
+        PORTCR(89, 0xe6051059), /* PORT89CR */
+
+        PORTCR(90, 0xe605105a), /* PORT90CR */
+        PORTCR(91, 0xe605105b), /* PORT91CR */
+        PORTCR(92, 0xe605105c), /* PORT92CR */
+        PORTCR(93, 0xe605105d), /* PORT93CR */
+        PORTCR(94, 0xe605105e), /* PORT94CR */
+        PORTCR(95, 0xe605105f), /* PORT95CR */
+        PORTCR(96, 0xe6052060), /* PORT96CR */
+        PORTCR(97, 0xe6052061), /* PORT97CR */
+        PORTCR(98, 0xe6052062), /* PORT98CR */
+        PORTCR(99, 0xe6052063), /* PORT99CR */
+
+        PORTCR(100, 0xe6052064), /* PORT100CR */
+        PORTCR(101, 0xe6052065), /* PORT101CR */
+        PORTCR(102, 0xe6052066), /* PORT102CR */
+        PORTCR(103, 0xe6052067), /* PORT103CR */
+        PORTCR(104, 0xe6052068), /* PORT104CR */
+        PORTCR(105, 0xe6052069), /* PORT105CR */
+        PORTCR(106, 0xe605206a), /* PORT106CR */
+        PORTCR(107, 0xe605206b), /* PORT107CR */
+        PORTCR(108, 0xe605206c), /* PORT108CR */
+        PORTCR(109, 0xe605206d), /* PORT109CR */
+
+        PORTCR(110, 0xe605206e), /* PORT110CR */
+        PORTCR(111, 0xe605206f), /* PORT111CR */
+        PORTCR(112, 0xe6052070), /* PORT112CR */
+        PORTCR(113, 0xe6052071), /* PORT113CR */
+        PORTCR(114, 0xe6052072), /* PORT114CR */
+        PORTCR(115, 0xe6052073), /* PORT115CR */
+        PORTCR(116, 0xe6052074), /* PORT116CR */
+        PORTCR(117, 0xe6052075), /* PORT117CR */
+        PORTCR(118, 0xe6052076), /* PORT118CR */
+
+        PORTCR(128, 0xe6052080), /* PORT128CR */
+        PORTCR(129, 0xe6052081), /* PORT129CR */
+
+        PORTCR(130, 0xe6052082), /* PORT130CR */
+        PORTCR(131, 0xe6052083), /* PORT131CR */
+        PORTCR(132, 0xe6052084), /* PORT132CR */
+        PORTCR(133, 0xe6052085), /* PORT133CR */
+        PORTCR(134, 0xe6052086), /* PORT134CR */
+        PORTCR(135, 0xe6052087), /* PORT135CR */
+        PORTCR(136, 0xe6052088), /* PORT136CR */
+        PORTCR(137, 0xe6052089), /* PORT137CR */
+        PORTCR(138, 0xe605208a), /* PORT138CR */
+        PORTCR(139, 0xe605208b), /* PORT139CR */
+
+        PORTCR(140, 0xe605208c), /* PORT140CR */
+        PORTCR(141, 0xe605208d), /* PORT141CR */
+        PORTCR(142, 0xe605208e), /* PORT142CR */
+        PORTCR(143, 0xe605208f), /* PORT143CR */
+        PORTCR(144, 0xe6052090), /* PORT144CR */
+        PORTCR(145, 0xe6052091), /* PORT145CR */
+        PORTCR(146, 0xe6052092), /* PORT146CR */
+        PORTCR(147, 0xe6052093), /* PORT147CR */
+        PORTCR(148, 0xe6052094), /* PORT148CR */
+        PORTCR(149, 0xe6052095), /* PORT149CR */
+
+        PORTCR(150, 0xe6052096), /* PORT150CR */
+        PORTCR(151, 0xe6052097), /* PORT151CR */
+        PORTCR(152, 0xe6052098), /* PORT152CR */
+        PORTCR(153, 0xe6052099), /* PORT153CR */
+        PORTCR(154, 0xe605209a), /* PORT154CR */
+        PORTCR(155, 0xe605209b), /* PORT155CR */
+        PORTCR(156, 0xe605209c), /* PORT156CR */
+        PORTCR(157, 0xe605209d), /* PORT157CR */
+        PORTCR(158, 0xe605209e), /* PORT158CR */
+        PORTCR(159, 0xe605209f), /* PORT159CR */
+
+        PORTCR(160, 0xe60520a0), /* PORT160CR */
+        PORTCR(161, 0xe60520a1), /* PORT161CR */
+        PORTCR(162, 0xe60520a2), /* PORT162CR */
+        PORTCR(163, 0xe60520a3), /* PORT163CR */
+        PORTCR(164, 0xe60520a4), /* PORT164CR */
+
+        PORTCR(192, 0xe60520c0), /* PORT192CR */
+        PORTCR(193, 0xe60520c1), /* PORT193CR */
+        PORTCR(194, 0xe60520c2), /* PORT194CR */
+        PORTCR(195, 0xe60520c3), /* PORT195CR */
+        PORTCR(196, 0xe60520c4), /* PORT196CR */
+        PORTCR(197, 0xe60520c5), /* PORT197CR */
+        PORTCR(198, 0xe60520c6), /* PORT198CR */
+        PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+        PORTCR(200, 0xe60520c8), /* PORT200CR */
+        PORTCR(201, 0xe60520c9), /* PORT201CR */
+        PORTCR(202, 0xe60520ca), /* PORT202CR */
+        PORTCR(203, 0xe60520cb), /* PORT203CR */
+        PORTCR(204, 0xe60520cc), /* PORT204CR */
+        PORTCR(205, 0xe60520cd), /* PORT205CR */
+        PORTCR(206, 0xe60520ce), /* PORT206CR */
+        PORTCR(207, 0xe60520cf), /* PORT207CR */
+        PORTCR(208, 0xe60520d0), /* PORT208CR */
+        PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+        PORTCR(210, 0xe60520d2), /* PORT210CR */
+        PORTCR(211, 0xe60520d3), /* PORT211CR */
+        PORTCR(212, 0xe60520d4), /* PORT212CR */
+        PORTCR(213, 0xe60520d5), /* PORT213CR */
+        PORTCR(214, 0xe60520d6), /* PORT214CR */
+        PORTCR(215, 0xe60520d7), /* PORT215CR */
+        PORTCR(216, 0xe60520d8), /* PORT216CR */
+        PORTCR(217, 0xe60520d9), /* PORT217CR */
+        PORTCR(218, 0xe60520da), /* PORT218CR */
+        PORTCR(219, 0xe60520db), /* PORT219CR */
+
+        PORTCR(220, 0xe60520dc), /* PORT220CR */
+        PORTCR(221, 0xe60520dd), /* PORT221CR */
+        PORTCR(222, 0xe60520de), /* PORT222CR */
+        PORTCR(223, 0xe60520df), /* PORT223CR */
+        PORTCR(224, 0xe60530e0), /* PORT224CR */
+        PORTCR(225, 0xe60530e1), /* PORT225CR */
+        PORTCR(226, 0xe60530e2), /* PORT226CR */
+        PORTCR(227, 0xe60530e3), /* PORT227CR */
+        PORTCR(228, 0xe60530e4), /* PORT228CR */
+        PORTCR(229, 0xe60530e5), /* PORT229CR */
+
+        PORTCR(230, 0xe60530e6), /* PORT230CR */
+        PORTCR(231, 0xe60530e7), /* PORT231CR */
+        PORTCR(232, 0xe60530e8), /* PORT232CR */
+        PORTCR(233, 0xe60530e9), /* PORT233CR */
+        PORTCR(234, 0xe60530ea), /* PORT234CR */
+        PORTCR(235, 0xe60530eb), /* PORT235CR */
+        PORTCR(236, 0xe60530ec), /* PORT236CR */
+        PORTCR(237, 0xe60530ed), /* PORT237CR */
+        PORTCR(238, 0xe60530ee), /* PORT238CR */
+        PORTCR(239, 0xe60530ef), /* PORT239CR */
+
+        PORTCR(240, 0xe60530f0), /* PORT240CR */
+        PORTCR(241, 0xe60530f1), /* PORT241CR */
+        PORTCR(242, 0xe60530f2), /* PORT242CR */
+        PORTCR(243, 0xe60530f3), /* PORT243CR */
+        PORTCR(244, 0xe60530f4), /* PORT244CR */
+        PORTCR(245, 0xe60530f5), /* PORT245CR */
+        PORTCR(246, 0xe60530f6), /* PORT246CR */
+        PORTCR(247, 0xe60530f7), /* PORT247CR */
+        PORTCR(248, 0xe60530f8), /* PORT248CR */
+        PORTCR(249, 0xe60530f9), /* PORT249CR */
+
+        PORTCR(250, 0xe60530fa), /* PORT250CR */
+        PORTCR(251, 0xe60530fb), /* PORT251CR */
+        PORTCR(252, 0xe60530fc), /* PORT252CR */
+        PORTCR(253, 0xe60530fd), /* PORT253CR */
+        PORTCR(254, 0xe60530fe), /* PORT254CR */
+        PORTCR(255, 0xe60530ff), /* PORT255CR */
+        PORTCR(256, 0xe6053100), /* PORT256CR */
+        PORTCR(257, 0xe6053101), /* PORT257CR */
+        PORTCR(258, 0xe6053102), /* PORT258CR */
+        PORTCR(259, 0xe6053103), /* PORT259CR */
+
+        PORTCR(260, 0xe6053104), /* PORT260CR */
+        PORTCR(261, 0xe6053105), /* PORT261CR */
+        PORTCR(262, 0xe6053106), /* PORT262CR */
+        PORTCR(263, 0xe6053107), /* PORT263CR */
+        PORTCR(264, 0xe6053108), /* PORT264CR */
+        PORTCR(265, 0xe6053109), /* PORT265CR */
+        PORTCR(266, 0xe605310a), /* PORT266CR */
+        PORTCR(267, 0xe605310b), /* PORT267CR */
+        PORTCR(268, 0xe605310c), /* PORT268CR */
+        PORTCR(269, 0xe605310d), /* PORT269CR */
+
+        PORTCR(270, 0xe605310e), /* PORT270CR */
+        PORTCR(271, 0xe605310f), /* PORT271CR */
+        PORTCR(272, 0xe6053110), /* PORT272CR */
+        PORTCR(273, 0xe6053111), /* PORT273CR */
+        PORTCR(274, 0xe6053112), /* PORT274CR */
+        PORTCR(275, 0xe6053113), /* PORT275CR */
+        PORTCR(276, 0xe6053114), /* PORT276CR */
+        PORTCR(277, 0xe6053115), /* PORT277CR */
+        PORTCR(278, 0xe6053116), /* PORT278CR */
+        PORTCR(279, 0xe6053117), /* PORT279CR */
+
+        PORTCR(280, 0xe6053118), /* PORT280CR */
+        PORTCR(281, 0xe6053119), /* PORT281CR */
+        PORTCR(282, 0xe605311a), /* PORT282CR */
+
+        PORTCR(288, 0xe6052120), /* PORT288CR */
+        PORTCR(289, 0xe6052121), /* PORT289CR */
+
+        PORTCR(290, 0xe6052122), /* PORT290CR */
+        PORTCR(291, 0xe6052123), /* PORT291CR */
+        PORTCR(292, 0xe6052124), /* PORT292CR */
+        PORTCR(293, 0xe6052125), /* PORT293CR */
+        PORTCR(294, 0xe6052126), /* PORT294CR */
+        PORTCR(295, 0xe6052127), /* PORT295CR */
+        PORTCR(296, 0xe6052128), /* PORT296CR */
+        PORTCR(297, 0xe6052129), /* PORT297CR */
+        PORTCR(298, 0xe605212a), /* PORT298CR */
+        PORTCR(299, 0xe605212b), /* PORT299CR */
+
+        PORTCR(300, 0xe605212c), /* PORT300CR */
+        PORTCR(301, 0xe605212d), /* PORT301CR */
+        PORTCR(302, 0xe605212e), /* PORT302CR */
+        PORTCR(303, 0xe605212f), /* PORT303CR */
+        PORTCR(304, 0xe6052130), /* PORT304CR */
+        PORTCR(305, 0xe6052131), /* PORT305CR */
+        PORTCR(306, 0xe6052132), /* PORT306CR */
+        PORTCR(307, 0xe6052133), /* PORT307CR */
+        PORTCR(308, 0xe6052134), /* PORT308CR */
+        PORTCR(309, 0xe6052135), /* PORT309CR */
+
+        { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+                        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+                        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+                        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+                        0, 0,
+                        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+                        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+                        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+                        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+                        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+                        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+                        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+                        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+                        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+                        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+                        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+                        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+                        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+                        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+                        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+                        0, 0,
+                        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+                        0, 0,
+                        0, 0,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+                        0, 0,
+                        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+                        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+                        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+                        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+                        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+                        0, 0,
+                        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+                        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+                        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+                        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+                        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+                        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+                        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+                        0, 0,
+                }
+        },
+        { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
+                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
+                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, PORT164_DATA,
+                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
+                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+                        0, 0, 0, 0,
+                        0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+                        PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+                        PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+                        PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+                        PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, PORT309_DATA, PORT308_DATA,
+                        PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+                        PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+                        PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+                        PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+                        PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh73a0_pinmux_info = {
+        .name = "sh73a0_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PORT0,
+        .last_gpio = GPIO_FN_FSIAISLD_PU,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void sh73a0_pinmux_init(void)
+{
+        register_pinmux(&sh73a0_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
new file mode 100644
index 000000000000..65e879bab4dc
--- /dev/null
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -0,0 +1,70 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2011  Paul Mundt
+ *
+ * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+
+static unsigned int __init shmobile_smp_get_core_count(void)
+{
+        if (machine_is_ag5evm())
+                return sh73a0_get_core_count();
+
+        return 1;
+}
+
+static void __init shmobile_smp_prepare_cpus(void)
+{
+        if (machine_is_ag5evm())
+                sh73a0_smp_prepare_cpus();
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        trace_hardirqs_off();
+
+        if (machine_is_ag5evm())
+                sh73a0_secondary_init(cpu);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (machine_is_ag5evm())
+                return sh73a0_boot_secondary(cpu);
+
+        return -ENOSYS;
+}
+
+void __init smp_init_cpus(void)
+{
+        unsigned int ncores = shmobile_smp_get_core_count();
+        unsigned int i;
+
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
+
+        for (i = 0; i < max_cpus; i++)
+                set_cpu_present(i, true);
+
+        shmobile_smp_prepare_cpus();
+}
diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c
new file mode 100644
index 000000000000..94912d3944d3
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm_runtime.c
@@ -0,0 +1,169 @@
+/*
+ * arch/arm/mach-shmobile/pm_runtime.c
+ *
+ * Runtime PM support code for SuperH Mobile ARM
+ *
+ *  Copyright (C) 2009-2010 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/sh_clk.h>
+#include <linux/bitmap.h>
+
+#ifdef CONFIG_PM_RUNTIME
+#define BIT_ONCE 0
+#define BIT_ACTIVE 1
+#define BIT_CLK_ENABLED 2
+
+struct pm_runtime_data {
+        unsigned long flags;
+        struct clk *clk;
+};
+
+static void __devres_release(struct device *dev, void *res)
+{
+        struct pm_runtime_data *prd = res;
+
+        dev_dbg(dev, "__devres_release()\n");
+
+        if (test_bit(BIT_CLK_ENABLED, &prd->flags))
+                clk_disable(prd->clk);
+
+        if (test_bit(BIT_ACTIVE, &prd->flags))
+                clk_put(prd->clk);
+}
+
+static struct pm_runtime_data *__to_prd(struct device *dev)
+{
+        return devres_find(dev, __devres_release, NULL, NULL);
+}
+
+static void platform_pm_runtime_init(struct device *dev,
+                                     struct pm_runtime_data *prd)
+{
+        if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) {
+                prd->clk = clk_get(dev, NULL);
+                if (!IS_ERR(prd->clk)) {
+                        set_bit(BIT_ACTIVE, &prd->flags);
+                        dev_info(dev, "clocks managed by runtime pm\n");
+                }
+        }
+}
+
+static void platform_pm_runtime_bug(struct device *dev,
+                                    struct pm_runtime_data *prd)
+{
+        if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags))
+                dev_err(dev, "runtime pm suspend before resume\n");
+}
+
+int platform_pm_runtime_suspend(struct device *dev)
+{
+        struct pm_runtime_data *prd = __to_prd(dev);
+
+        dev_dbg(dev, "platform_pm_runtime_suspend()\n");
+
+        platform_pm_runtime_bug(dev, prd);
+
+        if (prd && test_bit(BIT_ACTIVE, &prd->flags)) {
+                clk_disable(prd->clk);
+                clear_bit(BIT_CLK_ENABLED, &prd->flags);
+        }
+
+        return 0;
+}
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+        struct pm_runtime_data *prd = __to_prd(dev);
+
+        dev_dbg(dev, "platform_pm_runtime_resume()\n");
+
+        platform_pm_runtime_init(dev, prd);
+
+        if (prd && test_bit(BIT_ACTIVE, &prd->flags)) {
+                clk_enable(prd->clk);
+                set_bit(BIT_CLK_ENABLED, &prd->flags);
+        }
+
+        return 0;
+}
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+        /* suspend synchronously to disable clocks immediately */
+        return pm_runtime_suspend(dev);
+}
+
+static int platform_bus_notify(struct notifier_block *nb,
+                               unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct pm_runtime_data *prd;
+
+        dev_dbg(dev, "platform_bus_notify() %ld !\n", action);
+
+        if (action == BUS_NOTIFY_BIND_DRIVER) {
+                prd = devres_alloc(__devres_release, sizeof(*prd), GFP_KERNEL);
+                if (prd)
+                        devres_add(dev, prd);
+                else
+                        dev_err(dev, "unable to alloc memory for runtime pm\n");
+        }
+
+        return 0;
+}
+
+#else /* CONFIG_PM_RUNTIME */
+
+static int platform_bus_notify(struct notifier_block *nb,
+                               unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct clk *clk;
+
+        dev_dbg(dev, "platform_bus_notify() %ld !\n", action);
+
+        switch (action) {
+        case BUS_NOTIFY_BIND_DRIVER:
+                clk = clk_get(dev, NULL);
+                if (!IS_ERR(clk)) {
+                        clk_enable(clk);
+                        clk_put(clk);
+                        dev_info(dev, "runtime pm disabled, clock forced on\n");
+                }
+                break;
+        case BUS_NOTIFY_UNBOUND_DRIVER:
+                clk = clk_get(dev, NULL);
+                if (!IS_ERR(clk)) {
+                        clk_disable(clk);
+                        clk_put(clk);
+                        dev_info(dev, "runtime pm disabled, clock forced off\n");
+                }
+                break;
+        }
+
+        return 0;
+}
+
+#endif /* CONFIG_PM_RUNTIME */
+
+static struct notifier_block platform_bus_notifier = {
+        .notifier_call = platform_bus_notify
+};
+
+static int __init sh_pm_runtime_init(void)
+{
+        bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
+        return 0;
+}
+core_initcall(sh_pm_runtime_init);
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
new file mode 100644
index 000000000000..ce28141662da
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -0,0 +1,225 @@
+/*
+ * sh7367 processor support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/* SCIFA0 */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xe6c40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
+                            evt2irq(0xc00), evt2irq(0xc00) },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+/* SCIFA1 */
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xe6c50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
+                            evt2irq(0xc20), evt2irq(0xc20) },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+/* SCIFA2 */
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xe6c60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
+                            evt2irq(0xc40), evt2irq(0xc40) },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+/* SCIFA3 */
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xe6c70000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
+                            evt2irq(0xc60), evt2irq(0xc60) },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+/* SCIFA4 */
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xe6c80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
+                            evt2irq(0xd20), evt2irq(0xd20) },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+/* SCIFA5 */
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xe6cb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
+                            evt2irq(0xd40), evt2irq(0xd40) },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+/* SCIFB */
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xe6c30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
+                            evt2irq(0xd60), evt2irq(0xd60) },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .channel_offset = 0x10,
+        .timer_bit = 0,
+        .clockevent_rating = 125,
+        .clocksource_rating = 125,
+};
+
+static struct resource cmt10_resources[] = {
+        [0] = {
+                .name   = "CMT10",
+                .start  = 0xe6138010,
+                .end    = 0xe613801b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0xb00), /* CMT1_CMT10 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt10_device = {
+        .name           = "sh_cmt",
+        .id             = 10,
+        .dev = {
+                .platform_data  = &cmt10_platform_data,
+        },
+        .resource       = cmt10_resources,
+        .num_resources  = ARRAY_SIZE(cmt10_resources),
+};
+
+static struct platform_device *sh7367_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &cmt10_device,
+};
+
+void __init sh7367_add_standard_devices(void)
+{
+        platform_add_devices(sh7367_early_devices,
+                             ARRAY_SIZE(sh7367_early_devices));
+}
+
+#define SYMSTPCR2 0xe6158048
+#define SYMSTPCR2_CMT1 (1 << 29)
+
+void __init sh7367_add_early_devices(void)
+{
+        /* enable clock to CMT1 */
+        __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
+
+        early_platform_add_devices(sh7367_early_devices,
+                                   ARRAY_SIZE(sh7367_early_devices));
+}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
new file mode 100644
index 000000000000..ff0494f3d00c
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -0,0 +1,638 @@
+/*
+ * sh7372 processor support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_timer.h>
+#include <mach/hardware.h>
+#include <mach/sh7372.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/* SCIFA0 */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xe6c40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
+                            evt2irq(0x0c00), evt2irq(0x0c00) },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+/* SCIFA1 */
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xe6c50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
+                            evt2irq(0x0c20), evt2irq(0x0c20) },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+/* SCIFA2 */
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xe6c60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
+                            evt2irq(0x0c40), evt2irq(0x0c40) },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+/* SCIFA3 */
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xe6c70000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
+                            evt2irq(0x0c60), evt2irq(0x0c60) },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+/* SCIFA4 */
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xe6c80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
+                            evt2irq(0x0d20), evt2irq(0x0d20) },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+/* SCIFA5 */
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xe6cb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
+                            evt2irq(0x0d40), evt2irq(0x0d40) },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+/* SCIFB */
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xe6c30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFB,
+        .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
+                            evt2irq(0x0d60), evt2irq(0x0d60) },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+/* CMT */
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .channel_offset = 0x10,
+        .timer_bit = 0,
+        .clockevent_rating = 125,
+        .clocksource_rating = 125,
+};
+
+static struct resource cmt10_resources[] = {
+        [0] = {
+                .name   = "CMT10",
+                .start  = 0xe6138010,
+                .end    = 0xe613801b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0b00), /* CMT1_CMT10 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt10_device = {
+        .name           = "sh_cmt",
+        .id             = 10,
+        .dev = {
+                .platform_data  = &cmt10_platform_data,
+        },
+        .resource       = cmt10_resources,
+        .num_resources  = ARRAY_SIZE(cmt10_resources),
+};
+
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+        .name = "TMU00",
+        .channel_offset = 0x4,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+        [0] = {
+                .name   = "TMU00",
+                .start  = 0xfff60008,
+                .end    = 0xfff60013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu00_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu00_platform_data,
+        },
+        .resource       = tmu00_resources,
+        .num_resources  = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+        .name = "TMU01",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+        [0] = {
+                .name   = "TMU01",
+                .start  = 0xfff60014,
+                .end    = 0xfff6001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu01_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu01_platform_data,
+        },
+        .resource       = tmu01_resources,
+        .num_resources  = ARRAY_SIZE(tmu01_resources),
+};
+
+/* I2C */
+static struct resource iic0_resources[] = {
+        [0] = {
+                .name   = "IIC0",
+                .start  = 0xFFF20000,
+                .end    = 0xFFF20425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
+                .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device iic0_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 0, /* "i2c0" clock */
+        .num_resources  = ARRAY_SIZE(iic0_resources),
+        .resource       = iic0_resources,
+};
+
+static struct resource iic1_resources[] = {
+        [0] = {
+                .name   = "IIC1",
+                .start  = 0xE6C20000,
+                .end    = 0xE6C20425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x780), /* IIC1_ALI1 */
+                .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device iic1_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 1, /* "i2c1" clock */
+        .num_resources  = ARRAY_SIZE(iic1_resources),
+        .resource       = iic1_resources,
+};
+
+/* DMA */
+/* Transmit sizes and respective CHCR register values */
+enum {
+        XMIT_SZ_8BIT            = 0,
+        XMIT_SZ_16BIT           = 1,
+        XMIT_SZ_32BIT           = 2,
+        XMIT_SZ_64BIT           = 7,
+        XMIT_SZ_128BIT          = 3,
+        XMIT_SZ_256BIT          = 4,
+        XMIT_SZ_512BIT          = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_64BIT]         = 3,    \
+        [XMIT_SZ_128BIT]        = 4,    \
+        [XMIT_SZ_256BIT]        = 5,    \
+        [XMIT_SZ_512BIT]        = 6,    \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
+                         (((i) & 0xc) << (20 - 2)))
+
+static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF0_TX,
+                .addr           = 0xe6c40020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF0_RX,
+                .addr           = 0xe6c40024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_TX,
+                .addr           = 0xe6c50020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x25,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_RX,
+                .addr           = 0xe6c50024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x26,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+                .addr           = 0xe6c60020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+                .addr           = 0xe6c60024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+                .addr           = 0xe6c70020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2d,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+                .addr           = 0xe6c70024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2e,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+                .addr           = 0xe6c80020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x39,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+                .addr           = 0xe6c80024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x3a,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF5_TX,
+                .addr           = 0xe6cb0020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x35,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF5_RX,
+                .addr           = 0xe6cb0024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x36,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF6_TX,
+                .addr           = 0xe6c30040,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x3d,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF6_RX,
+                .addr           = 0xe6c30060,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x3e,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+                .addr           = 0xe6850030,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+                .addr           = 0xe6850030,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_TX,
+                .addr           = 0xe6860030,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc9,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_RX,
+                .addr           = 0xe6860030,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xca,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI2_TX,
+                .addr           = 0xe6870030,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xcd,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI2_RX,
+                .addr           = 0xe6870030,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xce,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0xe6bd0034,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0xe6bd0034,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
+        },
+};
+
+static const struct sh_dmae_channel sh7372_dmae_channels[] = {
+        {
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma_platform_data = {
+        .slave          = sh7372_dmae_slaves,
+        .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
+        .channel        = sh7372_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
+        .ts_low_shift   = 3,
+        .ts_low_mask    = 0x18,
+        .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
+        .ts_high_mask   = 0x00300000,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_DME,
+};
+
+/* Resource order important! */
+static struct resource sh7372_dmae0_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe008020,
+                .end    = 0xfe00808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe009000,
+                .end    = 0xfe00900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = evt2irq(0x20c0),
+                .end    = evt2irq(0x20c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x2000),
+                .end    = evt2irq(0x20a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* Resource order important! */
+static struct resource sh7372_dmae1_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe018020,
+                .end    = 0xfe01808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe019000,
+                .end    = 0xfe01900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = evt2irq(0x21c0),
+                .end    = evt2irq(0x21c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x2100),
+                .end    = evt2irq(0x21a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* Resource order important! */
+static struct resource sh7372_dmae2_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe028020,
+                .end    = 0xfe02808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe029000,
+                .end    = 0xfe02900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = evt2irq(0x22c0),
+                .end    = evt2irq(0x22c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x2200),
+                .end    = evt2irq(0x22a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7372_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7372_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+};
+
+static struct platform_device dma2_device = {
+        .name           = "sh-dma-engine",
+        .id             = 2,
+        .resource       = sh7372_dmae2_resources,
+        .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+};
+
+static struct platform_device *sh7372_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &cmt10_device,
+        &tmu00_device,
+        &tmu01_device,
+};
+
+static struct platform_device *sh7372_late_devices[] __initdata = {
+        &iic0_device,
+        &iic1_device,
+        &dma0_device,
+        &dma1_device,
+        &dma2_device,
+};
+
+void __init sh7372_add_standard_devices(void)
+{
+        platform_add_devices(sh7372_early_devices,
+                            ARRAY_SIZE(sh7372_early_devices));
+
+        platform_add_devices(sh7372_late_devices,
+                            ARRAY_SIZE(sh7372_late_devices));
+}
+
+void __init sh7372_add_early_devices(void)
+{
+        early_platform_add_devices(sh7372_early_devices,
+                                   ARRAY_SIZE(sh7372_early_devices));
+}
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
new file mode 100644
index 000000000000..8099b0b8a934
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -0,0 +1,246 @@
+/*
+ * sh7377 processor support
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_timer.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/* SCIFA0 */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xe6c40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
+                            evt2irq(0xc00), evt2irq(0xc00) },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+/* SCIFA1 */
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xe6c50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
+                            evt2irq(0xc20), evt2irq(0xc20) },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+/* SCIFA2 */
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xe6c60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
+                            evt2irq(0xc40), evt2irq(0xc40) },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+/* SCIFA3 */
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xe6c70000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
+                            evt2irq(0xc60), evt2irq(0xc60) },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+/* SCIFA4 */
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xe6c80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
+                            evt2irq(0xd20), evt2irq(0xd20) },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+/* SCIFA5 */
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xe6cb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
+                            evt2irq(0xd40), evt2irq(0xd40) },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+/* SCIFA6 */
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xe6cc0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
+                            intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+/* SCIFB */
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xe6c30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
+                            evt2irq(0xd60), evt2irq(0xd60) },
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
+        .dev            = {
+                .platform_data  = &scif7_platform_data,
+        },
+};
+
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .channel_offset = 0x10,
+        .timer_bit = 0,
+        .clockevent_rating = 125,
+        .clocksource_rating = 125,
+};
+
+static struct resource cmt10_resources[] = {
+        [0] = {
+                .name   = "CMT10",
+                .start  = 0xe6138010,
+                .end    = 0xe613801b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0xb00), /* CMT1_CMT10 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt10_device = {
+        .name           = "sh_cmt",
+        .id             = 10,
+        .dev = {
+                .platform_data  = &cmt10_platform_data,
+        },
+        .resource       = cmt10_resources,
+        .num_resources  = ARRAY_SIZE(cmt10_resources),
+};
+
+static struct platform_device *sh7377_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &cmt10_device,
+};
+
+void __init sh7377_add_standard_devices(void)
+{
+        platform_add_devices(sh7377_early_devices,
+                            ARRAY_SIZE(sh7377_early_devices));
+}
+
+#define SMSTPCR3 0xe615013c
+#define SMSTPCR3_CMT1 (1 << 29)
+
+void __init sh7377_add_early_devices(void)
+{
+        /* enable clock to CMT1 */
+        __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
+
+        early_platform_add_devices(sh7377_early_devices,
+                                   ARRAY_SIZE(sh7377_early_devices));
+}
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
new file mode 100644
index 000000000000..685c40a2f5e6
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -0,0 +1,430 @@
+/*
+ * sh73a0 processor support
+ *
+ * Copyright (C) 2010  Takashi Yoshii
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_timer.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xe6c40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(72), gic_spi(72),
+                            gic_spi(72), gic_spi(72) },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xe6c50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(73), gic_spi(73),
+                            gic_spi(73), gic_spi(73) },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xe6c60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(74), gic_spi(74),
+                            gic_spi(74), gic_spi(74) },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xe6c70000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(75), gic_spi(75),
+                            gic_spi(75), gic_spi(75) },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xe6c80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(78), gic_spi(78),
+                            gic_spi(78), gic_spi(78) },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xe6cb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(79), gic_spi(79),
+                            gic_spi(79), gic_spi(79) },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xe6cc0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(156), gic_spi(156),
+                            gic_spi(156), gic_spi(156) },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xe6cd0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(143), gic_spi(143),
+                            gic_spi(143), gic_spi(143) },
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
+        .dev            = {
+                .platform_data  = &scif7_platform_data,
+        },
+};
+
+static struct plat_sci_port scif8_platform_data = {
+        .mapbase        = 0xe6c30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIFB,
+        .irqs           = { gic_spi(80), gic_spi(80),
+                            gic_spi(80), gic_spi(80) },
+};
+
+static struct platform_device scif8_device = {
+        .name           = "sh-sci",
+        .id             = 8,
+        .dev            = {
+                .platform_data  = &scif8_platform_data,
+        },
+};
+
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .channel_offset = 0x10,
+        .timer_bit = 0,
+        .clockevent_rating = 125,
+        .clocksource_rating = 125,
+};
+
+static struct resource cmt10_resources[] = {
+        [0] = {
+                .name   = "CMT10",
+                .start  = 0xe6138010,
+                .end    = 0xe613801b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(65),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt10_device = {
+        .name           = "sh_cmt",
+        .id             = 10,
+        .dev = {
+                .platform_data  = &cmt10_platform_data,
+        },
+        .resource       = cmt10_resources,
+        .num_resources  = ARRAY_SIZE(cmt10_resources),
+};
+
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+        .name = "TMU00",
+        .channel_offset = 0x4,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+        [0] = {
+                .name   = "TMU00",
+                .start  = 0xfff60008,
+                .end    = 0xfff60013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu00_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu00_platform_data,
+        },
+        .resource       = tmu00_resources,
+        .num_resources  = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+        .name = "TMU01",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+        [0] = {
+                .name   = "TMU01",
+                .start  = 0xfff60014,
+                .end    = 0xfff6001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu01_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu01_platform_data,
+        },
+        .resource       = tmu01_resources,
+        .num_resources  = ARRAY_SIZE(tmu01_resources),
+};
+
+static struct resource i2c0_resources[] = {
+        [0] = {
+                .name   = "IIC0",
+                .start  = 0xe6820000,
+                .end    = 0xe6820425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(167),
+                .end    = gic_spi(170),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c1_resources[] = {
+        [0] = {
+                .name   = "IIC1",
+                .start  = 0xe6822000,
+                .end    = 0xe6822425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(51),
+                .end    = gic_spi(54),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c2_resources[] = {
+        [0] = {
+                .name   = "IIC2",
+                .start  = 0xe6824000,
+                .end    = 0xe6824425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(171),
+                .end    = gic_spi(174),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c3_resources[] = {
+        [0] = {
+                .name   = "IIC3",
+                .start  = 0xe6826000,
+                .end    = 0xe6826425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(183),
+                .end    = gic_spi(186),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c4_resources[] = {
+        [0] = {
+                .name   = "IIC4",
+                .start  = 0xe6828000,
+                .end    = 0xe6828425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(187),
+                .end    = gic_spi(190),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c0_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 0,
+        .resource       = i2c0_resources,
+        .num_resources  = ARRAY_SIZE(i2c0_resources),
+};
+
+static struct platform_device i2c1_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 1,
+        .resource       = i2c1_resources,
+        .num_resources  = ARRAY_SIZE(i2c1_resources),
+};
+
+static struct platform_device i2c2_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 2,
+        .resource       = i2c2_resources,
+        .num_resources  = ARRAY_SIZE(i2c2_resources),
+};
+
+static struct platform_device i2c3_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 3,
+        .resource       = i2c3_resources,
+        .num_resources  = ARRAY_SIZE(i2c3_resources),
+};
+
+static struct platform_device i2c4_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 4,
+        .resource       = i2c4_resources,
+        .num_resources  = ARRAY_SIZE(i2c4_resources),
+};
+
+static struct platform_device *sh73a0_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &scif8_device,
+        &cmt10_device,
+        &tmu00_device,
+        &tmu01_device,
+};
+
+static struct platform_device *sh73a0_late_devices[] __initdata = {
+        &i2c0_device,
+        &i2c1_device,
+        &i2c2_device,
+        &i2c3_device,
+        &i2c4_device,
+};
+
+void __init sh73a0_add_standard_devices(void)
+{
+        platform_add_devices(sh73a0_early_devices,
+                            ARRAY_SIZE(sh73a0_early_devices));
+        platform_add_devices(sh73a0_late_devices,
+                            ARRAY_SIZE(sh73a0_late_devices));
+}
+
+void __init sh73a0_add_early_devices(void)
+{
+        early_platform_add_devices(sh73a0_early_devices,
+                                   ARRAY_SIZE(sh73a0_early_devices));
+}
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
new file mode 100644
index 000000000000..a156d2108df1
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -0,0 +1,97 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2010  Takashi Yoshii
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/gic.h>
+
+#define WUPCR           0xe6151010
+#define SRESCR          0xe6151018
+#define PSTR            0xe6151040
+#define SBAR            0xe6180020
+#define APARMBAREA      0xe6f10020
+
+static void __iomem *scu_base_addr(void)
+{
+        return (void __iomem *)0xf0000000;
+}
+
+static DEFINE_SPINLOCK(scu_lock);
+static unsigned long tmp;
+
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+        void __iomem *scu_base = scu_base_addr();
+
+        spin_lock(&scu_lock);
+        tmp = __raw_readl(scu_base + 8);
+        tmp &= ~clr;
+        tmp |= set;
+        spin_unlock(&scu_lock);
+
+        /* disable cache coherency after releasing the lock */
+        __raw_writel(tmp, scu_base + 8);
+}
+
+unsigned int __init sh73a0_get_core_count(void)
+{
+        void __iomem *scu_base = scu_base_addr();
+
+        return scu_get_core_count(scu_base);
+}
+
+void __cpuinit sh73a0_secondary_init(unsigned int cpu)
+{
+        gic_secondary_init(0);
+}
+
+int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
+{
+        /* enable cache coherency */
+        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+
+        if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
+                __raw_writel(1 << cpu, __io(WUPCR));    /* wake up */
+        else
+                __raw_writel(1 << cpu, __io(SRESCR));   /* reset */
+
+        return 0;
+}
+
+void __init sh73a0_smp_prepare_cpus(void)
+{
+#ifdef CONFIG_HAVE_ARM_TWD
+        twd_base = (void __iomem *)0xf0000600;
+#endif
+
+        scu_enable(scu_base_addr());
+
+        /* Map the reset vector (in headsmp.S) */
+        __raw_writel(0, __io(APARMBAREA));      /* 4k */
+        __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
+
+        /* enable cache coherency on CPU0 */
+        modify_scu_cpu_psr(0, 3 << (0 * 8));
+}
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
new file mode 100644
index 000000000000..895794b543cd
--- /dev/null
+++ b/arch/arm/mach-shmobile/timer.c
@@ -0,0 +1,46 @@
+/*
+ * SH-Mobile Timer
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2002 - 2009  Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/time.h>
+
+static void __init shmobile_late_time_init(void)
+{
+        /*
+         * Make sure all compiled-in early timers register themselves.
+         *
+         * Run probe() for two "earlytimer" devices, these will be the
+         * clockevents and clocksource devices respectively. In the event
+         * that only a clockevents device is available, we -ENODEV on the
+         * clocksource and the jiffies clocksource is used transparently
+         * instead. No error handling is necessary here.
+         */
+        early_platform_driver_register_all("earlytimer");
+        early_platform_driver_probe("earlytimer", 2, 0);
+}
+
+static void __init shmobile_timer_init(void)
+{
+        late_time_init = shmobile_late_time_init;
+}
+
+struct sys_timer shmobile_timer = {
+        .init           = shmobile_timer_init,
+};