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authorSimon Horman <horms+renesas@verge.net.au>2013-04-01 22:08:34 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-04-01 22:08:34 -0400
commit809609a5d8427b0025304dbb69a84a692d11c4f9 (patch)
tree95a544cda32d36e4a9ee1ce27c527406c54d91b4 /arch/arm/mach-shmobile
parenta4339a9cb46644e19278e4dd5d89b262a37cb0b0 (diff)
parent8585deb18580d04209a2986430aa0959ef38fce2 (diff)
Merge branch 'soc' into pinmux-base
Conflicts: drivers/pinctrl/sh-pfc/pfc-r8a7740.c This merge is to provide r8a73a4 SoC files, which are added in the soc branch and depended on by r8a73a4 pfc-changes which are to be added to the pinmux branch.
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/Kconfig28
-rw-r--r--arch/arm/mach-shmobile/Makefile10
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c35
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c14
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c115
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c127
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c104
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c200
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c93
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c50
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c122
-rw-r--r--arch/arm/mach-shmobile/clock.c13
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S (renamed from arch/arm/mach-shmobile/headsmp-sh73a0.S)15
-rw-r--r--arch/arm/mach-shmobile/hotplug.c68
-rw-r--r--arch/arm/mach-shmobile/include/mach/clock.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h64
-rw-r--r--arch/arm/mach-shmobile/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a73a4.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h28
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h13
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7790.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h12
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h15
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c641
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c78
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c125
-rw-r--r--arch/arm/mach-shmobile/setup-emev2.c4
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c202
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c192
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c193
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c104
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c137
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c162
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c86
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c129
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c36
37 files changed, 1866 insertions, 1418 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9255546e7bf6..ff674c5f2d03 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -16,12 +16,30 @@ config ARCH_SH73A0
16 select CPU_V7 16 select CPU_V7
17 select I2C 17 select I2C
18 select SH_CLK_CPG 18 select SH_CLK_CPG
19 select RENESAS_INTC_IRQPIN
20
21config ARCH_R8A73A4
22 bool "R-Mobile APE6 (R8A73A40)"
23 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select ARM_GIC
25 select CPU_V7
26 select ARM_ARCH_TIMER
27 select SH_CLK_CPG
28 select RENESAS_IRQC
19 29
20config ARCH_R8A7740 30config ARCH_R8A7740
21 bool "R-Mobile A1 (R8A77400)" 31 bool "R-Mobile A1 (R8A77400)"
22 select ARCH_WANT_OPTIONAL_GPIOLIB 32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select ARM_GIC
23 select CPU_V7 34 select CPU_V7
24 select SH_CLK_CPG 35 select SH_CLK_CPG
36 select RENESAS_INTC_IRQPIN
37
38config ARCH_R8A7778
39 bool "R-Car M1 (R8A77780)"
40 select CPU_V7
41 select SH_CLK_CPG
42 select ARM_GIC
25 43
26config ARCH_R8A7779 44config ARCH_R8A7779
27 bool "R-Car H1 (R8A77790)" 45 bool "R-Car H1 (R8A77790)"
@@ -31,6 +49,16 @@ config ARCH_R8A7779
31 select SH_CLK_CPG 49 select SH_CLK_CPG
32 select USB_ARCH_HAS_EHCI 50 select USB_ARCH_HAS_EHCI
33 select USB_ARCH_HAS_OHCI 51 select USB_ARCH_HAS_OHCI
52 select RENESAS_INTC_IRQPIN
53
54config ARCH_R8A7790
55 bool "R-Car H2 (R8A77900)"
56 select ARCH_WANT_OPTIONAL_GPIOLIB
57 select ARM_GIC
58 select CPU_V7
59 select ARM_ARCH_TIMER
60 select SH_CLK_CPG
61 select RENESAS_IRQC
34 62
35config ARCH_EMEV2 63config ARCH_EMEV2
36 bool "Emma Mobile EV2" 64 bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e1fac57514b9..709b9b421f93 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -8,16 +8,18 @@ obj-y := timer.o console.o clock.o
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o 12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
12obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o 14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
13obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o 16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
14 17
15# SMP objects 18# SMP objects
16smp-y := platsmp.o headsmp.o 19smp-y := platsmp.o headsmp.o
17smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o 20smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o
18smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o 21smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o
19smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o 22smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o
20smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
21 23
22# IRQ objects 24# IRQ objects
23obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 25obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 04eff93df793..9415cb4e6199 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -146,7 +146,7 @@
146 * see 146 * see
147 * usbhsf_power_ctrl() 147 * usbhsf_power_ctrl()
148 */ 148 */
149#define IRQ7 evt2irq(0x02e0) 149#define IRQ7 irq_pin(7)
150#define USBCR1 IOMEM(0xe605810a) 150#define USBCR1 IOMEM(0xe605810a)
151#define USBH 0xC6700000 151#define USBH 0xC6700000
152#define USBH_USBCTR 0x10834 152#define USBH_USBCTR 0x10834
@@ -331,7 +331,7 @@ static struct resource usbhsf_resources[] = {
331 .flags = IORESOURCE_MEM, 331 .flags = IORESOURCE_MEM,
332 }, 332 },
333 { 333 {
334 .start = evt2irq(0x0A20), 334 .start = gic_spi(51),
335 .flags = IORESOURCE_IRQ, 335 .flags = IORESOURCE_IRQ,
336 }, 336 },
337}; 337};
@@ -364,7 +364,7 @@ static struct resource sh_eth_resources[] = {
364 .end = 0xe9a02000 - 1, 364 .end = 0xe9a02000 - 1,
365 .flags = IORESOURCE_MEM, 365 .flags = IORESOURCE_MEM,
366 }, { 366 }, {
367 .start = evt2irq(0x0500), 367 .start = gic_spi(110),
368 .flags = IORESOURCE_IRQ, 368 .flags = IORESOURCE_IRQ,
369 }, 369 },
370}; 370};
@@ -418,7 +418,7 @@ static struct resource lcdc0_resources[] = {
418 .flags = IORESOURCE_MEM, 418 .flags = IORESOURCE_MEM,
419 }, 419 },
420 [1] = { 420 [1] = {
421 .start = intcs_evt2irq(0x580), 421 .start = gic_spi(177),
422 .flags = IORESOURCE_IRQ, 422 .flags = IORESOURCE_IRQ,
423 }, 423 },
424}; 424};
@@ -453,7 +453,7 @@ static struct resource hdmi_resources[] = {
453 .flags = IORESOURCE_MEM, 453 .flags = IORESOURCE_MEM,
454 }, 454 },
455 [1] = { 455 [1] = {
456 .start = evt2irq(0x1700), 456 .start = gic_spi(131),
457 .flags = IORESOURCE_IRQ, 457 .flags = IORESOURCE_IRQ,
458 }, 458 },
459 [2] = { 459 [2] = {
@@ -515,7 +515,7 @@ static struct resource hdmi_lcdc_resources[] = {
515 .flags = IORESOURCE_MEM, 515 .flags = IORESOURCE_MEM,
516 }, 516 },
517 [1] = { 517 [1] = {
518 .start = intcs_evt2irq(0x1780), 518 .start = gic_spi(178),
519 .flags = IORESOURCE_IRQ, 519 .flags = IORESOURCE_IRQ,
520 }, 520 },
521}; 521};
@@ -575,7 +575,7 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
575 * We can use IRQ31 as card detect irq, 575 * We can use IRQ31 as card detect irq,
576 * but it needs chattering removal operation 576 * but it needs chattering removal operation
577 */ 577 */
578#define IRQ31 evt2irq(0x33E0) 578#define IRQ31 irq_pin(31)
579static struct sh_mobile_sdhi_info sdhi0_info = { 579static struct sh_mobile_sdhi_info sdhi0_info = {
580 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 580 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
581 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 581 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -597,12 +597,12 @@ static struct resource sdhi0_resources[] = {
597 */ 597 */
598 { 598 {
599 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 599 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
600 .start = evt2irq(0x0E20), 600 .start = gic_spi(118),
601 .flags = IORESOURCE_IRQ, 601 .flags = IORESOURCE_IRQ,
602 }, 602 },
603 { 603 {
604 .name = SH_MOBILE_SDHI_IRQ_SDIO, 604 .name = SH_MOBILE_SDHI_IRQ_SDIO,
605 .start = evt2irq(0x0E40), 605 .start = gic_spi(119),
606 .flags = IORESOURCE_IRQ, 606 .flags = IORESOURCE_IRQ,
607 }, 607 },
608}; 608};
@@ -634,15 +634,15 @@ static struct resource sdhi1_resources[] = {
634 .flags = IORESOURCE_MEM, 634 .flags = IORESOURCE_MEM,
635 }, 635 },
636 [1] = { 636 [1] = {
637 .start = evt2irq(0x0E80), 637 .start = gic_spi(121),
638 .flags = IORESOURCE_IRQ, 638 .flags = IORESOURCE_IRQ,
639 }, 639 },
640 [2] = { 640 [2] = {
641 .start = evt2irq(0x0EA0), 641 .start = gic_spi(122),
642 .flags = IORESOURCE_IRQ, 642 .flags = IORESOURCE_IRQ,
643 }, 643 },
644 [3] = { 644 [3] = {
645 .start = evt2irq(0x0EC0), 645 .start = gic_spi(123),
646 .flags = IORESOURCE_IRQ, 646 .flags = IORESOURCE_IRQ,
647 }, 647 },
648}; 648};
@@ -686,12 +686,12 @@ static struct resource sh_mmcif_resources[] = {
686 }, 686 },
687 [1] = { 687 [1] = {
688 /* MMC ERR */ 688 /* MMC ERR */
689 .start = evt2irq(0x1AC0), 689 .start = gic_spi(56),
690 .flags = IORESOURCE_IRQ, 690 .flags = IORESOURCE_IRQ,
691 }, 691 },
692 [2] = { 692 [2] = {
693 /* MMC NOR */ 693 /* MMC NOR */
694 .start = evt2irq(0x1AE0), 694 .start = gic_spi(57),
695 .flags = IORESOURCE_IRQ, 695 .flags = IORESOURCE_IRQ,
696 }, 696 },
697}; 697};
@@ -768,7 +768,7 @@ static struct resource ceu0_resources[] = {
768 .flags = IORESOURCE_MEM, 768 .flags = IORESOURCE_MEM,
769 }, 769 },
770 [1] = { 770 [1] = {
771 .start = intcs_evt2irq(0x0500), 771 .start = gic_spi(160),
772 .flags = IORESOURCE_IRQ, 772 .flags = IORESOURCE_IRQ,
773 }, 773 },
774 [2] = { 774 [2] = {
@@ -810,7 +810,7 @@ static struct resource fsi_resources[] = {
810 .flags = IORESOURCE_MEM, 810 .flags = IORESOURCE_MEM,
811 }, 811 },
812 [1] = { 812 [1] = {
813 .start = evt2irq(0x1840), 813 .start = gic_spi(9),
814 .flags = IORESOURCE_IRQ, 814 .flags = IORESOURCE_IRQ,
815 }, 815 },
816}; 816};
@@ -893,7 +893,7 @@ static struct platform_device i2c_gpio_device = {
893static struct i2c_board_info i2c0_devices[] = { 893static struct i2c_board_info i2c0_devices[] = {
894 { 894 {
895 I2C_BOARD_INFO("st1232-ts", 0x55), 895 I2C_BOARD_INFO("st1232-ts", 0x55),
896 .irq = evt2irq(0x0340), 896 .irq = irq_pin(10),
897 }, 897 },
898 { 898 {
899 I2C_BOARD_INFO("wm8978", 0x1a), 899 I2C_BOARD_INFO("wm8978", 0x1a),
@@ -1183,7 +1183,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1183 .map_io = r8a7740_map_io, 1183 .map_io = r8a7740_map_io,
1184 .init_early = eva_add_early_devices, 1184 .init_early = eva_add_early_devices,
1185 .init_irq = r8a7740_init_irq, 1185 .init_irq = r8a7740_init_irq,
1186 .handle_irq = shmobile_handle_irq_intc,
1187 .init_machine = eva_init, 1186 .init_machine = eva_init,
1188 .init_late = shmobile_init_late, 1187 .init_late = shmobile_init_late,
1189 .init_time = eva_earlytimer_init, 1188 .init_time = eva_earlytimer_init,
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index c1c0401ff6a4..446d04db404f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -83,7 +83,7 @@ static struct resource smsc9221_resources[] = {
83 .flags = IORESOURCE_MEM, 83 .flags = IORESOURCE_MEM,
84 }, 84 },
85 [1] = { 85 [1] = {
86 .start = intcs_evt2irq(0x260), /* IRQ3 */ 86 .start = irq_pin(3), /* IRQ3 */
87 .flags = IORESOURCE_IRQ, 87 .flags = IORESOURCE_IRQ,
88 }, 88 },
89}; 89};
@@ -117,7 +117,7 @@ static struct resource usb_resources[] = {
117 .flags = IORESOURCE_MEM, 117 .flags = IORESOURCE_MEM,
118 }, 118 },
119 [1] = { 119 [1] = {
120 .start = intcs_evt2irq(0x220), /* IRQ1 */ 120 .start = irq_pin(1), /* IRQ1 */
121 .flags = IORESOURCE_IRQ, 121 .flags = IORESOURCE_IRQ,
122 }, 122 },
123}; 123};
@@ -140,7 +140,7 @@ struct usbhs_private {
140 struct renesas_usbhs_platform_info info; 140 struct renesas_usbhs_platform_info info;
141}; 141};
142 142
143#define IRQ15 intcs_evt2irq(0x03e0) 143#define IRQ15 irq_pin(15)
144#define USB_PHY_MODE (1 << 4) 144#define USB_PHY_MODE (1 << 4)
145#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) 145#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
146#define USB_PHY_ON (1 << 1) 146#define USB_PHY_ON (1 << 1)
@@ -565,25 +565,25 @@ static struct i2c_board_info i2c0_devices[] = {
565 }, 565 },
566 { 566 {
567 I2C_BOARD_INFO("ak8975", 0x0c), 567 I2C_BOARD_INFO("ak8975", 0x0c),
568 .irq = intcs_evt2irq(0x3380), /* IRQ28 */ 568 .irq = irq_pin(28), /* IRQ28 */
569 }, 569 },
570 { 570 {
571 I2C_BOARD_INFO("adxl34x", 0x1d), 571 I2C_BOARD_INFO("adxl34x", 0x1d),
572 .irq = intcs_evt2irq(0x3340), /* IRQ26 */ 572 .irq = irq_pin(26), /* IRQ26 */
573 }, 573 },
574}; 574};
575 575
576static struct i2c_board_info i2c1_devices[] = { 576static struct i2c_board_info i2c1_devices[] = {
577 { 577 {
578 I2C_BOARD_INFO("st1232-ts", 0x55), 578 I2C_BOARD_INFO("st1232-ts", 0x55),
579 .irq = intcs_evt2irq(0x300), /* IRQ8 */ 579 .irq = irq_pin(8), /* IRQ8 */
580 }, 580 },
581}; 581};
582 582
583static struct i2c_board_info i2c3_devices[] = { 583static struct i2c_board_info i2c3_devices[] = {
584 { 584 {
585 I2C_BOARD_INFO("pcf8575", 0x20), 585 I2C_BOARD_INFO("pcf8575", 0x20),
586 .irq = intcs_evt2irq(0x3260), /* IRQ19 */ 586 .irq = irq_pin(19), /* IRQ19 */
587 .platform_data = &pcf8575_pdata, 587 .platform_data = &pcf8575_pdata,
588 }, 588 },
589}; 589};
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
new file mode 100644
index 000000000000..e710c00c3822
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -0,0 +1,115 @@
1/*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x270
29
30#define MPCKCR 0xe6150080
31#define SMSTPCR2 0xe6150138
32#define SMSTPCR5 0xe6150144
33
34static struct clk_mapping cpg_mapping = {
35 .phys = CPG_BASE,
36 .len = CPG_LEN,
37};
38
39static struct clk extalr_clk = {
40 .rate = 32768,
41 .mapping = &cpg_mapping,
42};
43
44static struct clk extal1_clk = {
45 .rate = 26000000,
46 .mapping = &cpg_mapping,
47};
48
49static struct clk extal2_clk = {
50 .rate = 48000000,
51 .mapping = &cpg_mapping,
52};
53
54static struct clk *main_clks[] = {
55 &extalr_clk,
56 &extal1_clk,
57 &extal2_clk,
58};
59
60enum {
61 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
62 MSTP522,
63 MSTP_NR
64};
65
66static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
68 [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
69 [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
70 [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
71 [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
72 [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
73 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
74};
75
76static struct clk_lookup lookups[] = {
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
80 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
81 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
82 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
83 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
84
85 /* for DT */
86 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
87};
88
89void __init r8a73a4_clock_init(void)
90{
91 void __iomem *cpg_base, *reg;
92 int k, ret = 0;
93
94 /* fix MPCLK to EXTAL2 for now.
95 * this is needed until more detailed clock topology is supported
96 */
97 cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
98 BUG_ON(!cpg_base);
99 reg = cpg_base + (MPCKCR - CPG_BASE);
100 iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
101 iounmap(cpg_base);
102
103 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
104 ret = clk_register(main_clks[k]);
105
106 if (!ret)
107 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
108
109 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
110
111 if (!ret)
112 shmobile_clk_init();
113 else
114 panic("failed to setup r8a73a4 clocks\n");
115}
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 19ce885a3b43..c0d39aa6de50 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/sh_clk.h> 23#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/r8a7740.h> 27#include <mach/r8a7740.h>
27 28
@@ -97,42 +98,13 @@ static struct clk dv_clk = {
97 .rate = 27000000, 98 .rate = 27000000,
98}; 99};
99 100
100static unsigned long div_recalc(struct clk *clk) 101SH_CLK_RATIO(div2, 1, 2);
101{ 102SH_CLK_RATIO(div1k, 1, 1024);
102 return clk->parent->rate / (int)(clk->priv);
103}
104
105static struct sh_clk_ops div_clk_ops = {
106 .recalc = div_recalc,
107};
108
109/* extal1 / 2 */
110static struct clk extal1_div2_clk = {
111 .ops = &div_clk_ops,
112 .priv = (void *)2,
113 .parent = &extal1_clk,
114};
115
116/* extal1 / 1024 */
117static struct clk extal1_div1024_clk = {
118 .ops = &div_clk_ops,
119 .priv = (void *)1024,
120 .parent = &extal1_clk,
121};
122
123/* extal1 / 2 / 1024 */
124static struct clk extal1_div2048_clk = {
125 .ops = &div_clk_ops,
126 .priv = (void *)1024,
127 .parent = &extal1_div2_clk,
128};
129 103
130/* extal2 / 2 */ 104SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
131static struct clk extal2_div2_clk = { 105SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
132 .ops = &div_clk_ops, 106SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
133 .priv = (void *)2, 107SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
134 .parent = &extal2_clk,
135};
136 108
137static struct sh_clk_ops followparent_clk_ops = { 109static struct sh_clk_ops followparent_clk_ops = {
138 .recalc = followparent_recalc, 110 .recalc = followparent_recalc,
@@ -143,11 +115,7 @@ static struct clk system_clk = {
143 .ops = &followparent_clk_ops, 115 .ops = &followparent_clk_ops,
144}; 116};
145 117
146static struct clk system_div2_clk = { 118SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
147 .ops = &div_clk_ops,
148 .priv = (void *)2,
149 .parent = &system_clk,
150};
151 119
152/* r_clk */ 120/* r_clk */
153static struct clk r_clk = { 121static struct clk r_clk = {
@@ -184,11 +152,7 @@ static struct clk pllc1_clk = {
184}; 152};
185 153
186/* PLLC1 / 2 */ 154/* PLLC1 / 2 */
187static struct clk pllc1_div2_clk = { 155SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
188 .ops = &div_clk_ops,
189 .priv = (void *)2,
190 .parent = &pllc1_clk,
191};
192 156
193/* USB clock */ 157/* USB clock */
194/* 158/*
@@ -323,6 +287,7 @@ struct clk *main_clks[] = {
323 &fsibck_clk, 287 &fsibck_clk,
324}; 288};
325 289
290/* DIV4 clocks */
326static void div4_kick(struct clk *clk) 291static void div4_kick(struct clk *clk)
327{ 292{
328 unsigned long value; 293 unsigned long value;
@@ -346,6 +311,26 @@ static struct clk_div4_table div4_table = {
346 .kick = div4_kick, 311 .kick = div4_kick,
347}; 312};
348 313
314enum {
315 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
316 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
317 DIV4_NR
318};
319
320struct clk div4_clks[DIV4_NR] = {
321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
326 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
327 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
328 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
330 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
332};
333
349/* DIV6 reparent */ 334/* DIV6 reparent */
350enum { 335enum {
351 DIV6_HDMI, 336 DIV6_HDMI,
@@ -391,6 +376,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
391 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), 376 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
392}; 377};
393 378
379/* DIV6 clocks */
380enum {
381 DIV6_SUB,
382 DIV6_NR
383};
384
385static struct clk div6_clks[DIV6_NR] = {
386 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
387};
388
394/* HDMI1/2 clock */ 389/* HDMI1/2 clock */
395static unsigned long hdmi12_recalc(struct clk *clk) 390static unsigned long hdmi12_recalc(struct clk *clk)
396{ 391{
@@ -456,35 +451,6 @@ static struct clk fsidivs[] = {
456 451
457/* MSTP */ 452/* MSTP */
458enum { 453enum {
459 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
460 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
461 DIV4_NR
462};
463
464struct clk div4_clks[DIV4_NR] = {
465 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
466 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
467 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
468 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
469 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
470 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
471 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
472 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
473 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
474 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
475 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
476};
477
478enum {
479 DIV6_SUB,
480 DIV6_NR
481};
482
483static struct clk div6_clks[DIV6_NR] = {
484 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
485};
486
487enum {
488 MSTP128, MSTP127, MSTP125, 454 MSTP128, MSTP127, MSTP125,
489 MSTP116, MSTP111, MSTP100, MSTP117, 455 MSTP116, MSTP111, MSTP100, MSTP117,
490 456
@@ -593,29 +559,42 @@ static struct clk_lookup lookups[] = {
593 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), 559 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
594 560
595 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), 561 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
562 CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]),
596 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), 563 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
564 CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]),
597 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), 565 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
566 CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]),
598 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 567 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
568 CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]),
599 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 569 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
570 CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]),
600 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), 571 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
572 CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]),
601 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), 573 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
574 CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]),
602 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), 575 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
603 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), 576 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
604 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), 577 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
605 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), 578 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
606 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), 579 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
580 CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]),
607 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), 581 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
582 CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]),
608 583
609 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), 584 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
610 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), 585 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
611 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), 586 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
612 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), 587 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
613 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 588 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
589 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]),
614 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), 590 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
591 CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]),
615 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), 592 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
593 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
616 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), 594 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
617 595
618 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), 596 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
597 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
619 598
620 /* ICK */ 599 /* ICK */
621 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), 600 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
new file mode 100644
index 000000000000..f1277f45381e
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -0,0 +1,104 @@
1/*
2 * r8a7778 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/io.h>
27#include <linux/sh_clk.h>
28#include <linux/clkdev.h>
29#include <mach/common.h>
30
31#define MSTPCR0 IOMEM(0xffc80030)
32#define MSTPCR1 IOMEM(0xffc80034)
33#define MSTPCR3 IOMEM(0xffc8003c)
34#define MSTPSR1 IOMEM(0xffc80044)
35#define MSTPSR4 IOMEM(0xffc80048)
36#define MSTPSR6 IOMEM(0xffc8004c)
37#define MSTPCR4 IOMEM(0xffc80050)
38#define MSTPCR5 IOMEM(0xffc80054)
39#define MSTPCR6 IOMEM(0xffc80058)
40
41/* ioremap() through clock mapping mandatory to avoid
42 * collision with ARM coherent DMA virtual memory range.
43 */
44
45static struct clk_mapping cpg_mapping = {
46 .phys = 0xffc80000,
47 .len = 0x80,
48};
49
50static struct clk clkp = {
51 .rate = 62500000, /* FIXME: shortcut */
52 .flags = CLK_ENABLE_ON_INIT,
53 .mapping = &cpg_mapping,
54};
55
56static struct clk *main_clks[] = {
57 &clkp,
58};
59
60enum {
61 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
62 MSTP016, MSTP015,
63 MSTP_NR };
64
65static struct clk mstp_clks[MSTP_NR] = {
66 [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
67 [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
68 [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
69 [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
70 [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
71 [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
72 [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
73 [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
74};
75
76static struct clk_lookup lookups[] = {
77 /* MSTP32 clocks */
78 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
79 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
80 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
81 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
82 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
83 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
84 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
85 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
86};
87
88void __init r8a7778_clock_init(void)
89{
90 int k, ret = 0;
91
92 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
93 ret = clk_register(main_clks[k]);
94
95 if (!ret)
96 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
97
98 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
99
100 if (!ret)
101 shmobile_clk_init();
102 else
103 panic("failed to setup r8a7778 clocks\n");
104}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1db36537255c..7d86bfbb5b06 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -17,13 +17,17 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <linux/bitops.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <mach/clock.h>
25#include <mach/common.h> 27#include <mach/common.h>
26 28
29#define MD(nr) BIT(nr)
30
27#define FRQMR IOMEM(0xffc80014) 31#define FRQMR IOMEM(0xffc80014)
28#define MSTPCR0 IOMEM(0xffc80030) 32#define MSTPCR0 IOMEM(0xffc80030)
29#define MSTPCR1 IOMEM(0xffc80034) 33#define MSTPCR1 IOMEM(0xffc80034)
@@ -36,6 +40,9 @@
36#define MSTPCR6 IOMEM(0xffc80058) 40#define MSTPCR6 IOMEM(0xffc80058)
37#define MSTPCR7 IOMEM(0xffc80040) 41#define MSTPCR7 IOMEM(0xffc80040)
38 42
43#define MODEMR 0xffcc0020
44
45
39/* ioremap() through clock mapping mandatory to avoid 46/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range. 47 * collision with ARM coherent DMA virtual memory range.
41 */ 48 */
@@ -50,44 +57,44 @@ static struct clk_mapping cpg_mapping = {
50 * from the platform code. 57 * from the platform code.
51 */ 58 */
52static struct clk plla_clk = { 59static struct clk plla_clk = {
53 .rate = 1500000000, 60 /* .rate will be updated on r8a7779_clock_init() */
54 .mapping = &cpg_mapping, 61 .mapping = &cpg_mapping,
55}; 62};
56 63
64/*
65 * clock ratio of these clock will be updated
66 * on r8a7779_clock_init()
67 */
68SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
69SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
70SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
71SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
72SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
73SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
74SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
75SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
76SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
77SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
78SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
79
57static struct clk *main_clks[] = { 80static struct clk *main_clks[] = {
58 &plla_clk, 81 &plla_clk,
59}; 82 &clkz_clk,
60 83 &clkzs_clk,
61static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; 84 &clki_clk,
62 85 &clks_clk,
63static struct clk_div_mult_table div4_div_mult_table = { 86 &clks1_clk,
64 .divisors = divisors, 87 &clks3_clk,
65 .nr_divisors = ARRAY_SIZE(divisors), 88 &clks4_clk,
66}; 89 &clkb_clk,
67 90 &clkout_clk,
68static struct clk_div4_table div4_table = { 91 &clkp_clk,
69 .div_mult_table = &div4_div_mult_table, 92 &clkg_clk,
70};
71
72enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
73
74static struct clk div4_clks[DIV4_NR] = {
75 [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
76 0x0018, CLK_ENABLE_ON_INIT),
77 [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
78 0x0700, CLK_ENABLE_ON_INIT),
79 [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
80 0x0040, CLK_ENABLE_ON_INIT),
81 [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
82 0x0010, CLK_ENABLE_ON_INIT),
83 [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
84 0x0060, CLK_ENABLE_ON_INIT),
85 [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
86 0x0300, CLK_ENABLE_ON_INIT),
87}; 93};
88 94
89enum { MSTP323, MSTP322, MSTP321, MSTP320, 95enum { MSTP323, MSTP322, MSTP321, MSTP320,
90 MSTP101, MSTP100, 96 MSTP115,
97 MSTP103, MSTP101, MSTP100,
91 MSTP030, 98 MSTP030,
92 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 99 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
93 MSTP016, MSTP015, MSTP014, 100 MSTP016, MSTP015, MSTP014,
@@ -95,50 +102,28 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320,
95 MSTP_NR }; 102 MSTP_NR };
96 103
97static struct clk mstp_clks[MSTP_NR] = { 104static struct clk mstp_clks[MSTP_NR] = {
98 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ 105 [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
99 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ 106 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
100 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ 107 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
101 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ 108 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
102 [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ 109 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
103 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ 110 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
104 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ 111 [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */
105 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ 112 [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */
106 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ 113 [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
107 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ 114 [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
108 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ 115 [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
109 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ 116 [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
110 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ 117 [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
111 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ 118 [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
112 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ 119 [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
113 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ 120 [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
114 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ 121 [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
115 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ 122 [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
116 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ 123 [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
117 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ 124 [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
118}; 125 [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
119 126 [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
120static unsigned long mul4_recalc(struct clk *clk)
121{
122 return clk->parent->rate * 4;
123}
124
125static struct sh_clk_ops mul4_clk_ops = {
126 .recalc = mul4_recalc,
127};
128
129struct clk clkz_clk = {
130 .ops = &mul4_clk_ops,
131 .parent = &div4_clks[DIV4_S],
132};
133
134struct clk clkzs_clk = {
135 /* clks x 4 / 4 = clks */
136 .parent = &div4_clks[DIV4_S],
137};
138
139static struct clk *late_main_clks[] = {
140 &clkz_clk,
141 &clkzs_clk,
142}; 127};
143 128
144static struct clk_lookup lookups[] = { 129static struct clk_lookup lookups[] = {
@@ -148,14 +133,16 @@ static struct clk_lookup lookups[] = {
148 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), 133 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
149 134
150 /* DIV4 clocks */ 135 /* DIV4 clocks */
151 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), 136 CLKDEV_CON_ID("shyway_clk", &clks_clk),
152 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), 137 CLKDEV_CON_ID("bus_clk", &clkout_clk),
153 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), 138 CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
154 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), 139 CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
155 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), 140 CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
156 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 141 CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
157 142
158 /* MSTP32 clocks */ 143 /* MSTP32 clocks */
144 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
145 CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
159 CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ 146 CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
160 CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ 147 CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
161 CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ 148 CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
@@ -180,24 +167,65 @@ static struct clk_lookup lookups[] = {
180 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 167 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
181 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 168 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
182 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ 169 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
170 CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
183}; 171};
184 172
185void __init r8a7779_clock_init(void) 173void __init r8a7779_clock_init(void)
186{ 174{
175 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
176 u32 mode;
187 int k, ret = 0; 177 int k, ret = 0;
188 178
179 BUG_ON(!modemr);
180 mode = ioread32(modemr);
181 iounmap(modemr);
182
183 if (mode & MD(1)) {
184 plla_clk.rate = 1500000000;
185
186 SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
187 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
188 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
189 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
190 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
191 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
192 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
193 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
194 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
195 if (mode & MD(2)) {
196 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
197 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
198 } else {
199 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
200 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
201 }
202 } else {
203 plla_clk.rate = 1600000000;
204
205 SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
206 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
207 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
208 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
209 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
210 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
211 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
212 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
213 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
214 if (mode & MD(2)) {
215 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
216 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
217 } else {
218 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
219 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
220 }
221 }
222
189 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 223 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
190 ret = clk_register(main_clks[k]); 224 ret = clk_register(main_clks[k]);
191 225
192 if (!ret) 226 if (!ret)
193 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
194
195 if (!ret)
196 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 227 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
197 228
198 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
199 ret = clk_register(late_main_clks[k]);
200
201 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 229 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
202 230
203 if (!ret) 231 if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
new file mode 100644
index 000000000000..bad9bf2e34d6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -0,0 +1,93 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x1000
29
30#define SMSTPCR2 0xe6150138
31#define SMSTPCR7 0xe615014c
32
33static struct clk_mapping cpg_mapping = {
34 .phys = CPG_BASE,
35 .len = CPG_LEN,
36};
37
38static struct clk p_clk = {
39 .rate = 65000000, /* shortcut for now */
40 .mapping = &cpg_mapping,
41};
42
43static struct clk mp_clk = {
44 .rate = 52000000, /* shortcut for now */
45 .mapping = &cpg_mapping,
46};
47
48static struct clk *main_clks[] = {
49 &p_clk,
50 &mp_clk,
51};
52
53enum { MSTP721, MSTP720,
54 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
55static struct clk mstp_clks[MSTP_NR] = {
56 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
57 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
58 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
59 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
60 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
61 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
62 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
63 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
64};
65
66static struct clk_lookup lookups[] = {
67 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
68 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
69 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
70 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
71 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
72 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
73 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
74 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
75};
76
77void __init r8a7790_clock_init(void)
78{
79 int k, ret = 0;
80
81 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
82 ret = clk_register(main_clks[k]);
83
84 if (!ret)
85 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
86
87 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
88
89 if (!ret)
90 shmobile_clk_init();
91 else
92 panic("failed to setup r8a7790 clocks\n");
93}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 45d21fe317f4..7e105932c09d 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <mach/clock.h>
24#include <mach/common.h> 25#include <mach/common.h>
25 26
26/* SH7372 registers */ 27/* SH7372 registers */
@@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = {
83 .rate = 48000000, 84 .rate = 48000000,
84}; 85};
85 86
86/* A fixed divide-by-2 block */ 87SH_CLK_RATIO(div2, 1, 2);
87static unsigned long div2_recalc(struct clk *clk)
88{
89 return clk->parent->rate / 2;
90}
91
92static struct sh_clk_ops div2_clk_ops = {
93 .recalc = div2_recalc,
94};
95 88
96/* Divide dv_clki by two */ 89SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
97struct clk sh7372_dv_clki_div2_clk = { 90SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
98 .ops = &div2_clk_ops, 91SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
99 .parent = &sh7372_dv_clki_clk, 92SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
100};
101
102/* Divide extal1 by two */
103static struct clk extal1_div2_clk = {
104 .ops = &div2_clk_ops,
105 .parent = &sh7372_extal1_clk,
106};
107
108/* Divide extal2 by two */
109static struct clk extal2_div2_clk = {
110 .ops = &div2_clk_ops,
111 .parent = &sh7372_extal2_clk,
112};
113
114/* Divide extal2 by four */
115static struct clk extal2_div4_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &extal2_div2_clk,
118};
119 93
120/* PLLC0 and PLLC1 */ 94/* PLLC0 and PLLC1 */
121static unsigned long pllc01_recalc(struct clk *clk) 95static unsigned long pllc01_recalc(struct clk *clk)
@@ -147,10 +121,7 @@ static struct clk pllc1_clk = {
147}; 121};
148 122
149/* Divide PLLC1 by two */ 123/* Divide PLLC1 by two */
150static struct clk pllc1_div2_clk = { 124SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
151 .ops = &div2_clk_ops,
152 .parent = &pllc1_clk,
153};
154 125
155/* PLLC2 */ 126/* PLLC2 */
156 127
@@ -342,7 +313,7 @@ static struct clk_div4_table div4_table = {
342}; 313};
343 314
344enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, 315enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
345 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, 316 DIV4_ZX, DIV4_HP,
346 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, 317 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
347 DIV4_DDRP, DIV4_NR }; 318 DIV4_DDRP, DIV4_NR };
348 319
@@ -355,8 +326,6 @@ static struct clk div4_clks[DIV4_NR] = {
355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 326 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), 327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), 328 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
358 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
359 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
360 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), 329 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
361 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), 330 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
362 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), 331 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
@@ -516,8 +485,6 @@ static struct clk_lookup lookups[] = {
516 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), 485 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
517 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), 486 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
518 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), 487 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
519 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
520 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
521 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), 488 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
522 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), 489 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
523 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), 490 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
@@ -654,5 +621,4 @@ void __init sh7372_clock_init(void)
654 shmobile_clk_init(); 621 shmobile_clk_init();
655 else 622 else
656 panic("failed to setup sh7372 clocks\n"); 623 panic("failed to setup sh7372 clocks\n");
657
658} 624}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afa5423a0f93..784fbaa4cc55 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <asm/processor.h>
25#include <mach/clock.h>
24#include <mach/common.h> 26#include <mach/common.h>
25 27
26#define FRQCRA IOMEM(0xe6150000) 28#define FRQCRA IOMEM(0xe6150000)
@@ -82,61 +84,16 @@ struct clk sh73a0_extal2_clk = {
82 .rate = 48000000, 84 .rate = 48000000,
83}; 85};
84 86
85/* A fixed divide-by-2 block */
86static unsigned long div2_recalc(struct clk *clk)
87{
88 return clk->parent->rate / 2;
89}
90
91static struct sh_clk_ops div2_clk_ops = {
92 .recalc = div2_recalc,
93};
94
95static unsigned long div7_recalc(struct clk *clk)
96{
97 return clk->parent->rate / 7;
98}
99
100static struct sh_clk_ops div7_clk_ops = {
101 .recalc = div7_recalc,
102};
103
104static unsigned long div13_recalc(struct clk *clk)
105{
106 return clk->parent->rate / 13;
107}
108
109static struct sh_clk_ops div13_clk_ops = {
110 .recalc = div13_recalc,
111};
112
113/* Divide extal1 by two */
114static struct clk extal1_div2_clk = {
115 .ops = &div2_clk_ops,
116 .parent = &sh73a0_extal1_clk,
117};
118
119/* Divide extal2 by two */
120static struct clk extal2_div2_clk = {
121 .ops = &div2_clk_ops,
122 .parent = &sh73a0_extal2_clk,
123};
124
125static struct sh_clk_ops main_clk_ops = { 87static struct sh_clk_ops main_clk_ops = {
126 .recalc = followparent_recalc, 88 .recalc = followparent_recalc,
127}; 89};
128 90
129/* Main clock */ 91/* Main clock */
130static struct clk main_clk = { 92static struct clk main_clk = {
93 /* .parent wll be set on sh73a0_clock_init() */
131 .ops = &main_clk_ops, 94 .ops = &main_clk_ops,
132}; 95};
133 96
134/* Divide Main clock by two */
135static struct clk main_div2_clk = {
136 .ops = &div2_clk_ops,
137 .parent = &main_clk,
138};
139
140/* PLL0, PLL1, PLL2, PLL3 */ 97/* PLL0, PLL1, PLL2, PLL3 */
141static unsigned long pll_recalc(struct clk *clk) 98static unsigned long pll_recalc(struct clk *clk)
142{ 99{
@@ -192,21 +149,17 @@ static struct clk pll3_clk = {
192 .enable_bit = 3, 149 .enable_bit = 3,
193}; 150};
194 151
195/* Divide PLL */ 152/* A fixed divide block */
196static struct clk pll1_div2_clk = { 153SH_CLK_RATIO(div2, 1, 2);
197 .ops = &div2_clk_ops, 154SH_CLK_RATIO(div7, 1, 7);
198 .parent = &pll1_clk, 155SH_CLK_RATIO(div13, 1, 13);
199};
200
201static struct clk pll1_div7_clk = {
202 .ops = &div7_clk_ops,
203 .parent = &pll1_clk,
204};
205 156
206static struct clk pll1_div13_clk = { 157SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
207 .ops = &div13_clk_ops, 158SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
208 .parent = &pll1_clk, 159SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
209}; 160SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
161SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
162SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
210 163
211/* External input clock */ 164/* External input clock */
212struct clk sh73a0_extcki_clk = { 165struct clk sh73a0_extcki_clk = {
@@ -234,14 +187,24 @@ static struct clk *main_clks[] = {
234 &sh73a0_extalr_clk, 187 &sh73a0_extalr_clk,
235}; 188};
236 189
237static void div4_kick(struct clk *clk) 190static int frqcr_kick(void)
238{ 191{
239 unsigned long value; 192 int i;
193
194 /* set KICK bit in FRQCRB to update hardware setting, check success */
195 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
196 for (i = 1000; i; i--)
197 if (__raw_readl(FRQCRB) & (1 << 31))
198 cpu_relax();
199 else
200 return i;
240 201
241 /* set KICK bit in FRQCRB to update hardware setting */ 202 return -ETIMEDOUT;
242 value = __raw_readl(FRQCRB); 203}
243 value |= (1 << 31); 204
244 __raw_writel(value, FRQCRB); 205static void div4_kick(struct clk *clk)
206{
207 frqcr_kick();
245} 208}
246 209
247static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 210static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
@@ -258,25 +221,37 @@ static struct clk_div4_table div4_table = {
258}; 221};
259 222
260enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, 223enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
261 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; 224 DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR };
262 225
263#define DIV4(_reg, _bit, _mask, _flags) \ 226#define DIV4(_reg, _bit, _mask, _flags) \
264 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) 227 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
265 228
266static struct clk div4_clks[DIV4_NR] = { 229static struct clk div4_clks[DIV4_NR] = {
267 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), 230 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
268 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), 231 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
269 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), 232 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
270 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), 233 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
271 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), 234 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
272 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), 235 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
273 [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0), 236 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
274 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
275 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
276 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), 237 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
277 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), 238 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
278}; 239};
279 240
241static unsigned long twd_recalc(struct clk *clk)
242{
243 return clk_get_rate(clk->parent) / 4;
244}
245
246static struct sh_clk_ops twd_clk_ops = {
247 .recalc = twd_recalc,
248};
249
250static struct clk twd_clk = {
251 .parent = &div4_clks[DIV4_Z],
252 .ops = &twd_clk_ops,
253};
254
280enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, 255enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
281 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, 256 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
282 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, 257 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -471,6 +446,7 @@ static struct clk dsi1phy_clk = {
471static struct clk *late_main_clks[] = { 446static struct clk *late_main_clks[] = {
472 &dsi0phy_clk, 447 &dsi0phy_clk,
473 &dsi1phy_clk, 448 &dsi1phy_clk,
449 &twd_clk,
474}; 450};
475 451
476enum { MSTP001, 452enum { MSTP001,
@@ -535,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
535static struct clk_lookup lookups[] = { 511static struct clk_lookup lookups[] = {
536 /* main clocks */ 512 /* main clocks */
537 CLKDEV_CON_ID("r_clk", &r_clk), 513 CLKDEV_CON_ID("r_clk", &r_clk),
514 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
538 515
539 /* DIV6 clocks */ 516 /* DIV6 clocks */
540 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 517 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
@@ -581,10 +558,13 @@ static struct clk_lookup lookups[] = {
581 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ 558 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
582 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ 559 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
583 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ 560 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
561 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
584 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ 562 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
563 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
585 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ 564 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
586 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ 565 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
587 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ 566 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
567 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
588 CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ 568 CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
589 CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ 569 CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
590 CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ 570 CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index e816ca9bd213..ad7df629d995 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -23,6 +23,19 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
25#include <linux/export.h> 25#include <linux/export.h>
26#include <mach/clock.h>
27#include <mach/common.h>
28
29unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
30{
31 struct clk_ratio *p = clk->priv;
32
33 return clk->parent->rate / p->div * p->mul;
34};
35
36struct sh_clk_ops shmobile_fixed_ratio_clk_ops = {
37 .recalc = shmobile_fixed_ratio_clk_recalc,
38};
26 39
27int __init shmobile_clk_init(void) 40int __init shmobile_clk_init(void)
28{ 41{
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bec4c0d9b713..7d113f898e7f 100644
--- a/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * SMP support for SoC sh73a0 2 * Shared SCU setup for mach-shmobile
3 * 3 *
4 * Copyright (C) 2012 Bastian Hecht 4 * Copyright (C) 2012 Bastian Hecht
5 * 5 *
@@ -35,11 +35,12 @@
35 * the physical address as the MMU is still turned off. 35 * the physical address as the MMU is still turned off.
36 */ 36 */
37 .align 12 37 .align 12
38ENTRY(sh73a0_secondary_vector) 38ENTRY(shmobile_secondary_vector_scu)
39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR 39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
40 and r0, r0, #3 @ mask out cpu ID 40 and r0, r0, #3 @ mask out cpu ID
41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits 41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
42 mov r1, #0xf0000000 @ SCU base address 42 ldr r1, 2f
43 ldr r1, [r1] @ SCU base address
43 ldr r2, [r1, #8] @ SCU Power Status Register 44 ldr r2, [r1, #8] @ SCU Power Status Register
44 mov r3, #3 45 mov r3, #3
45 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) 46 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
@@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
47 48
48 ldr pc, 1f 49 ldr pc, 1f
491: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET 501: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
50ENDPROC(sh73a0_secondary_vector) 512: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
52ENDPROC(shmobile_secondary_vector_scu)
53
54 .text
55 .globl shmobile_scu_base
56shmobile_scu_base:
57 .space 4
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
deleted file mode 100644
index a1524e3367b0..000000000000
--- a/arch/arm/mach-shmobile/hotplug.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * SMP support for R-Mobile / SH-Mobile
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/smp.h>
15#include <linux/cpumask.h>
16#include <linux/delay.h>
17#include <linux/of.h>
18#include <mach/common.h>
19#include <mach/r8a7779.h>
20#include <mach/emev2.h>
21#include <asm/cacheflush.h>
22#include <asm/mach-types.h>
23
24static cpumask_t dead_cpus;
25
26void shmobile_cpu_die(unsigned int cpu)
27{
28 /* hardware shutdown code running on the CPU that is being offlined */
29 flush_cache_all();
30 dsb();
31
32 /* notify platform_cpu_kill() that hardware shutdown is finished */
33 cpumask_set_cpu(cpu, &dead_cpus);
34
35 /* wait for SoC code in platform_cpu_kill() to shut off CPU core
36 * power. CPU bring up starts from the reset vector.
37 */
38 while (1) {
39 /*
40 * here's the WFI
41 */
42 asm(".word 0xe320f003\n"
43 :
44 :
45 : "memory", "cc");
46 }
47}
48
49int shmobile_cpu_disable(unsigned int cpu)
50{
51 cpumask_clear_cpu(cpu, &dead_cpus);
52 /*
53 * we don't allow CPU 0 to be shutdown (it is still too special
54 * e.g. clock tick interrupts)
55 */
56 return cpu == 0 ? -EPERM : 0;
57}
58
59int shmobile_cpu_disable_any(unsigned int cpu)
60{
61 cpumask_clear_cpu(cpu, &dead_cpus);
62 return 0;
63}
64
65int shmobile_cpu_is_dead(unsigned int cpu)
66{
67 return cpumask_test_cpu(cpu, &dead_cpus);
68}
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
new file mode 100644
index 000000000000..76ac61292e48
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -0,0 +1,39 @@
1#ifndef CLOCK_H
2#define CLOCK_H
3
4unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
5extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
6
7/* clock ratio */
8struct clk_ratio {
9 int mul;
10 int div;
11};
12
13#define SH_CLK_RATIO(name, m, d) \
14static struct clk_ratio name ##_ratio = { \
15 .mul = m, \
16 .div = d, \
17}
18
19#define SH_FIXED_RATIO_CLKg(name, p, r) \
20struct clk name = { \
21 .parent = &p, \
22 .ops = &shmobile_fixed_ratio_clk_ops,\
23 .priv = &r ## _ratio, \
24}
25
26#define SH_FIXED_RATIO_CLK(name, p, r) \
27static SH_FIXED_RATIO_CLKg(name, p, r);
28
29#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
30 SH_CLK_RATIO(name, m, d); \
31 SH_FIXED_RATIO_CLK(name, p, name);
32
33#define SH_CLK_SET_RATIO(p, m, d) \
34{ \
35 (p)->mul = m; \
36 (p)->div = d; \
37}
38
39#endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e48606d8a2be..e002cfd9d2df 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
8struct twd_local_timer; 8struct twd_local_timer;
9extern void shmobile_setup_console(void); 9extern void shmobile_setup_console(void);
10extern void shmobile_secondary_vector(void); 10extern void shmobile_secondary_vector(void);
11extern void shmobile_secondary_vector_scu(void);
11struct clk; 12struct clk;
12extern int shmobile_clk_init(void); 13extern int shmobile_clk_init(void);
13extern void shmobile_handle_irq_intc(struct pt_regs *); 14extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -18,58 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
18 struct cpuidle_driver *drv, int index); 19 struct cpuidle_driver *drv, int index);
19extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 20extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
20 21
21extern void sh7372_init_irq(void);
22extern void sh7372_map_io(void);
23extern void sh7372_earlytimer_init(void);
24extern void sh7372_add_early_devices(void);
25extern void sh7372_add_standard_devices(void);
26extern void sh7372_add_early_devices_dt(void);
27extern void sh7372_add_standard_devices_dt(void);
28extern void sh7372_clock_init(void);
29extern void sh7372_pinmux_init(void);
30extern void sh7372_pm_init(void);
31extern void sh7372_resume_core_standby_sysc(void);
32extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
33extern struct clk sh7372_extal1_clk;
34extern struct clk sh7372_extal2_clk;
35
36extern void sh73a0_init_irq(void);
37extern void sh73a0_init_irq_dt(void);
38extern void sh73a0_map_io(void);
39extern void sh73a0_earlytimer_init(void);
40extern void sh73a0_add_early_devices(void);
41extern void sh73a0_add_early_devices_dt(void);
42extern void sh73a0_add_standard_devices(void);
43extern void sh73a0_add_standard_devices_dt(void);
44extern void sh73a0_clock_init(void);
45extern void sh73a0_pinmux_init(void);
46extern void sh73a0_pm_init(void);
47extern void sh73a0_secondary_vector(void);
48extern struct clk sh73a0_extal1_clk;
49extern struct clk sh73a0_extal2_clk;
50extern struct clk sh73a0_extcki_clk;
51extern struct clk sh73a0_extalr_clk;
52
53extern void r8a7740_init_irq(void);
54extern void r8a7740_map_io(void);
55extern void r8a7740_add_early_devices(void);
56extern void r8a7740_add_standard_devices(void);
57extern void r8a7740_clock_init(u8 md_ck);
58extern void r8a7740_pinmux_init(void);
59extern void r8a7740_pm_init(void);
60
61extern void r8a7779_init_irq(void);
62extern void r8a7779_map_io(void);
63extern void r8a7779_earlytimer_init(void);
64extern void r8a7779_add_early_devices(void);
65extern void r8a7779_add_standard_devices(void);
66extern void r8a7779_clock_init(void);
67extern void r8a7779_pinmux_init(void);
68extern void r8a7779_pm_init(void);
69extern void r8a7740_meram_workaround(void);
70
71extern void r8a7779_register_twd(void);
72
73#ifdef CONFIG_SUSPEND 22#ifdef CONFIG_SUSPEND
74int shmobile_suspend_init(void); 23int shmobile_suspend_init(void);
75#else 24#else
@@ -82,16 +31,7 @@ int shmobile_cpuidle_init(void);
82static inline int shmobile_cpuidle_init(void) { return 0; } 31static inline int shmobile_cpuidle_init(void) { return 0; }
83#endif 32#endif
84 33
85extern void shmobile_cpu_die(unsigned int cpu); 34extern void __iomem *shmobile_scu_base;
86extern int shmobile_cpu_disable(unsigned int cpu);
87extern int shmobile_cpu_disable_any(unsigned int cpu);
88
89#ifdef CONFIG_HOTPLUG_CPU
90extern int shmobile_cpu_is_dead(unsigned int cpu);
91#else
92static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
93#endif
94
95extern void shmobile_smp_init_cpus(unsigned int ncores); 35extern void shmobile_smp_init_cpus(unsigned int ncores);
96 36
97static inline void __init shmobile_init_late(void) 37static inline void __init shmobile_init_late(void)
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 06a5da3c3050..b2074e2acb15 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -5,10 +5,15 @@
5 5
6/* GIC */ 6/* GIC */
7#define gic_spi(nr) ((nr) + 32) 7#define gic_spi(nr) ((nr) + 32)
8#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
8 9
9/* INTCS */ 10/* INTCS */
10#define INTCS_VECT_BASE 0x3400 11#define INTCS_VECT_BASE 0x3400
11#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) 12#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
12#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) 13#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
13 14
15/* External IRQ pins */
16#define IRQPIN_BASE 2000
17#define irq_pin(nr) ((nr) + IRQPIN_BASE)
18
14#endif /* __ASM_MACH_IRQS_H */ 19#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
new file mode 100644
index 000000000000..f043103e32c9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A73A4_H__
2#define __ASM_R8A73A4_H__
3
4void r8a73a4_add_standard_devices(void);
5void r8a73a4_clock_init(void);
6void r8a73a4_pinmux_init(void);
7
8#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index c2583610ad36..abdc4d4efa28 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -532,6 +532,15 @@ enum {
532 SHDMA_SLAVE_USBHS_RX, 532 SHDMA_SLAVE_USBHS_RX,
533}; 533};
534 534
535extern void r8a7740_meram_workaround(void);
536extern void r8a7740_init_irq(void);
537extern void r8a7740_map_io(void);
538extern void r8a7740_add_early_devices(void);
539extern void r8a7740_add_standard_devices(void);
540extern void r8a7740_clock_init(u8 md_ck);
541extern void r8a7740_pinmux_init(void);
542extern void r8a7740_pm_init(void);
543
535#ifdef CONFIG_PM 544#ifdef CONFIG_PM
536extern void __init r8a7740_init_pm_domains(void); 545extern void __init r8a7740_init_pm_domains(void);
537#else 546#else
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
new file mode 100644
index 000000000000..a755dcafef4d
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ASM_R8A7778_H__
19#define __ASM_R8A7778_H__
20
21extern void r8a7778_add_standard_devices(void);
22extern void r8a7778_add_standard_devices_dt(void);
23extern void r8a7778_init_delay(void);
24extern void r8a7778_init_irq(void);
25extern void r8a7778_init_irq_dt(void);
26extern void r8a7778_clock_init(void);
27
28#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ea0ad18cdff..68c3b2dfb018 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -339,6 +339,19 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
339 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; 339 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
340} 340}
341 341
342extern void r8a7779_init_delay(void);
343extern void r8a7779_init_irq(void);
344extern void r8a7779_init_irq_extpin(int irlm);
345extern void r8a7779_init_irq_dt(void);
346extern void r8a7779_map_io(void);
347extern void r8a7779_earlytimer_init(void);
348extern void r8a7779_add_early_devices(void);
349extern void r8a7779_add_standard_devices(void);
350extern void r8a7779_add_standard_devices_dt(void);
351extern void r8a7779_clock_init(void);
352extern void r8a7779_pinmux_init(void);
353extern void r8a7779_pm_init(void);
354extern void r8a7779_register_twd(void);
342extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); 355extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
343extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); 356extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
344 357
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
new file mode 100644
index 000000000000..9bd6f5c894bb
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__
3
4void r8a7790_add_standard_devices(void);
5void r8a7790_clock_init(void);
6void r8a7790_pinmux_init(void);
7
8#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 7ded4ebaf5cc..fd7cba024c39 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -449,6 +449,18 @@ extern struct clk sh7372_dv_clki_clk;
449extern struct clk sh7372_dv_clki_div2_clk; 449extern struct clk sh7372_dv_clki_div2_clk;
450extern struct clk sh7372_pllc2_clk; 450extern struct clk sh7372_pllc2_clk;
451 451
452extern void sh7372_init_irq(void);
453extern void sh7372_map_io(void);
454extern void sh7372_earlytimer_init(void);
455extern void sh7372_add_early_devices(void);
456extern void sh7372_add_standard_devices(void);
457extern void sh7372_add_early_devices_dt(void);
458extern void sh7372_add_standard_devices_dt(void);
459extern void sh7372_clock_init(void);
460extern void sh7372_pinmux_init(void);
461extern void sh7372_pm_init(void);
462extern void sh7372_resume_core_standby_sysc(void);
463extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
452extern void sh7372_intcs_suspend(void); 464extern void sh7372_intcs_suspend(void);
453extern void sh7372_intcs_resume(void); 465extern void sh7372_intcs_resume(void);
454extern void sh7372_intca_suspend(void); 466extern void sh7372_intca_suspend(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index fbc1584d6712..eb7a4320d487 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -444,6 +444,21 @@ enum {
444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) 444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) 445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
446 446
447extern void sh73a0_init_delay(void);
448extern void sh73a0_init_irq(void);
449extern void sh73a0_init_irq_dt(void);
450extern void sh73a0_map_io(void);
451extern void sh73a0_earlytimer_init(void);
452extern void sh73a0_add_early_devices(void);
453extern void sh73a0_add_standard_devices(void);
454extern void sh73a0_add_standard_devices_dt(void);
455extern void sh73a0_clock_init(void);
456extern void sh73a0_pinmux_init(void);
457extern void sh73a0_pm_init(void);
458extern struct clk sh73a0_extal1_clk;
459extern struct clk sh73a0_extal2_clk;
460extern struct clk sh73a0_extcki_clk;
461extern struct clk sh73a0_extalr_clk;
447extern struct smp_operations sh73a0_smp_ops; 462extern struct smp_operations sh73a0_smp_ops;
448 463
449#endif /* __ASM_SH73A0_H__ */ 464#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index 9a69a31918ba..b741c8409a5a 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -18,620 +18,39 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/kernel.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h> 22#include <linux/io.h>
26#include <linux/sh_intc.h> 23#include <linux/irqchip/arm-gic.h>
27#include <mach/intc.h>
28#include <mach/irqs.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/*
33 * INTCA
34 */
35enum {
36 UNUSED_INTCA = 0,
37
38 /* interrupt sources INTCA */
39 DIRC,
40 ATAPI,
41 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
42 AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI, MFIS,
44 BBIF1, BBIF2,
45 USBHSDMAC,
46 USBF_OUL_SOF, USBF_IXL_INT,
47 SGX540,
48 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
49 CMT2,
50 CMT3,
51 KEYSC,
52 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
53 MSIOF2, MSIOF1,
54 SCIFA4, SCIFA5, SCIFB,
55 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
56 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
57 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
58 AP_ARM_L2CINT,
59 IRDA,
60 TPU0,
61 SCIFA6, SCIFA7,
62 GbEther,
63 ICBS0,
64 DDM,
65 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
66 RWDT0,
67 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
68 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 HDMI,
75 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
76 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
77 SPU2_0, SPU2_1,
78 FSI, FMSI,
79 HDMI_SSS, HDMI_KEY,
80 IPMMU,
81 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 MMCIF_0, MMCIF_1, MMCIF_2,
86 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
87 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
88
89 /* interrupt groups INTCA */
90 DMAC1_1, DMAC1_2,
91 DMAC2_1, DMAC2_2,
92 DMAC3_1, DMAC3_2,
93 AP_ARM1, AP_ARM2,
94 SDHI0, SDHI1, SDHI2,
95 SHWYSTAT,
96 USBF, USBH1, USBH2,
97 RSPI, SPU2, FLCTL, IIC1,
98};
99
100static struct intc_vect intca_vectors[] __initdata = {
101 INTC_VECT(DIRC, 0x0560),
102 INTC_VECT(ATAPI, 0x05E0),
103 INTC_VECT(IIC1_ALI, 0x0780),
104 INTC_VECT(IIC1_TACKI, 0x07A0),
105 INTC_VECT(IIC1_WAITI, 0x07C0),
106 INTC_VECT(IIC1_DTEI, 0x07E0),
107 INTC_VECT(AP_ARM_COMMTX, 0x0840),
108 INTC_VECT(AP_ARM_COMMRX, 0x0860),
109 INTC_VECT(MFI, 0x0900),
110 INTC_VECT(MFIS, 0x0920),
111 INTC_VECT(BBIF1, 0x0940),
112 INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC, 0x0A00),
114 INTC_VECT(USBF_OUL_SOF, 0x0A20),
115 INTC_VECT(USBF_IXL_INT, 0x0A40),
116 INTC_VECT(SGX540, 0x0A60),
117 INTC_VECT(CMT1_0, 0x0B00),
118 INTC_VECT(CMT1_1, 0x0B20),
119 INTC_VECT(CMT1_2, 0x0B40),
120 INTC_VECT(CMT1_3, 0x0B60),
121 INTC_VECT(CMT2, 0x0B80),
122 INTC_VECT(CMT3, 0x0BA0),
123 INTC_VECT(KEYSC, 0x0BE0),
124 INTC_VECT(SCIFA0, 0x0C00),
125 INTC_VECT(SCIFA1, 0x0C20),
126 INTC_VECT(SCIFA2, 0x0C40),
127 INTC_VECT(SCIFA3, 0x0C60),
128 INTC_VECT(MSIOF2, 0x0C80),
129 INTC_VECT(MSIOF1, 0x0D00),
130 INTC_VECT(SCIFA4, 0x0D20),
131 INTC_VECT(SCIFA5, 0x0D40),
132 INTC_VECT(SCIFB, 0x0D60),
133 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
134 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
135 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
136 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
137 INTC_VECT(SDHI0_0, 0x0E00),
138 INTC_VECT(SDHI0_1, 0x0E20),
139 INTC_VECT(SDHI0_2, 0x0E40),
140 INTC_VECT(SDHI0_3, 0x0E60),
141 INTC_VECT(SDHI1_0, 0x0E80),
142 INTC_VECT(SDHI1_1, 0x0EA0),
143 INTC_VECT(SDHI1_2, 0x0EC0),
144 INTC_VECT(SDHI1_3, 0x0EE0),
145 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
146 INTC_VECT(IRDA, 0x0480),
147 INTC_VECT(TPU0, 0x04A0),
148 INTC_VECT(SCIFA6, 0x04C0),
149 INTC_VECT(SCIFA7, 0x04E0),
150 INTC_VECT(GbEther, 0x0500),
151 INTC_VECT(ICBS0, 0x0540),
152 INTC_VECT(DDM, 0x1140),
153 INTC_VECT(SDHI2_0, 0x1200),
154 INTC_VECT(SDHI2_1, 0x1220),
155 INTC_VECT(SDHI2_2, 0x1240),
156 INTC_VECT(SDHI2_3, 0x1260),
157 INTC_VECT(RWDT0, 0x1280),
158 INTC_VECT(DMAC1_1_DEI0, 0x2000),
159 INTC_VECT(DMAC1_1_DEI1, 0x2020),
160 INTC_VECT(DMAC1_1_DEI2, 0x2040),
161 INTC_VECT(DMAC1_1_DEI3, 0x2060),
162 INTC_VECT(DMAC1_2_DEI4, 0x2080),
163 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
164 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
165 INTC_VECT(DMAC2_1_DEI0, 0x2100),
166 INTC_VECT(DMAC2_1_DEI1, 0x2120),
167 INTC_VECT(DMAC2_1_DEI2, 0x2140),
168 INTC_VECT(DMAC2_1_DEI3, 0x2160),
169 INTC_VECT(DMAC2_2_DEI4, 0x2180),
170 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
171 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
172 INTC_VECT(DMAC3_1_DEI0, 0x2200),
173 INTC_VECT(DMAC3_1_DEI1, 0x2220),
174 INTC_VECT(DMAC3_1_DEI2, 0x2240),
175 INTC_VECT(DMAC3_1_DEI3, 0x2260),
176 INTC_VECT(DMAC3_2_DEI4, 0x2280),
177 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
178 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
179 INTC_VECT(SHWYSTAT_RT, 0x1300),
180 INTC_VECT(SHWYSTAT_HS, 0x1320),
181 INTC_VECT(SHWYSTAT_COM, 0x1340),
182 INTC_VECT(USBH_INT, 0x1540),
183 INTC_VECT(USBH_OHCI, 0x1560),
184 INTC_VECT(USBH_EHCI, 0x1580),
185 INTC_VECT(USBH_PME, 0x15A0),
186 INTC_VECT(USBH_BIND, 0x15C0),
187 INTC_VECT(HDMI, 0x1700),
188 INTC_VECT(RSPI_OVRF, 0x1780),
189 INTC_VECT(RSPI_SPTEF, 0x17A0),
190 INTC_VECT(RSPI_SPRF, 0x17C0),
191 INTC_VECT(SPU2_0, 0x1800),
192 INTC_VECT(SPU2_1, 0x1820),
193 INTC_VECT(FSI, 0x1840),
194 INTC_VECT(FMSI, 0x1860),
195 INTC_VECT(HDMI_SSS, 0x18A0),
196 INTC_VECT(HDMI_KEY, 0x18C0),
197 INTC_VECT(IPMMU, 0x1920),
198 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
199 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
200 INTC_VECT(MFIS2, 0x1A00),
201 INTC_VECT(CPORTR2S, 0x1A20),
202 INTC_VECT(CMT14, 0x1A40),
203 INTC_VECT(CMT15, 0x1A60),
204 INTC_VECT(MMCIF_0, 0x1AA0),
205 INTC_VECT(MMCIF_1, 0x1AC0),
206 INTC_VECT(MMCIF_2, 0x1AE0),
207 INTC_VECT(SIM_ERI, 0x1C00),
208 INTC_VECT(SIM_RXI, 0x1C20),
209 INTC_VECT(SIM_TXI, 0x1C40),
210 INTC_VECT(SIM_TEI, 0x1C60),
211 INTC_VECT(STPRO_0, 0x1C80),
212 INTC_VECT(STPRO_1, 0x1CA0),
213 INTC_VECT(STPRO_2, 0x1CC0),
214 INTC_VECT(STPRO_3, 0x1CE0),
215 INTC_VECT(STPRO_4, 0x1D00),
216};
217
218static struct intc_group intca_groups[] __initdata = {
219 INTC_GROUP(DMAC1_1,
220 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
221 INTC_GROUP(DMAC1_2,
222 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
223 INTC_GROUP(DMAC2_1,
224 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
225 INTC_GROUP(DMAC2_2,
226 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
227 INTC_GROUP(DMAC3_1,
228 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
229 INTC_GROUP(DMAC3_2,
230 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
231 INTC_GROUP(AP_ARM1,
232 AP_ARM_COMMTX, AP_ARM_COMMRX),
233 INTC_GROUP(AP_ARM2,
234 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
235 INTC_GROUP(USBF,
236 USBF_OUL_SOF, USBF_IXL_INT),
237 INTC_GROUP(SDHI0,
238 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
239 INTC_GROUP(SDHI1,
240 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
241 INTC_GROUP(SDHI2,
242 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
243 INTC_GROUP(SHWYSTAT,
244 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
245 INTC_GROUP(USBH1, /* FIXME */
246 USBH_INT, USBH_OHCI),
247 INTC_GROUP(USBH2, /* FIXME */
248 USBH_EHCI,
249 USBH_PME, USBH_BIND),
250 INTC_GROUP(RSPI,
251 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
252 INTC_GROUP(SPU2,
253 SPU2_0, SPU2_1),
254 INTC_GROUP(FLCTL,
255 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
256 INTC_GROUP(IIC1,
257 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
258};
259
260static struct intc_mask_reg intca_mask_registers[] __initdata = {
261 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
262 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
263 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
264 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
265 { ATAPI, 0, DIRC, 0,
266 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
267 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
268 { 0, 0, 0, 0,
269 BBIF1, BBIF2, MFIS, MFI } },
270 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
271 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
272 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
273 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
274 { DDM, 0, 0, 0,
275 0, 0, 0, 0 } },
276 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
277 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
278 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
279 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
280 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
281 0, 0, MSIOF2, 0 } },
282 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
283 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
284 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
285 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
286 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
287 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
288 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
289 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
290 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
291 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
292 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
293 0, 0, 0, 0 } },
294 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
295 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
296 ICBS0, 0, 0, 0 } },
297 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
298 { 0, 0, TPU0, SCIFA6,
299 SCIFA7, GbEther, 0, 0 } },
300 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
301 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
302 0, CMT3, 0, RWDT0 } },
303 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
304 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
305 0, 0, 0, 0 } },
306 /* IMR1A3 / IMCR1A3 */
307 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
308 { 0, 0, USBH_INT, USBH_OHCI,
309 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
310 /* IMR3A3 / IMCR3A3 */
311 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
312 { HDMI, 0, 0, 0,
313 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
314 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
315 { SPU2_0, SPU2_1, FSI, FMSI,
316 0, HDMI_SSS, HDMI_KEY, 0 } },
317 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
318 { 0, IPMMU, 0, 0,
319 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
320 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
321 { MFIS2, CPORTR2S, CMT14, CMT15,
322 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
323 /* IMR8A3 / IMCR8A3 */
324 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
325 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
326 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
327 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
328 { STPRO_4, 0, 0, 0,
329 0, 0, 0, 0 } },
330};
331
332static struct intc_prio_reg intca_prio_registers[] __initdata = {
333 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
334 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
335 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
336 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
337 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
338 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
339 SGX540, CMT1_0 } },
340 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
341 SCIFA2, SCIFA3 } },
342 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
343 FLCTL, SDHI0 } },
344 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
345 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
346 AP_ARM_L2CINT, 0 } },
347 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
348 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
349 SCIFA7, GbEther } },
350 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
351 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
352 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
353 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
354 /* IPRBA3 */
355 /* IPRCA3 */
356 /* IPRDA3 */
357 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
358 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
359 /* IPRGA3 */
360 /* IPRHA3 */
361 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
362 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
363 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
364 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
365 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
366 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
367 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
368 CMT14, CMT15 } },
369 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
370 /* IPRQA3 */
371 /* IPRRA3 */
372 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
373 SIM_TXI, SIM_TEI } },
374 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
375 STPRO_2, STPRO_3 } },
376 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
377};
378
379static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
380 intca_vectors, intca_groups,
381 intca_mask_registers, intca_prio_registers,
382 NULL);
383
384INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
385 INTC_VECT, "r8a7740-intca-irq-pins");
386
387
388/*
389 * INTCS
390 */
391enum {
392 UNUSED_INTCS = 0,
393
394 INTCS,
395
396 /* interrupt sources INTCS */
397
398 /* HUDI */
399 /* STPRO */
400 /* RTDMAC(1) */
401 VPU5HA2,
402 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
403 /* MFI */
404 /* BBIF2 */
405 VPU5F,
406 _2DG_BRK_INT,
407 /* SGX540 */
408 /* 2DDMAC */
409 /* IPMMU */
410 /* RTDMAC 2 */
411 /* KEYSC */
412 /* MSIOF */
413 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
414 TMU0_0, TMU0_1, TMU0_2,
415 CMT0,
416 /* CMT2 */
417 LMB,
418 CTI,
419 VOU,
420 /* RWDT0 */
421 ICB,
422 VIO6C,
423 CEU20, CEU21,
424 JPU,
425 LCDC0,
426 LCRC,
427 /* RTDMAC2(1) */
428 /* RTDMAC2(2) */
429 LCDC1,
430 /* SPU2 */
431 /* FSI */
432 /* FMSI */
433 TMU1_0, TMU1_1, TMU1_2,
434 CMT4,
435 DISP,
436 DSRV,
437 /* MFIS2 */
438 CPORTS2R,
439
440 /* interrupt groups INTCS */
441 _2DG1,
442 IIC0, TMU1,
443};
444
445static struct intc_vect intcs_vectors[] = {
446 /* HUDI */
447 /* STPRO */
448 /* RTDMAC(1) */
449 INTCS_VECT(VPU5HA2, 0x0880),
450 INTCS_VECT(_2DG_TRAP, 0x08A0),
451 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
452 INTCS_VECT(_2DG_CER_INT, 0x08E0),
453 /* MFI */
454 /* BBIF2 */
455 INTCS_VECT(VPU5F, 0x0980),
456 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
457 /* SGX540 */
458 /* 2DDMAC */
459 /* IPMMU */
460 /* RTDMAC(2) */
461 /* KEYSC */
462 /* MSIOF */
463 INTCS_VECT(IIC0_ALI, 0x0E00),
464 INTCS_VECT(IIC0_TACKI, 0x0E20),
465 INTCS_VECT(IIC0_WAITI, 0x0E40),
466 INTCS_VECT(IIC0_DTEI, 0x0E60),
467 INTCS_VECT(TMU0_0, 0x0E80),
468 INTCS_VECT(TMU0_1, 0x0EA0),
469 INTCS_VECT(TMU0_2, 0x0EC0),
470 INTCS_VECT(CMT0, 0x0F00),
471 /* CMT2 */
472 INTCS_VECT(LMB, 0x0F60),
473 INTCS_VECT(CTI, 0x0400),
474 INTCS_VECT(VOU, 0x0420),
475 /* RWDT0 */
476 INTCS_VECT(ICB, 0x0480),
477 INTCS_VECT(VIO6C, 0x04E0),
478 INTCS_VECT(CEU20, 0x0500),
479 INTCS_VECT(CEU21, 0x0520),
480 INTCS_VECT(JPU, 0x0560),
481 INTCS_VECT(LCDC0, 0x0580),
482 INTCS_VECT(LCRC, 0x05A0),
483 /* RTDMAC2(1) */
484 /* RTDMAC2(2) */
485 INTCS_VECT(LCDC1, 0x1780),
486 /* SPU2 */
487 /* FSI */
488 /* FMSI */
489 INTCS_VECT(TMU1_0, 0x1900),
490 INTCS_VECT(TMU1_1, 0x1920),
491 INTCS_VECT(TMU1_2, 0x1940),
492 INTCS_VECT(CMT4, 0x1980),
493 INTCS_VECT(DISP, 0x19A0),
494 INTCS_VECT(DSRV, 0x19C0),
495 /* MFIS2 */
496 INTCS_VECT(CPORTS2R, 0x1A20),
497
498 INTC_VECT(INTCS, 0xf80),
499};
500
501static struct intc_group intcs_groups[] __initdata = {
502 INTC_GROUP(_2DG1, /*FIXME*/
503 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
504 INTC_GROUP(IIC0,
505 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
506 INTC_GROUP(TMU1,
507 TMU1_0, TMU1_1, TMU1_2),
508};
509
510static struct intc_mask_reg intcs_mask_registers[] = {
511 /* IMR0SA / IMCR0SA */ /* all 0 */
512 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
513 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
514 0, 0, 0, 0 /*STPRO*/ } },
515 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
516 { 0/*STPRO*/, 0, CEU21, VPU5F,
517 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
518 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
519 { 0, 0, 0, 0, /*2DDMAC*/
520 VIO6C, 0, 0, ICB } },
521 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
522 { 0, 0, VOU, CTI,
523 JPU, 0, LCRC, LCDC0 } },
524 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
525 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
526 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
527 { 0, TMU0_2, TMU0_1, TMU0_0,
528 0, 0, 0, 0 } },
529 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
530 { 0, 0, 0, 0,
531 CEU20, 0, 0, 0 } },
532 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
533 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
534 0, 0, 0, 0 } },
535 /* IMR10SA / IMCR10SA */ /*IPMMU*/
536 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
537 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
538 0, _2DG_BRK_INT, LMB, 0 } },
539 /* IMR12SA / IMCR12SA */
540 /* IMR13SA / IMCR13SA */
541 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
542 /* IMR1SA3 / IMCR1SA3 */
543 /* IMR2SA3 / IMCR2SA3 */
544 /* IMR3SA3 / IMCR3SA3 */
545 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
546 { 0, 0, 0, 0,
547 LCDC1, 0, 0, 0 } },
548 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
549 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
550 { TMU1_0, TMU1_1, TMU1_2, 0,
551 CMT4, DISP, DSRV, 0 } },
552 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
553 { 0/*MFIS2*/, CPORTS2R, 0, 0,
554 0, 0, 0, 0 } },
555 { /* INTAMASK */ 0xffd20104, 0, 16,
556 { 0, 0, 0, 0, 0, 0, 0, 0,
557 0, 0, 0, 0, 0, 0, 0, INTCS } },
558};
559
560/* Priority is needed for INTCA to receive the INTCS interrupt */
561static struct intc_prio_reg intcs_prio_registers[] = {
562 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
563 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
564 /* IPRCS */ /*BBIF2*/
565 /* IPRDS */
566 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
567 0/*MFI*/, VPU5F } },
568 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
569 0/*CMT2*/, CMT0 } },
570 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
571 TMU0_2, _2DG1 } },
572 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
573 _2DG_BRK_INT/*FIXME*/ } },
574 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
575 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
576 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
577 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
578 /* IPRMS */ /*RWDT0*/
579 /* IPRAS3 */ /*RTDMAC2(1)*/
580 /* IPRBS3 */ /*RTDMAC2(2)*/
581 /* IPRCS3 */
582 /* IPRDS3 */
583 /* IPRES3 */
584 /* IPRFS3 */
585 /* IPRGS3 */
586 /* IPRHS3 */
587 /* IPRIS3 */
588 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
589 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
590 /* IPRLS3 */
591 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
592 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
593 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
594 /* IPRPS3 */
595};
596
597static struct resource intcs_resources[] __initdata = {
598 [0] = {
599 .start = 0xffd20000,
600 .end = 0xffd201ff,
601 .flags = IORESOURCE_MEM,
602 },
603 [1] = {
604 .start = 0xffd50000,
605 .end = 0xffd501ff,
606 .flags = IORESOURCE_MEM,
607 }
608};
609
610static struct intc_desc intcs_desc __initdata = {
611 .name = "r8a7740-intcs",
612 .resource = intcs_resources,
613 .num_resources = ARRAY_SIZE(intcs_resources),
614 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
615 intcs_prio_registers, NULL, NULL),
616};
617
618static void intcs_demux(unsigned int irq, struct irq_desc *desc)
619{
620 void __iomem *reg = (void *)irq_get_handler_data(irq);
621 unsigned int evtcodeas = ioread32(reg);
622
623 generic_handle_irq(intcs_evt2irq(evtcodeas));
624}
625 24
626void __init r8a7740_init_irq(void) 25void __init r8a7740_init_irq(void)
627{ 26{
628 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 27 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
629 28 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
630 register_intc_controller(&intca_desc); 29 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
631 register_intc_controller(&intca_irq_pins_desc); 30 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
632 register_intc_controller(&intcs_desc); 31 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
633 32
634 /* demux using INTEVTSA */ 33 /* initialize the Generic Interrupt Controller PL390 r0p0 */
635 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); 34 gic_init(0, 29, gic_dist_base, gic_cpu_base);
636 irq_set_chained_handler(evt2irq(0xf80), intcs_demux); 35
36 /* route signals to GIC */
37 iowrite32(0x0, pfc_inta_ctrl);
38
39 /*
40 * To mask the shared interrupt to SPI 149 we must ensure to set
41 * PRIO *and* MASK. Else we run into IRQ floods when registering
42 * the intc_irqpin devices
43 */
44 iowrite32(0x0, intc_prio_base + 0x0);
45 iowrite32(0x0, intc_prio_base + 0x4);
46 iowrite32(0x0, intc_prio_base + 0x8);
47 iowrite32(0x0, intc_prio_base + 0xc);
48 iowrite8(0xff, intc_msk_base + 0x0);
49 iowrite8(0xff, intc_msk_base + 0x4);
50 iowrite8(0xff, intc_msk_base + 0x8);
51 iowrite8(0xff, intc_msk_base + 0xc);
52
53 iounmap(intc_prio_base);
54 iounmap(intc_msk_base);
55 iounmap(pfc_inta_ctrl);
637} 56}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27f71f9..b86dc8908724 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -19,12 +19,16 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/platform_device.h>
22#include <linux/interrupt.h> 23#include <linux/interrupt.h>
23#include <linux/irq.h> 24#include <linux/irq.h>
24#include <linux/io.h> 25#include <linux/io.h>
25#include <linux/irqchip/arm-gic.h> 26#include <linux/irqchip/arm-gic.h>
27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
28#include <linux/irqchip.h>
26#include <mach/common.h> 29#include <mach/common.h>
27#include <mach/intc.h> 30#include <mach/intc.h>
31#include <mach/irqs.h>
28#include <mach/r8a7779.h> 32#include <mach/r8a7779.h>
29#include <asm/mach-types.h> 33#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
@@ -38,18 +42,61 @@
38#define INT2NTSR0 IOMEM(0xfe700060) 42#define INT2NTSR0 IOMEM(0xfe700060)
39#define INT2NTSR1 IOMEM(0xfe700064) 43#define INT2NTSR1 IOMEM(0xfe700064)
40 44
45static struct renesas_intc_irqpin_config irqpin0_platform_data = {
46 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
47 .sense_bitfield_width = 2,
48};
49
50static struct resource irqpin0_resources[] = {
51 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
52 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
53 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
54 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
55 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
56 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
57 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
58 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
59 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
60};
61
62static struct platform_device irqpin0_device = {
63 .name = "renesas_intc_irqpin",
64 .id = 0,
65 .resource = irqpin0_resources,
66 .num_resources = ARRAY_SIZE(irqpin0_resources),
67 .dev = {
68 .platform_data = &irqpin0_platform_data,
69 },
70};
71
72void __init r8a7779_init_irq_extpin(int irlm)
73{
74 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
75 unsigned long tmp;
76
77 if (icr0) {
78 tmp = ioread32(icr0);
79 if (irlm)
80 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
81 else
82 tmp &= ~(1 << 23); /* IRL mode - not supported */
83 tmp |= (1 << 21); /* LVLMODE = 1 */
84 iowrite32(tmp, icr0);
85 iounmap(icr0);
86
87 if (irlm)
88 platform_device_register(&irqpin0_device);
89 } else
90 pr_warn("r8a7779: unable to setup external irq pin mode\n");
91}
92
41static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 93static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
42{ 94{
43 return 0; /* always allow wakeup */ 95 return 0; /* always allow wakeup */
44} 96}
45 97
46void __init r8a7779_init_irq(void) 98static void __init r8a7779_init_irq_common(void)
47{ 99{
48 void __iomem *gic_dist_base = IOMEM(0xf0001000);
49 void __iomem *gic_cpu_base = IOMEM(0xf0000100);
50
51 /* use GIC to handle interrupts */
52 gic_init(0, 29, gic_dist_base, gic_cpu_base);
53 gic_arch_extn.irq_set_wake = r8a7779_set_wake; 100 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
54 101
55 /* route all interrupts to ARM */ 102 /* route all interrupts to ARM */
@@ -63,3 +110,22 @@ void __init r8a7779_init_irq(void)
63 __raw_writel(0xbffffffc, INT2SMSKCR3); 110 __raw_writel(0xbffffffc, INT2SMSKCR3);
64 __raw_writel(0x003fee3f, INT2SMSKCR4); 111 __raw_writel(0x003fee3f, INT2SMSKCR4);
65} 112}
113
114void __init r8a7779_init_irq(void)
115{
116 void __iomem *gic_dist_base = IOMEM(0xf0001000);
117 void __iomem *gic_cpu_base = IOMEM(0xf0000100);
118
119 /* use GIC to handle interrupts */
120 gic_init(0, 29, gic_dist_base, gic_cpu_base);
121
122 r8a7779_init_irq_common();
123}
124
125#ifdef CONFIG_OF
126void __init r8a7779_init_irq_dt(void)
127{
128 irqchip_init();
129 r8a7779_init_irq_common();
130}
131#endif
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 91faba666d46..19a26f4579b3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
260 return 0; /* always allow wakeup */ 260 return 0; /* always allow wakeup */
261} 261}
262 262
263#define RELOC_BASE 0x1200
264
265/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
266#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
267
268INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
269 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
270
271static int to_gic_irq(struct irq_data *data)
272{
273 unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
274
275 if (vect >= 0x3200)
276 vect -= 0x3000;
277 else
278 vect -= 0x0200;
279
280 return gic_spi((vect >> 5) + 1);
281}
282
283static int to_intca_reloc_irq(struct irq_data *data)
284{
285 return data->irq + (RELOC_BASE >> 5);
286}
287
288#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
289#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
290
291static void intca_gic_enable(struct irq_data *data)
292{
293 irq_cb(irq_unmask, to_intca_reloc_irq(data));
294 irq_cb(irq_unmask, to_gic_irq(data));
295}
296
297static void intca_gic_disable(struct irq_data *data)
298{
299 irq_cb(irq_mask, to_gic_irq(data));
300 irq_cb(irq_mask, to_intca_reloc_irq(data));
301}
302
303static void intca_gic_mask_ack(struct irq_data *data)
304{
305 irq_cb(irq_mask, to_gic_irq(data));
306 irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
307}
308
309static void intca_gic_eoi(struct irq_data *data)
310{
311 irq_cb(irq_eoi, to_gic_irq(data));
312}
313
314static int intca_gic_set_type(struct irq_data *data, unsigned int type)
315{
316 return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
317}
318
319#ifdef CONFIG_SMP
320static int intca_gic_set_affinity(struct irq_data *data,
321 const struct cpumask *cpumask,
322 bool force)
323{
324 return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
325}
326#endif
327
328struct irq_chip intca_gic_irq_chip = {
329 .name = "INTCA-GIC",
330 .irq_mask = intca_gic_disable,
331 .irq_unmask = intca_gic_enable,
332 .irq_mask_ack = intca_gic_mask_ack,
333 .irq_eoi = intca_gic_eoi,
334 .irq_enable = intca_gic_enable,
335 .irq_disable = intca_gic_disable,
336 .irq_shutdown = intca_gic_disable,
337 .irq_set_type = intca_gic_set_type,
338 .irq_set_wake = sh73a0_set_wake,
339#ifdef CONFIG_SMP
340 .irq_set_affinity = intca_gic_set_affinity,
341#endif
342};
343
344static int to_intc_vect(int irq)
345{
346 unsigned int irq_pin = irq - gic_spi(1);
347 unsigned int offs;
348
349 if (irq_pin < 16)
350 offs = 0x0200;
351 else
352 offs = 0x3000;
353
354 return offs + (irq_pin << 5);
355}
356
357static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
358{
359 generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
360 return IRQ_HANDLED;
361}
362
363static struct irqaction sh73a0_irq_pin_cascade[32];
364
365#define PINTER0_PHYS 0xe69000a0 263#define PINTER0_PHYS 0xe69000a0
366#define PINTER1_PHYS 0xe69000a4 264#define PINTER1_PHYS 0xe69000a4
367#define PINTER0_VIRT IOMEM(0xe69000a0) 265#define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
422 void __iomem *gic_dist_base = IOMEM(0xf0001000); 320 void __iomem *gic_dist_base = IOMEM(0xf0001000);
423 void __iomem *gic_cpu_base = IOMEM(0xf0000100); 321 void __iomem *gic_cpu_base = IOMEM(0xf0000100);
424 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 322 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
425 int k, n;
426 323
427 gic_init(0, 29, gic_dist_base, gic_cpu_base); 324 gic_init(0, 29, gic_dist_base, gic_cpu_base);
428 gic_arch_extn.irq_set_wake = sh73a0_set_wake; 325 gic_arch_extn.irq_set_wake = sh73a0_set_wake;
429 326
430 register_intc_controller(&intcs_desc); 327 register_intc_controller(&intcs_desc);
431 register_intc_controller(&intca_irq_pins_desc);
432 register_intc_controller(&intc_pint0_desc); 328 register_intc_controller(&intc_pint0_desc);
433 register_intc_controller(&intc_pint1_desc); 329 register_intc_controller(&intc_pint1_desc);
434 330
@@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
438 sh73a0_intcs_cascade.dev_id = intevtsa; 334 sh73a0_intcs_cascade.dev_id = intevtsa;
439 setup_irq(gic_spi(50), &sh73a0_intcs_cascade); 335 setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
440 336
441 /* IRQ pins require special handling through INTCA and GIC */
442 for (k = 0; k < 32; k++) {
443 sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
444 sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
445 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
446
447 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
448 WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
449 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
450 handle_level_irq, "level");
451 set_irq_flags(n, IRQF_VALID); /* yuck */
452 }
453
454 /* PINT pins are sanely tied to the GIC as SPI */ 337 /* PINT pins are sanely tied to the GIC as SPI */
455 sh73a0_pint0_cascade.name = "PINT0 cascade"; 338 sh73a0_pint0_cascade.name = "PINT0 cascade";
456 sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; 339 sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
@@ -460,11 +343,3 @@ void __init sh73a0_init_irq(void)
460 sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; 343 sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
461 setup_irq(gic_spi(34), &sh73a0_pint1_cascade); 344 setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
462} 345}
463
464#ifdef CONFIG_OF
465void __init sh73a0_init_irq_dt(void)
466{
467 irqchip_init();
468 gic_arch_extn.irq_set_wake = sh73a0_set_wake;
469}
470#endif
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 47662a581c0a..e4545c152722 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
404 ARRAY_SIZE(emev2_late_devices)); 404 ARRAY_SIZE(emev2_late_devices));
405} 405}
406 406
407void __init emev2_init_delay(void) 407static void __init emev2_init_delay(void)
408{ 408{
409 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ 409 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
410} 410}
@@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
439 { } 439 { }
440}; 440};
441 441
442void __init emev2_add_standard_devices_dt(void) 442static void __init emev2_add_standard_devices_dt(void)
443{ 443{
444 of_platform_populate(NULL, of_default_bus_match_table, 444 of_platform_populate(NULL, of_default_bus_match_table,
445 emev2_auxdata_lookup, NULL); 445 emev2_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
new file mode 100644
index 000000000000..c5a75a7a508f
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -0,0 +1,202 @@
1/*
2 * r8a73a4 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/kernel.h>
23#include <linux/of_platform.h>
24#include <linux/platform_data/irq-renesas-irqc.h>
25#include <linux/serial_sci.h>
26#include <mach/common.h>
27#include <mach/irqs.h>
28#include <mach/r8a73a4.h>
29#include <asm/mach/arch.h>
30
31static const struct resource pfc_resources[] = {
32 DEFINE_RES_MEM(0xe6050000, 0x9000),
33};
34
35void __init r8a73a4_pinmux_init(void)
36{
37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
38 ARRAY_SIZE(pfc_resources));
39}
40
41#define SCIF_COMMON(scif_type, baseaddr, irq) \
42 .type = scif_type, \
43 .mapbase = baseaddr, \
44 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
45 .scbrr_algo_id = SCBRR_ALGO_4, \
46 .irqs = SCIx_IRQ_MUXED(irq)
47
48#define SCIFA_DATA(index, baseaddr, irq) \
49[index] = { \
50 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
52}
53
54#define SCIFB_DATA(index, baseaddr, irq) \
55[index] = { \
56 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
57 .scscr = SCSCR_RE | SCSCR_TE, \
58}
59
60enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
61
62static const struct plat_sci_port scif[] = {
63 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
64 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
65 SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
66 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
67 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
68 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
69};
70
71static inline void r8a73a4_register_scif(int idx)
72{
73 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
74 sizeof(struct plat_sci_port));
75}
76
77static const struct renesas_irqc_config irqc0_data = {
78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
79};
80
81static const struct resource irqc0_resources[] = {
82 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
83 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
84 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
85 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
86 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
87 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
88 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
89 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
90 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
91 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
92 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
93 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
94 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
95 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
96 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
97 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
98 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
99 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
100 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
101 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
102 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
103 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
104 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
105 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
106 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
107 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
108 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
109 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
110 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
111 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
112 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
113 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
114 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
115};
116
117static const struct renesas_irqc_config irqc1_data = {
118 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
119};
120
121static const struct resource irqc1_resources[] = {
122 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
123 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
124 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
125 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
126 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
127 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
128 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
129 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
130 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
131 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
132 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
133 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
134 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
135 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
136 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
137 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
138 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
139 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
140 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
141 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
142 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
143 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
144 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
145 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
146 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
147 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
148 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
149};
150
151#define r8a73a4_register_irqc(idx) \
152 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
153 idx, irqc##idx##_resources, \
154 ARRAY_SIZE(irqc##idx##_resources), \
155 &irqc##idx##_data, \
156 sizeof(struct renesas_irqc_config))
157
158/* Thermal0 -> Thermal2 */
159static const struct resource thermal0_resources[] = {
160 DEFINE_RES_MEM(0xe61f0000, 0x14),
161 DEFINE_RES_MEM(0xe61f0100, 0x38),
162 DEFINE_RES_MEM(0xe61f0200, 0x38),
163 DEFINE_RES_MEM(0xe61f0300, 0x38),
164 DEFINE_RES_IRQ(gic_spi(69)),
165};
166
167#define r8a73a4_register_thermal() \
168 platform_device_register_simple("rcar_thermal", -1, \
169 thermal0_resources, \
170 ARRAY_SIZE(thermal0_resources))
171
172void __init r8a73a4_add_standard_devices(void)
173{
174 r8a73a4_register_scif(SCIFA0);
175 r8a73a4_register_scif(SCIFA1);
176 r8a73a4_register_scif(SCIFB0);
177 r8a73a4_register_scif(SCIFB1);
178 r8a73a4_register_scif(SCIFB2);
179 r8a73a4_register_scif(SCIFB3);
180 r8a73a4_register_irqc(0);
181 r8a73a4_register_irqc(1);
182 r8a73a4_register_thermal();
183}
184
185#ifdef CONFIG_USE_OF
186void __init r8a73a4_add_standard_devices_dt(void)
187{
188 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
189}
190
191static const char *r8a73a4_boards_compat_dt[] __initdata = {
192 "renesas,r8a73a4",
193 NULL,
194};
195
196DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
197 .init_irq = irqchip_init,
198 .init_machine = r8a73a4_add_standard_devices_dt,
199 .init_time = shmobile_timer_init,
200 .dt_compat = r8a73a4_boards_compat_dt,
201MACHINE_END
202#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8b85d4d8fab6..228d7aba4a7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
27#include <linux/serial_sci.h> 28#include <linux/serial_sci.h>
@@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void)
94 platform_device_register(&r8a7740_pfc_device); 95 platform_device_register(&r8a7740_pfc_device);
95} 96}
96 97
98static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
100};
101
102static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
104 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
105 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
106 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
107 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
108 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
109 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
110 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
111 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
112 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
113 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
114 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
115 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
116};
117
118static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
120 .id = 0,
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
123 .dev = {
124 .platform_data = &irqpin0_platform_data,
125 },
126};
127
128static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
130};
131
132static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
134 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
135 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
136 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
137 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
138 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
139 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
140 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
141 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
142 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
143 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
144 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
145 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
146};
147
148static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
150 .id = 1,
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
153 .dev = {
154 .platform_data = &irqpin1_platform_data,
155 },
156};
157
158static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
160};
161
162static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
164 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
165 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
166 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
167 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
168 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
169 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
170 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
171 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
172 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
173 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
174 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
175 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
176};
177
178static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
180 .id = 2,
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
183 .dev = {
184 .platform_data = &irqpin2_platform_data,
185 },
186};
187
188static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
190};
191
192static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
194 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
195 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
196 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
197 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
198 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
199 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
200 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
201 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
202 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
203 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
204 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
205 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
206};
207
208static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
210 .id = 3,
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
213 .dev = {
214 .platform_data = &irqpin3_platform_data,
215 },
216};
217
97/* SCIFA0 */ 218/* SCIFA0 */
98static struct plat_sci_port scif0_platform_data = { 219static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000, 220 .mapbase = 0xe6c40000,
@@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = {
101 .scscr = SCSCR_RE | SCSCR_TE, 222 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4, 223 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 224 .type = PORT_SCIFA,
104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), 225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
105}; 226};
106 227
107static struct platform_device scif0_device = { 228static struct platform_device scif0_device = {
@@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = {
119 .scscr = SCSCR_RE | SCSCR_TE, 240 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4, 241 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA, 242 .type = PORT_SCIFA,
122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), 243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
123}; 244};
124 245
125static struct platform_device scif1_device = { 246static struct platform_device scif1_device = {
@@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = {
137 .scscr = SCSCR_RE | SCSCR_TE, 258 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4, 259 .scbrr_algo_id = SCBRR_ALGO_4,
139 .type = PORT_SCIFA, 260 .type = PORT_SCIFA,
140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), 261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
141}; 262};
142 263
143static struct platform_device scif2_device = { 264static struct platform_device scif2_device = {
@@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = {
155 .scscr = SCSCR_RE | SCSCR_TE, 276 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4, 277 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA, 278 .type = PORT_SCIFA,
158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), 279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
159}; 280};
160 281
161static struct platform_device scif3_device = { 282static struct platform_device scif3_device = {
@@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE, 294 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4, 295 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFA, 296 .type = PORT_SCIFA,
176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), 297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
177}; 298};
178 299
179static struct platform_device scif4_device = { 300static struct platform_device scif4_device = {
@@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = {
191 .scscr = SCSCR_RE | SCSCR_TE, 312 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4, 313 .scbrr_algo_id = SCBRR_ALGO_4,
193 .type = PORT_SCIFA, 314 .type = PORT_SCIFA,
194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), 315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
195}; 316};
196 317
197static struct platform_device scif5_device = { 318static struct platform_device scif5_device = {
@@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = {
209 .scscr = SCSCR_RE | SCSCR_TE, 330 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4, 331 .scbrr_algo_id = SCBRR_ALGO_4,
211 .type = PORT_SCIFA, 332 .type = PORT_SCIFA,
212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), 333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
213}; 334};
214 335
215static struct platform_device scif6_device = { 336static struct platform_device scif6_device = {
@@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = {
227 .scscr = SCSCR_RE | SCSCR_TE, 348 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4, 349 .scbrr_algo_id = SCBRR_ALGO_4,
229 .type = PORT_SCIFA, 350 .type = PORT_SCIFA,
230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), 351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
231}; 352};
232 353
233static struct platform_device scif7_device = { 354static struct platform_device scif7_device = {
@@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = {
245 .scscr = SCSCR_RE | SCSCR_TE, 366 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4, 367 .scbrr_algo_id = SCBRR_ALGO_4,
247 .type = PORT_SCIFB, 368 .type = PORT_SCIFB,
248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), 369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
249}; 370};
250 371
251static struct platform_device scifb_device = { 372static struct platform_device scifb_device = {
@@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = {
273 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
274 }, 395 },
275 [1] = { 396 [1] = {
276 .start = evt2irq(0x0b00), 397 .start = gic_spi(58),
277 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
278 }, 399 },
279}; 400};
@@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = {
304 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
305 }, 426 },
306 [1] = { 427 [1] = {
307 .start = intcs_evt2irq(0xe80), 428 .start = gic_spi(198),
308 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
309 }, 430 },
310}; 431};
@@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = {
334 .flags = IORESOURCE_MEM, 455 .flags = IORESOURCE_MEM,
335 }, 456 },
336 [1] = { 457 [1] = {
337 .start = intcs_evt2irq(0xea0), 458 .start = gic_spi(199),
338 .flags = IORESOURCE_IRQ, 459 .flags = IORESOURCE_IRQ,
339 }, 460 },
340}; 461};
@@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = {
364 .flags = IORESOURCE_MEM, 485 .flags = IORESOURCE_MEM,
365 }, 486 },
366 [1] = { 487 [1] = {
367 .start = intcs_evt2irq(0xec0), 488 .start = gic_spi(200),
368 .flags = IORESOURCE_IRQ, 489 .flags = IORESOURCE_IRQ,
369 }, 490 },
370}; 491};
@@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = {
411}; 532};
412 533
413static struct platform_device *r8a7740_early_devices[] __initdata = { 534static struct platform_device *r8a7740_early_devices[] __initdata = {
535 &irqpin0_device,
536 &irqpin1_device,
537 &irqpin2_device,
538 &irqpin3_device,
414 &scif0_device, 539 &scif0_device,
415 &scif1_device, 540 &scif1_device,
416 &scif2_device, 541 &scif2_device,
@@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = {
525 }, 650 },
526 { 651 {
527 .name = "error_irq", 652 .name = "error_irq",
528 .start = evt2irq(0x20c0), 653 .start = gic_spi(34),
529 .end = evt2irq(0x20c0), 654 .end = gic_spi(34),
530 .flags = IORESOURCE_IRQ, 655 .flags = IORESOURCE_IRQ,
531 }, 656 },
532 { 657 {
533 /* IRQ for channels 0-5 */ 658 /* IRQ for channels 0-5 */
534 .start = evt2irq(0x2000), 659 .start = gic_spi(28),
535 .end = evt2irq(0x20a0), 660 .end = gic_spi(33),
536 .flags = IORESOURCE_IRQ, 661 .flags = IORESOURCE_IRQ,
537 }, 662 },
538}; 663};
@@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = {
553 }, 678 },
554 { 679 {
555 .name = "error_irq", 680 .name = "error_irq",
556 .start = evt2irq(0x21c0), 681 .start = gic_spi(41),
557 .end = evt2irq(0x21c0), 682 .end = gic_spi(41),
558 .flags = IORESOURCE_IRQ, 683 .flags = IORESOURCE_IRQ,
559 }, 684 },
560 { 685 {
561 /* IRQ for channels 0-5 */ 686 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2100), 687 .start = gic_spi(35),
563 .end = evt2irq(0x21a0), 688 .end = gic_spi(40),
564 .flags = IORESOURCE_IRQ, 689 .flags = IORESOURCE_IRQ,
565 }, 690 },
566}; 691};
@@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = {
581 }, 706 },
582 { 707 {
583 .name = "error_irq", 708 .name = "error_irq",
584 .start = evt2irq(0x22c0), 709 .start = gic_spi(48),
585 .end = evt2irq(0x22c0), 710 .end = gic_spi(48),
586 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
587 }, 712 },
588 { 713 {
589 /* IRQ for channels 0-5 */ 714 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2200), 715 .start = gic_spi(42),
591 .end = evt2irq(0x22a0), 716 .end = gic_spi(47),
592 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
593 }, 718 },
594}; 719};
@@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = {
677 }, 802 },
678 { 803 {
679 /* IRQ for channels */ 804 /* IRQ for channels */
680 .start = evt2irq(0x0a00), 805 .start = gic_spi(49),
681 .end = evt2irq(0x0a00), 806 .end = gic_spi(49),
682 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
683 }, 808 },
684}; 809};
@@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = {
702 .flags = IORESOURCE_MEM, 827 .flags = IORESOURCE_MEM,
703 }, 828 },
704 [1] = { 829 [1] = {
705 .start = intcs_evt2irq(0xe00), 830 .start = gic_spi(201),
706 .end = intcs_evt2irq(0xe60), 831 .end = gic_spi(204),
707 .flags = IORESOURCE_IRQ, 832 .flags = IORESOURCE_IRQ,
708 }, 833 },
709}; 834};
@@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = {
716 .flags = IORESOURCE_MEM, 841 .flags = IORESOURCE_MEM,
717 }, 842 },
718 [1] = { 843 [1] = {
719 .start = evt2irq(0x780), /* IIC1_ALI1 */ 844 .start = gic_spi(70), /* IIC1_ALI1 */
720 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ 845 .end = gic_spi(73), /* IIC1_DTEI1 */
721 .flags = IORESOURCE_IRQ, 846 .flags = IORESOURCE_IRQ,
722 }, 847 },
723}; 848};
@@ -738,8 +863,8 @@ static struct platform_device i2c1_device = {
738 863
739static struct resource pmu_resources[] = { 864static struct resource pmu_resources[] = {
740 [0] = { 865 [0] = {
741 .start = evt2irq(0x19a0), 866 .start = gic_spi(83),
742 .end = evt2irq(0x19a0), 867 .end = gic_spi(83),
743 .flags = IORESOURCE_IRQ, 868 .flags = IORESOURCE_IRQ,
744 }, 869 },
745}; 870};
@@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
904 .map_io = r8a7740_map_io, 1029 .map_io = r8a7740_map_io,
905 .init_early = r8a7740_add_early_devices_dt, 1030 .init_early = r8a7740_add_early_devices_dt,
906 .init_irq = r8a7740_init_irq, 1031 .init_irq = r8a7740_init_irq,
907 .handle_irq = shmobile_handle_irq_intc,
908 .init_machine = r8a7740_add_standard_devices_dt, 1032 .init_machine = r8a7740_add_standard_devices_dt,
909 .init_time = shmobile_timer_init, 1033 .init_time = shmobile_timer_init,
910 .dt_compat = r8a7740_boards_compat_dt, 1034 .dt_compat = r8a7740_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
new file mode 100644
index 000000000000..01c62bedf9cf
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -0,0 +1,193 @@
1/*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/irqchip/arm-gic.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_device.h>
27#include <linux/irqchip.h>
28#include <linux/serial_sci.h>
29#include <linux/sh_timer.h>
30#include <mach/irqs.h>
31#include <mach/r8a7778.h>
32#include <mach/common.h>
33#include <asm/mach/arch.h>
34#include <asm/hardware/cache-l2x0.h>
35
36/* SCIF */
37#define SCIF_INFO(baseaddr, irq) \
38{ \
39 .mapbase = baseaddr, \
40 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
42 .scbrr_algo_id = SCBRR_ALGO_2, \
43 .type = PORT_SCIF, \
44 .irqs = SCIx_IRQ_MUXED(irq), \
45}
46
47static struct plat_sci_port scif_platform_data[] = {
48 SCIF_INFO(0xffe40000, gic_iid(0x66)),
49 SCIF_INFO(0xffe41000, gic_iid(0x67)),
50 SCIF_INFO(0xffe42000, gic_iid(0x68)),
51 SCIF_INFO(0xffe43000, gic_iid(0x69)),
52 SCIF_INFO(0xffe44000, gic_iid(0x6a)),
53 SCIF_INFO(0xffe45000, gic_iid(0x6b)),
54};
55
56/* TMU */
57static struct resource sh_tmu0_resources[] = {
58 DEFINE_RES_MEM(0xffd80008, 12),
59 DEFINE_RES_IRQ(gic_iid(0x40)),
60};
61
62static struct sh_timer_config sh_tmu0_platform_data = {
63 .name = "TMU00",
64 .channel_offset = 0x4,
65 .timer_bit = 0,
66 .clockevent_rating = 200,
67};
68
69static struct resource sh_tmu1_resources[] = {
70 DEFINE_RES_MEM(0xffd80014, 12),
71 DEFINE_RES_IRQ(gic_iid(0x41)),
72};
73
74static struct sh_timer_config sh_tmu1_platform_data = {
75 .name = "TMU01",
76 .channel_offset = 0x10,
77 .timer_bit = 1,
78 .clocksource_rating = 200,
79};
80
81#define PLATFORM_INFO(n, i) \
82{ \
83 .parent = &platform_bus, \
84 .name = #n, \
85 .id = i, \
86 .res = n ## i ## _resources, \
87 .num_res = ARRAY_SIZE(n ## i ##_resources), \
88 .data = &n ## i ##_platform_data, \
89 .size_data = sizeof(n ## i ## _platform_data), \
90}
91
92struct platform_device_info platform_devinfo[] = {
93 PLATFORM_INFO(sh_tmu, 0),
94 PLATFORM_INFO(sh_tmu, 1),
95};
96
97void __init r8a7778_add_standard_devices(void)
98{
99 int i;
100
101#ifdef CONFIG_CACHE_L2X0
102 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
103 if (base) {
104 /*
105 * Early BRESP enable, Shared attribute override enable, 64K*16way
106 * don't call iounmap(base)
107 */
108 l2x0_init(base, 0x40470000, 0x82000fff);
109 }
110#endif
111
112 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
113 platform_device_register_data(&platform_bus, "sh-sci", i,
114 &scif_platform_data[i],
115 sizeof(struct plat_sci_port));
116
117 for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
118 platform_device_register_full(&platform_devinfo[i]);
119}
120
121#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
122#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
123
124#define INT2NTSR0 0x00018 /* 0xfe700018 */
125#define INT2NTSR1 0x0002c /* 0xfe70002c */
126static void __init r8a7778_init_irq_common(void)
127{
128 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
129
130 BUG_ON(!base);
131
132 /* route all interrupts to ARM */
133 __raw_writel(0x73ffffff, base + INT2NTSR0);
134 __raw_writel(0xffffffff, base + INT2NTSR1);
135
136 /* unmask all known interrupts in INTCS2 */
137 __raw_writel(0x08330773, base + INT2SMSKCR0);
138 __raw_writel(0x00311110, base + INT2SMSKCR1);
139
140 iounmap(base);
141}
142
143void __init r8a7778_init_irq(void)
144{
145 void __iomem *gic_dist_base;
146 void __iomem *gic_cpu_base;
147
148 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
149 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
150 BUG_ON(!gic_dist_base || !gic_cpu_base);
151
152 /* use GIC to handle interrupts */
153 gic_init(0, 29, gic_dist_base, gic_cpu_base);
154
155 r8a7778_init_irq_common();
156}
157
158void __init r8a7778_init_delay(void)
159{
160 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
161}
162
163#ifdef CONFIG_USE_OF
164void __init r8a7778_init_irq_dt(void)
165{
166 irqchip_init();
167 r8a7778_init_irq_common();
168}
169
170static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
171 {},
172};
173
174void __init r8a7778_add_standard_devices_dt(void)
175{
176 of_platform_populate(NULL, of_default_bus_match_table,
177 r8a7778_auxdata_lookup, NULL);
178}
179
180static const char *r8a7778_compat_dt[] __initdata = {
181 "renesas,r8a7778",
182 NULL,
183};
184
185DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
186 .init_early = r8a7778_init_delay,
187 .init_irq = r8a7778_init_irq_dt,
188 .init_machine = r8a7778_add_standard_devices_dt,
189 .init_time = shmobile_timer_init,
190 .dt_compat = r8a7778_compat_dt,
191MACHINE_END
192
193#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index c54ff9b29fe5..042df35e71a0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/of_platform.h>
24#include <linux/platform_device.h> 25#include <linux/platform_device.h>
25#include <linux/delay.h> 26#include <linux/delay.h>
26#include <linux/input.h> 27#include <linux/input.h>
@@ -28,6 +29,7 @@
28#include <linux/serial_sci.h> 29#include <linux/serial_sci.h>
29#include <linux/sh_intc.h> 30#include <linux/sh_intc.h>
30#include <linux/sh_timer.h> 31#include <linux/sh_timer.h>
32#include <linux/dma-mapping.h>
31#include <mach/hardware.h> 33#include <mach/hardware.h>
32#include <mach/irqs.h> 34#include <mach/irqs.h>
33#include <mach/r8a7779.h> 35#include <mach/r8a7779.h>
@@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = {
91 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 93 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
92 .scbrr_algo_id = SCBRR_ALGO_2, 94 .scbrr_algo_id = SCBRR_ALGO_2,
93 .type = PORT_SCIF, 95 .type = PORT_SCIF,
94 .irqs = SCIx_IRQ_MUXED(gic_spi(88)), 96 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
95}; 97};
96 98
97static struct platform_device scif0_device = { 99static struct platform_device scif0_device = {
@@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = {
108 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 110 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
109 .scbrr_algo_id = SCBRR_ALGO_2, 111 .scbrr_algo_id = SCBRR_ALGO_2,
110 .type = PORT_SCIF, 112 .type = PORT_SCIF,
111 .irqs = SCIx_IRQ_MUXED(gic_spi(89)), 113 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
112}; 114};
113 115
114static struct platform_device scif1_device = { 116static struct platform_device scif1_device = {
@@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = {
125 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 127 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
126 .scbrr_algo_id = SCBRR_ALGO_2, 128 .scbrr_algo_id = SCBRR_ALGO_2,
127 .type = PORT_SCIF, 129 .type = PORT_SCIF,
128 .irqs = SCIx_IRQ_MUXED(gic_spi(90)), 130 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
129}; 131};
130 132
131static struct platform_device scif2_device = { 133static struct platform_device scif2_device = {
@@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = {
142 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 144 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
143 .scbrr_algo_id = SCBRR_ALGO_2, 145 .scbrr_algo_id = SCBRR_ALGO_2,
144 .type = PORT_SCIF, 146 .type = PORT_SCIF,
145 .irqs = SCIx_IRQ_MUXED(gic_spi(91)), 147 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
146}; 148};
147 149
148static struct platform_device scif3_device = { 150static struct platform_device scif3_device = {
@@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = {
159 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 161 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
160 .scbrr_algo_id = SCBRR_ALGO_2, 162 .scbrr_algo_id = SCBRR_ALGO_2,
161 .type = PORT_SCIF, 163 .type = PORT_SCIF,
162 .irqs = SCIx_IRQ_MUXED(gic_spi(92)), 164 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
163}; 165};
164 166
165static struct platform_device scif4_device = { 167static struct platform_device scif4_device = {
@@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = {
176 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 178 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
177 .scbrr_algo_id = SCBRR_ALGO_2, 179 .scbrr_algo_id = SCBRR_ALGO_2,
178 .type = PORT_SCIF, 180 .type = PORT_SCIF,
179 .irqs = SCIx_IRQ_MUXED(gic_spi(93)), 181 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
180}; 182};
181 183
182static struct platform_device scif5_device = { 184static struct platform_device scif5_device = {
@@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = {
203 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
204 }, 206 },
205 [1] = { 207 [1] = {
206 .start = gic_spi(32), 208 .start = gic_iid(0x40),
207 .flags = IORESOURCE_IRQ, 209 .flags = IORESOURCE_IRQ,
208 }, 210 },
209}; 211};
@@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = {
233 .flags = IORESOURCE_MEM, 235 .flags = IORESOURCE_MEM,
234 }, 236 },
235 [1] = { 237 [1] = {
236 .start = gic_spi(33), 238 .start = gic_iid(0x41),
237 .flags = IORESOURCE_IRQ, 239 .flags = IORESOURCE_IRQ,
238 }, 240 },
239}; 241};
@@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = {
255 .end = 0xffc70fff, 257 .end = 0xffc70fff,
256 .flags = IORESOURCE_MEM, 258 .flags = IORESOURCE_MEM,
257 }, { 259 }, {
258 .start = gic_spi(79), 260 .start = gic_iid(0x6f),
259 .flags = IORESOURCE_IRQ, 261 .flags = IORESOURCE_IRQ,
260 }, 262 },
261}; 263};
@@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = {
273 .end = 0xffc71fff, 275 .end = 0xffc71fff,
274 .flags = IORESOURCE_MEM, 276 .flags = IORESOURCE_MEM,
275 }, { 277 }, {
276 .start = gic_spi(82), 278 .start = gic_iid(0x72),
277 .flags = IORESOURCE_IRQ, 279 .flags = IORESOURCE_IRQ,
278 }, 280 },
279}; 281};
@@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = {
291 .end = 0xffc72fff, 293 .end = 0xffc72fff,
292 .flags = IORESOURCE_MEM, 294 .flags = IORESOURCE_MEM,
293 }, { 295 }, {
294 .start = gic_spi(80), 296 .start = gic_iid(0x70),
295 .flags = IORESOURCE_IRQ, 297 .flags = IORESOURCE_IRQ,
296 }, 298 },
297}; 299};
@@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = {
309 .end = 0xffc73fff, 311 .end = 0xffc73fff,
310 .flags = IORESOURCE_MEM, 312 .flags = IORESOURCE_MEM,
311 }, { 313 }, {
312 .start = gic_spi(81), 314 .start = gic_iid(0x71),
313 .flags = IORESOURCE_IRQ, 315 .flags = IORESOURCE_IRQ,
314 }, 316 },
315}; 317};
@@ -321,7 +323,31 @@ static struct platform_device i2c3_device = {
321 .num_resources = ARRAY_SIZE(rcar_i2c3_res), 323 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
322}; 324};
323 325
324static struct platform_device *r8a7779_early_devices[] __initdata = { 326static struct resource sata_resources[] = {
327 [0] = {
328 .name = "rcar-sata",
329 .start = 0xfc600000,
330 .end = 0xfc601fff,
331 .flags = IORESOURCE_MEM,
332 },
333 [1] = {
334 .start = gic_iid(0x84),
335 .flags = IORESOURCE_IRQ,
336 },
337};
338
339static struct platform_device sata_device = {
340 .name = "sata_rcar",
341 .id = -1,
342 .resource = sata_resources,
343 .num_resources = ARRAY_SIZE(sata_resources),
344 .dev = {
345 .dma_mask = &sata_device.dev.coherent_dma_mask,
346 .coherent_dma_mask = DMA_BIT_MASK(32),
347 },
348};
349
350static struct platform_device *r8a7779_devices_dt[] __initdata = {
325 &scif0_device, 351 &scif0_device,
326 &scif1_device, 352 &scif1_device,
327 &scif2_device, 353 &scif2_device,
@@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
330 &scif5_device, 356 &scif5_device,
331 &tmu00_device, 357 &tmu00_device,
332 &tmu01_device, 358 &tmu01_device,
359};
360
361static struct platform_device *r8a7779_late_devices[] __initdata = {
333 &i2c0_device, 362 &i2c0_device,
334 &i2c1_device, 363 &i2c1_device,
335 &i2c2_device, 364 &i2c2_device,
336 &i2c3_device, 365 &i2c3_device,
337}; 366 &sata_device,
338
339static struct platform_device *r8a7779_late_devices[] __initdata = {
340}; 367};
341 368
342void __init r8a7779_add_standard_devices(void) 369void __init r8a7779_add_standard_devices(void)
@@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void)
349 376
350 r8a7779_init_pm_domains(); 377 r8a7779_init_pm_domains();
351 378
352 platform_add_devices(r8a7779_early_devices, 379 platform_add_devices(r8a7779_devices_dt,
353 ARRAY_SIZE(r8a7779_early_devices)); 380 ARRAY_SIZE(r8a7779_devices_dt));
354 platform_add_devices(r8a7779_late_devices, 381 platform_add_devices(r8a7779_late_devices,
355 ARRAY_SIZE(r8a7779_late_devices)); 382 ARRAY_SIZE(r8a7779_late_devices));
356} 383}
@@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void)
367 394
368void __init r8a7779_add_early_devices(void) 395void __init r8a7779_add_early_devices(void)
369{ 396{
370 early_platform_add_devices(r8a7779_early_devices, 397 early_platform_add_devices(r8a7779_devices_dt,
371 ARRAY_SIZE(r8a7779_early_devices)); 398 ARRAY_SIZE(r8a7779_devices_dt));
372 399
373 /* Early serial console setup is not included here due to 400 /* Early serial console setup is not included here due to
374 * memory map collisions. The SCIF serial ports in r8a7779 401 * memory map collisions. The SCIF serial ports in r8a7779
@@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void)
386 * command line in case of the marzen board. 413 * command line in case of the marzen board.
387 */ 414 */
388} 415}
416
417#ifdef CONFIG_USE_OF
418void __init r8a7779_init_delay(void)
419{
420 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
421}
422
423static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
424 {},
425};
426
427void __init r8a7779_add_standard_devices_dt(void)
428{
429 /* clocks are setup late during boot in the case of DT */
430 r8a7779_clock_init();
431
432 platform_add_devices(r8a7779_devices_dt,
433 ARRAY_SIZE(r8a7779_devices_dt));
434 of_platform_populate(NULL, of_default_bus_match_table,
435 r8a7779_auxdata_lookup, NULL);
436}
437
438static const char *r8a7779_compat_dt[] __initdata = {
439 "renesas,r8a7779",
440 NULL,
441};
442
443DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
444 .map_io = r8a7779_map_io,
445 .init_early = r8a7779_init_delay,
446 .nr_irqs = NR_IRQS_LEGACY,
447 .init_irq = r8a7779_init_irq_dt,
448 .init_machine = r8a7779_add_standard_devices_dt,
449 .init_time = shmobile_timer_init,
450 .dt_compat = r8a7779_compat_dt,
451MACHINE_END
452#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
new file mode 100644
index 000000000000..481201a4f3f5
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -0,0 +1,137 @@
1/*
2 * r8a7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/irq.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h>
24#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/platform_data/irq-renesas-irqc.h>
27#include <mach/common.h>
28#include <mach/irqs.h>
29#include <mach/r8a7790.h>
30#include <asm/mach/arch.h>
31
32static const struct resource pfc_resources[] = {
33 DEFINE_RES_MEM(0xe6060000, 0x250),
34};
35
36void __init r8a7790_pinmux_init(void)
37{
38 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
39 ARRAY_SIZE(pfc_resources));
40}
41
42#define SCIF_COMMON(scif_type, baseaddr, irq) \
43 .type = scif_type, \
44 .mapbase = baseaddr, \
45 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
46 .irqs = SCIx_IRQ_MUXED(irq)
47
48#define SCIFA_DATA(index, baseaddr, irq) \
49[index] = { \
50 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
51 .scbrr_algo_id = SCBRR_ALGO_4, \
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
53}
54
55#define SCIFB_DATA(index, baseaddr, irq) \
56[index] = { \
57 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
58 .scbrr_algo_id = SCBRR_ALGO_4, \
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61
62#define SCIF_DATA(index, baseaddr, irq) \
63[index] = { \
64 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
65 .scbrr_algo_id = SCBRR_ALGO_2, \
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
67}
68
69enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
70
71static const struct plat_sci_port scif[] = {
72 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
73 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
74 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
75 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
76 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
77 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
78 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
79 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
80};
81
82static inline void r8a7790_register_scif(int idx)
83{
84 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
85 sizeof(struct plat_sci_port));
86}
87
88static struct renesas_irqc_config irqc0_data = {
89 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
90};
91
92static struct resource irqc0_resources[] = {
93 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
94 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
95 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
96 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
97 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
98};
99
100#define r8a7790_register_irqc(idx) \
101 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
102 idx, irqc##idx##_resources, \
103 ARRAY_SIZE(irqc##idx##_resources), \
104 &irqc##idx##_data, \
105 sizeof(struct renesas_irqc_config))
106
107void __init r8a7790_add_standard_devices(void)
108{
109 r8a7790_register_scif(SCIFA0);
110 r8a7790_register_scif(SCIFA1);
111 r8a7790_register_scif(SCIFB0);
112 r8a7790_register_scif(SCIFB1);
113 r8a7790_register_scif(SCIFB2);
114 r8a7790_register_scif(SCIFA2);
115 r8a7790_register_scif(SCIF0);
116 r8a7790_register_scif(SCIF1);
117 r8a7790_register_irqc(0);
118}
119
120#ifdef CONFIG_USE_OF
121void __init r8a7790_add_standard_devices_dt(void)
122{
123 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
124}
125
126static const char *r8a7790_boards_compat_dt[] __initdata = {
127 "renesas,r8a7790",
128 NULL,
129};
130
131DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
132 .init_irq = irqchip_init,
133 .init_machine = r8a7790_add_standard_devices_dt,
134 .init_time = shmobile_timer_init,
135 .dt_compat = r8a7790_boards_compat_dt,
136MACHINE_END
137#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index bdab575f88bc..e8cd93a5c550 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,6 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqchip.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
27#include <linux/delay.h> 28#include <linux/delay.h>
@@ -32,6 +33,7 @@
32#include <linux/sh_intc.h> 33#include <linux/sh_intc.h>
33#include <linux/sh_timer.h> 34#include <linux/sh_timer.h>
34#include <linux/platform_data/sh_ipmmu.h> 35#include <linux/platform_data/sh_ipmmu.h>
36#include <linux/platform_data/irq-renesas-intc-irqpin.h>
35#include <mach/dma-register.h> 37#include <mach/dma-register.h>
36#include <mach/hardware.h> 38#include <mach/hardware.h>
37#include <mach/irqs.h> 39#include <mach/irqs.h>
@@ -810,7 +812,128 @@ static struct platform_device ipmmu_device = {
810 .num_resources = ARRAY_SIZE(ipmmu_resources), 812 .num_resources = ARRAY_SIZE(ipmmu_resources),
811}; 813};
812 814
813static struct platform_device *sh73a0_early_devices_dt[] __initdata = { 815static struct renesas_intc_irqpin_config irqpin0_platform_data = {
816 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
817};
818
819static struct resource irqpin0_resources[] = {
820 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
821 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
822 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
823 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
824 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
825 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
826 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
827 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
828 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
829 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
830 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
831 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
832 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
833};
834
835static struct platform_device irqpin0_device = {
836 .name = "renesas_intc_irqpin",
837 .id = 0,
838 .resource = irqpin0_resources,
839 .num_resources = ARRAY_SIZE(irqpin0_resources),
840 .dev = {
841 .platform_data = &irqpin0_platform_data,
842 },
843};
844
845static struct renesas_intc_irqpin_config irqpin1_platform_data = {
846 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
847 .control_parent = true, /* Disable spurious IRQ10 */
848};
849
850static struct resource irqpin1_resources[] = {
851 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
852 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
853 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
854 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
855 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
856 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
857 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
858 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
859 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
860 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
861 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
862 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
863 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
864};
865
866static struct platform_device irqpin1_device = {
867 .name = "renesas_intc_irqpin",
868 .id = 1,
869 .resource = irqpin1_resources,
870 .num_resources = ARRAY_SIZE(irqpin1_resources),
871 .dev = {
872 .platform_data = &irqpin1_platform_data,
873 },
874};
875
876static struct renesas_intc_irqpin_config irqpin2_platform_data = {
877 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
878};
879
880static struct resource irqpin2_resources[] = {
881 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
882 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
883 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
884 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
885 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
886 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
887 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
888 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
889 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
890 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
891 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
892 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
893 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
894};
895
896static struct platform_device irqpin2_device = {
897 .name = "renesas_intc_irqpin",
898 .id = 2,
899 .resource = irqpin2_resources,
900 .num_resources = ARRAY_SIZE(irqpin2_resources),
901 .dev = {
902 .platform_data = &irqpin2_platform_data,
903 },
904};
905
906static struct renesas_intc_irqpin_config irqpin3_platform_data = {
907 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
908};
909
910static struct resource irqpin3_resources[] = {
911 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
912 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
913 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
914 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
915 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
916 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
917 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
918 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
919 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
920 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
921 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
922 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
923 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
924};
925
926static struct platform_device irqpin3_device = {
927 .name = "renesas_intc_irqpin",
928 .id = 3,
929 .resource = irqpin3_resources,
930 .num_resources = ARRAY_SIZE(irqpin3_resources),
931 .dev = {
932 .platform_data = &irqpin3_platform_data,
933 },
934};
935
936static struct platform_device *sh73a0_devices_dt[] __initdata = {
814 &scif0_device, 937 &scif0_device,
815 &scif1_device, 938 &scif1_device,
816 &scif2_device, 939 &scif2_device,
@@ -838,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
838 &dma0_device, 961 &dma0_device,
839 &mpdma0_device, 962 &mpdma0_device,
840 &pmu_device, 963 &pmu_device,
964 &irqpin0_device,
965 &irqpin1_device,
966 &irqpin2_device,
967 &irqpin3_device,
841}; 968};
842 969
843#define SRCR2 IOMEM(0xe61580b0) 970#define SRCR2 IOMEM(0xe61580b0)
@@ -847,8 +974,8 @@ void __init sh73a0_add_standard_devices(void)
847 /* Clear software reset bit on SY-DMAC module */ 974 /* Clear software reset bit on SY-DMAC module */
848 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 975 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
849 976
850 platform_add_devices(sh73a0_early_devices_dt, 977 platform_add_devices(sh73a0_devices_dt,
851 ARRAY_SIZE(sh73a0_early_devices_dt)); 978 ARRAY_SIZE(sh73a0_devices_dt));
852 platform_add_devices(sh73a0_early_devices, 979 platform_add_devices(sh73a0_early_devices,
853 ARRAY_SIZE(sh73a0_early_devices)); 980 ARRAY_SIZE(sh73a0_early_devices));
854 platform_add_devices(sh73a0_late_devices, 981 platform_add_devices(sh73a0_late_devices,
@@ -867,8 +994,8 @@ void __init sh73a0_earlytimer_init(void)
867 994
868void __init sh73a0_add_early_devices(void) 995void __init sh73a0_add_early_devices(void)
869{ 996{
870 early_platform_add_devices(sh73a0_early_devices_dt, 997 early_platform_add_devices(sh73a0_devices_dt,
871 ARRAY_SIZE(sh73a0_early_devices_dt)); 998 ARRAY_SIZE(sh73a0_devices_dt));
872 early_platform_add_devices(sh73a0_early_devices, 999 early_platform_add_devices(sh73a0_early_devices,
873 ARRAY_SIZE(sh73a0_early_devices)); 1000 ARRAY_SIZE(sh73a0_early_devices));
874 1001
@@ -878,23 +1005,9 @@ void __init sh73a0_add_early_devices(void)
878 1005
879#ifdef CONFIG_USE_OF 1006#ifdef CONFIG_USE_OF
880 1007
881/* Please note that the clock initialisation shcheme used in 1008void __init sh73a0_init_delay(void)
882 * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
883 * does not work with SMP as there is a yet to be resolved lock-up in
884 * workqueue initialisation.
885 *
886 * CONFIG_SMP should be disabled when using this code.
887 */
888
889void __init sh73a0_add_early_devices_dt(void)
890{ 1009{
891 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ 1010 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
892
893 early_platform_add_devices(sh73a0_early_devices_dt,
894 ARRAY_SIZE(sh73a0_early_devices_dt));
895
896 /* setup early console here as well */
897 shmobile_setup_console();
898} 1011}
899 1012
900static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { 1013static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
@@ -906,8 +1019,8 @@ void __init sh73a0_add_standard_devices_dt(void)
906 /* clocks are setup late during boot in the case of DT */ 1019 /* clocks are setup late during boot in the case of DT */
907 sh73a0_clock_init(); 1020 sh73a0_clock_init();
908 1021
909 platform_add_devices(sh73a0_early_devices_dt, 1022 platform_add_devices(sh73a0_devices_dt,
910 ARRAY_SIZE(sh73a0_early_devices_dt)); 1023 ARRAY_SIZE(sh73a0_devices_dt));
911 of_platform_populate(NULL, of_default_bus_match_table, 1024 of_platform_populate(NULL, of_default_bus_match_table,
912 sh73a0_auxdata_lookup, NULL); 1025 sh73a0_auxdata_lookup, NULL);
913} 1026}
@@ -918,10 +1031,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
918}; 1031};
919 1032
920DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") 1033DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
1034 .smp = smp_ops(sh73a0_smp_ops),
921 .map_io = sh73a0_map_io, 1035 .map_io = sh73a0_map_io,
922 .init_early = sh73a0_add_early_devices_dt, 1036 .init_early = sh73a0_init_delay,
923 .nr_irqs = NR_IRQS_LEGACY, 1037 .nr_irqs = NR_IRQS_LEGACY,
924 .init_irq = sh73a0_init_irq_dt, 1038 .init_irq = irqchip_init,
925 .init_machine = sh73a0_add_standard_devices_dt, 1039 .init_machine = sh73a0_add_standard_devices_dt,
926 .init_time = shmobile_timer_init, 1040 .init_time = shmobile_timer_init,
927 .dt_compat = sh73a0_boards_compat_dt, 1041 .dt_compat = sh73a0_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f9388d..8225c16b371b 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -28,63 +28,9 @@
28#include <mach/emev2.h> 28#include <mach/emev2.h>
29#include <asm/smp_plat.h> 29#include <asm/smp_plat.h>
30#include <asm/smp_scu.h> 30#include <asm/smp_scu.h>
31#include <asm/cacheflush.h>
32 31
33#define EMEV2_SCU_BASE 0x1e000000 32#define EMEV2_SCU_BASE 0x1e000000
34 33
35static DEFINE_SPINLOCK(scu_lock);
36static void __iomem *scu_base;
37
38static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
39{
40 unsigned long tmp;
41
42 /* we assume this code is running on a different cpu
43 * than the one that is changing coherency setting */
44 spin_lock(&scu_lock);
45 tmp = readl(scu_base + 8);
46 tmp &= ~clr;
47 tmp |= set;
48 writel(tmp, scu_base + 8);
49 spin_unlock(&scu_lock);
50
51}
52
53static unsigned int __init emev2_get_core_count(void)
54{
55 if (!scu_base) {
56 scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
57 emev2_clock_init(); /* need ioremapped SMU */
58 }
59
60 WARN_ON_ONCE(!scu_base);
61
62 return scu_base ? scu_get_core_count(scu_base) : 1;
63}
64
65static int emev2_platform_cpu_kill(unsigned int cpu)
66{
67 return 0; /* not supported yet */
68}
69
70static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
71{
72 int k;
73
74 /* this function is running on another CPU than the offline target,
75 * here we need wait for shutdown code in platform_cpu_die() to
76 * finish before asking SoC-specific code to power off the CPU core.
77 */
78 for (k = 0; k < 1000; k++) {
79 if (shmobile_cpu_is_dead(cpu))
80 return emev2_platform_cpu_kill(cpu);
81 mdelay(1);
82 }
83
84 return 0;
85}
86
87
88static void __cpuinit emev2_secondary_init(unsigned int cpu) 34static void __cpuinit emev2_secondary_init(unsigned int cpu)
89{ 35{
90 gic_secondary_init(0); 36 gic_secondary_init(0);
@@ -92,31 +38,30 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu)
92 38
93static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) 39static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
94{ 40{
95 cpu = cpu_logical_map(cpu); 41 arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
96
97 /* enable cache coherency */
98 modify_scu_cpu_psr(0, 3 << (cpu * 8));
99
100 /* Tell ROM loader about our vector (in headsmp.S) */
101 emev2_set_boot_vector(__pa(shmobile_secondary_vector));
102
103 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
104 return 0; 42 return 0;
105} 43}
106 44
107static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) 45static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
108{ 46{
109 int cpu = cpu_logical_map(0); 47 scu_enable(shmobile_scu_base);
110 48
111 scu_enable(scu_base); 49 /* Tell ROM loader about our vector (in headsmp-scu.S) */
50 emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
112 51
113 /* enable cache coherency on CPU0 */ 52 /* enable cache coherency on booting CPU */
114 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 53 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
115} 54}
116 55
117static void __init emev2_smp_init_cpus(void) 56static void __init emev2_smp_init_cpus(void)
118{ 57{
119 unsigned int ncores = emev2_get_core_count(); 58 unsigned int ncores;
59
60 /* setup EMEV2 specific SCU base */
61 shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
62 emev2_clock_init(); /* need ioremapped SMU */
63
64 ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
120 65
121 shmobile_smp_init_cpus(ncores); 66 shmobile_smp_init_cpus(ncores);
122} 67}
@@ -126,9 +71,4 @@ struct smp_operations emev2_smp_ops __initdata = {
126 .smp_prepare_cpus = emev2_smp_prepare_cpus, 71 .smp_prepare_cpus = emev2_smp_prepare_cpus,
127 .smp_secondary_init = emev2_secondary_init, 72 .smp_secondary_init = emev2_secondary_init,
128 .smp_boot_secondary = emev2_boot_secondary, 73 .smp_boot_secondary = emev2_boot_secondary,
129#ifdef CONFIG_HOTPLUG_CPU
130 .cpu_kill = emev2_cpu_kill,
131 .cpu_die = shmobile_cpu_die,
132 .cpu_disable = shmobile_cpu_disable,
133#endif
134}; 74};
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf23edcf..ea4535a5c4e2 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -26,11 +26,13 @@
26#include <linux/irqchip/arm-gic.h> 26#include <linux/irqchip/arm-gic.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/r8a7779.h> 28#include <mach/r8a7779.h>
29#include <asm/cacheflush.h>
29#include <asm/smp_plat.h> 30#include <asm/smp_plat.h>
30#include <asm/smp_scu.h> 31#include <asm/smp_scu.h>
31#include <asm/smp_twd.h> 32#include <asm/smp_twd.h>
32 33
33#define AVECR IOMEM(0xfe700040) 34#define AVECR IOMEM(0xfe700040)
35#define R8A7779_SCU_BASE 0xf0000000
34 36
35static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { 37static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
36 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ 38 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -56,44 +58,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
56 [3] = &r8a7779_ch_cpu3, 58 [3] = &r8a7779_ch_cpu3,
57}; 59};
58 60
59static void __iomem *scu_base_addr(void)
60{
61 return (void __iomem *)0xf0000000;
62}
63
64static DEFINE_SPINLOCK(scu_lock);
65static unsigned long tmp;
66
67#ifdef CONFIG_HAVE_ARM_TWD 61#ifdef CONFIG_HAVE_ARM_TWD
68static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 62static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
69
70void __init r8a7779_register_twd(void) 63void __init r8a7779_register_twd(void)
71{ 64{
72 twd_local_timer_register(&twd_local_timer); 65 twd_local_timer_register(&twd_local_timer);
73} 66}
74#endif 67#endif
75 68
76static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
77{
78 void __iomem *scu_base = scu_base_addr();
79
80 spin_lock(&scu_lock);
81 tmp = __raw_readl(scu_base + 8);
82 tmp &= ~clr;
83 tmp |= set;
84 spin_unlock(&scu_lock);
85
86 /* disable cache coherency after releasing the lock */
87 __raw_writel(tmp, scu_base + 8);
88}
89
90static unsigned int __init r8a7779_get_core_count(void)
91{
92 void __iomem *scu_base = scu_base_addr();
93
94 return scu_get_core_count(scu_base);
95}
96
97static int r8a7779_platform_cpu_kill(unsigned int cpu) 69static int r8a7779_platform_cpu_kill(unsigned int cpu)
98{ 70{
99 struct r8a7779_pm_ch *ch = NULL; 71 struct r8a7779_pm_ch *ch = NULL;
@@ -101,9 +73,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
101 73
102 cpu = cpu_logical_map(cpu); 74 cpu = cpu_logical_map(cpu);
103 75
104 /* disable cache coherency */
105 modify_scu_cpu_psr(3 << (cpu * 8), 0);
106
107 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 76 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
108 ch = r8a7779_ch_cpu[cpu]; 77 ch = r8a7779_ch_cpu[cpu];
109 78
@@ -113,25 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
113 return ret ? ret : 1; 82 return ret ? ret : 1;
114} 83}
115 84
116static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
117{
118 int k;
119
120 /* this function is running on another CPU than the offline target,
121 * here we need wait for shutdown code in platform_cpu_die() to
122 * finish before asking SoC-specific code to power off the CPU core.
123 */
124 for (k = 0; k < 1000; k++) {
125 if (shmobile_cpu_is_dead(cpu))
126 return r8a7779_platform_cpu_kill(cpu);
127
128 mdelay(1);
129 }
130
131 return 0;
132}
133
134
135static void __cpuinit r8a7779_secondary_init(unsigned int cpu) 85static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
136{ 86{
137 gic_secondary_init(0); 87 gic_secondary_init(0);
@@ -144,9 +94,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
144 94
145 cpu = cpu_logical_map(cpu); 95 cpu = cpu_logical_map(cpu);
146 96
147 /* enable cache coherency */
148 modify_scu_cpu_psr(0, 3 << (cpu * 8));
149
150 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 97 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
151 ch = r8a7779_ch_cpu[cpu]; 98 ch = r8a7779_ch_cpu[cpu];
152 99
@@ -158,15 +105,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
158 105
159static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) 106static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
160{ 107{
161 int cpu = cpu_logical_map(0); 108 scu_enable(shmobile_scu_base);
162 109
163 scu_enable(scu_base_addr()); 110 /* Map the reset vector (in headsmp-scu.S) */
111 __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
164 112
165 /* Map the reset vector (in headsmp.S) */ 113 /* enable cache coherency on booting CPU */
166 __raw_writel(__pa(shmobile_secondary_vector), AVECR); 114 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
167
168 /* enable cache coherency on CPU0 */
169 modify_scu_cpu_psr(0, 3 << (cpu * 8));
170 115
171 r8a7779_pm_init(); 116 r8a7779_pm_init();
172 117
@@ -178,10 +123,60 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
178 123
179static void __init r8a7779_smp_init_cpus(void) 124static void __init r8a7779_smp_init_cpus(void)
180{ 125{
181 unsigned int ncores = r8a7779_get_core_count(); 126 /* setup r8a7779 specific SCU base */
127 shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
128
129 shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
130}
182 131
183 shmobile_smp_init_cpus(ncores); 132#ifdef CONFIG_HOTPLUG_CPU
133static int r8a7779_scu_psr_core_disabled(int cpu)
134{
135 unsigned long mask = 3 << (cpu * 8);
136
137 if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
138 return 1;
139
140 return 0;
141}
142
143static int r8a7779_cpu_kill(unsigned int cpu)
144{
145 int k;
146
147 /* this function is running on another CPU than the offline target,
148 * here we need wait for shutdown code in platform_cpu_die() to
149 * finish before asking SoC-specific code to power off the CPU core.
150 */
151 for (k = 0; k < 1000; k++) {
152 if (r8a7779_scu_psr_core_disabled(cpu))
153 return r8a7779_platform_cpu_kill(cpu);
154
155 mdelay(1);
156 }
157
158 return 0;
159}
160
161static void r8a7779_cpu_die(unsigned int cpu)
162{
163 dsb();
164 flush_cache_all();
165
166 /* disable cache coherency */
167 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
168
169 /* Endless loop until power off from r8a7779_cpu_kill() */
170 while (1)
171 cpu_do_idle();
172}
173
174static int r8a7779_cpu_disable(unsigned int cpu)
175{
176 /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
177 return cpu == 0 ? -EPERM : 0;
184} 178}
179#endif /* CONFIG_HOTPLUG_CPU */
185 180
186struct smp_operations r8a7779_smp_ops __initdata = { 181struct smp_operations r8a7779_smp_ops __initdata = {
187 .smp_init_cpus = r8a7779_smp_init_cpus, 182 .smp_init_cpus = r8a7779_smp_init_cpus,
@@ -190,7 +185,7 @@ struct smp_operations r8a7779_smp_ops __initdata = {
190 .smp_boot_secondary = r8a7779_boot_secondary, 185 .smp_boot_secondary = r8a7779_boot_secondary,
191#ifdef CONFIG_HOTPLUG_CPU 186#ifdef CONFIG_HOTPLUG_CPU
192 .cpu_kill = r8a7779_cpu_kill, 187 .cpu_kill = r8a7779_cpu_kill,
193 .cpu_die = shmobile_cpu_die, 188 .cpu_die = r8a7779_cpu_die,
194 .cpu_disable = shmobile_cpu_disable, 189 .cpu_disable = r8a7779_cpu_disable,
195#endif 190#endif
196}; 191};
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index acb46a94ccdf..5ae502b16437 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -39,26 +39,16 @@
39 39
40#define PSTR_SHUTDOWN_MODE 3 40#define PSTR_SHUTDOWN_MODE 3
41 41
42static void __iomem *scu_base_addr(void) 42#define SH73A0_SCU_BASE 0xf0000000
43{
44 return (void __iomem *)0xf0000000;
45}
46 43
47#ifdef CONFIG_HAVE_ARM_TWD 44#ifdef CONFIG_HAVE_ARM_TWD
48static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 45static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
49void __init sh73a0_register_twd(void) 46void __init sh73a0_register_twd(void)
50{ 47{
51 twd_local_timer_register(&twd_local_timer); 48 twd_local_timer_register(&twd_local_timer);
52} 49}
53#endif 50#endif
54 51
55static unsigned int __init sh73a0_get_core_count(void)
56{
57 void __iomem *scu_base = scu_base_addr();
58
59 return scu_get_core_count(scu_base);
60}
61
62static void __cpuinit sh73a0_secondary_init(unsigned int cpu) 52static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
63{ 53{
64 gic_secondary_init(0); 54 gic_secondary_init(0);
@@ -78,21 +68,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
78 68
79static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) 69static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
80{ 70{
81 scu_enable(scu_base_addr()); 71 scu_enable(shmobile_scu_base);
82 72
83 /* Map the reset vector (in headsmp-sh73a0.S) */ 73 /* Map the reset vector (in headsmp-scu.S) */
84 __raw_writel(0, APARMBAREA); /* 4k */ 74 __raw_writel(0, APARMBAREA); /* 4k */
85 __raw_writel(__pa(sh73a0_secondary_vector), SBAR); 75 __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
86 76
87 /* enable cache coherency on booting CPU */ 77 /* enable cache coherency on booting CPU */
88 scu_power_mode(scu_base_addr(), SCU_PM_NORMAL); 78 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
89} 79}
90 80
91static void __init sh73a0_smp_init_cpus(void) 81static void __init sh73a0_smp_init_cpus(void)
92{ 82{
93 unsigned int ncores = sh73a0_get_core_count(); 83 /* setup sh73a0 specific SCU base */
84 shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
94 85
95 shmobile_smp_init_cpus(ncores); 86 shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
96} 87}
97 88
98#ifdef CONFIG_HOTPLUG_CPU 89#ifdef CONFIG_HOTPLUG_CPU
@@ -128,11 +119,16 @@ static void sh73a0_cpu_die(unsigned int cpu)
128 flush_cache_all(); 119 flush_cache_all();
129 120
130 /* Set power off mode. This takes the CPU out of the MP cluster */ 121 /* Set power off mode. This takes the CPU out of the MP cluster */
131 scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); 122 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
132 123
133 /* Enter shutdown mode */ 124 /* Enter shutdown mode */
134 cpu_do_idle(); 125 cpu_do_idle();
135} 126}
127
128static int sh73a0_cpu_disable(unsigned int cpu)
129{
130 return 0; /* CPU0 and CPU1 supported */
131}
136#endif /* CONFIG_HOTPLUG_CPU */ 132#endif /* CONFIG_HOTPLUG_CPU */
137 133
138struct smp_operations sh73a0_smp_ops __initdata = { 134struct smp_operations sh73a0_smp_ops __initdata = {
@@ -143,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = {
143#ifdef CONFIG_HOTPLUG_CPU 139#ifdef CONFIG_HOTPLUG_CPU
144 .cpu_kill = sh73a0_cpu_kill, 140 .cpu_kill = sh73a0_cpu_kill,
145 .cpu_die = sh73a0_cpu_die, 141 .cpu_die = sh73a0_cpu_die,
146 .cpu_disable = shmobile_cpu_disable_any, 142 .cpu_disable = sh73a0_cpu_disable,
147#endif 143#endif
148}; 144};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 16:31:18 -0500