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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-13 13:39:38 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-13 13:39:38 -0500
commit86f6f9b64a730844f1438cbedfacd6fb0170a7f7 (patch)
treecd80f8610b444ae3bd2ebfc136c2c3299a52bd9b /arch/arm/mach-shmobile
parentd33a6291c1c577ff2272edab7416a0f7308e1cef (diff)
parent8b6f08eaef16dfcfebc32fa9a017bf70336ad9ec (diff)
Merge branch 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (31 commits) sh: Add support for AP-SH4AD-0A board. sh: Add support for AP-SH4A-3A board. sh: Add a new mach type for alpha project boards. serial: sh-sci: build fixes. sh: sh7372 SH4AL-DSP probe support sh: sh7366 Enable SDIO IRQs sh: sh7343 Enable SDIO IRQs sh: mach-ecovec24: enable runtime PM for SDHI sh: sh7723 / ap325rxa enable SDIO IRQs sh: sh7722 Enable SDIO IRQs sh: sh7724 Enable SDIO IRQs sh: Fix up legacy PTEA space attribute mapping. sh: Stub out legacy PCC pgprot encoding for X2 TLBs. sh: constify prefetch pointers. sh: Add a machvec callback for early memblock reservations. sh: update sh7757lcr_defconfig sh: add PVR probing for SH7757 3rd cut sh: Use device_initcall() instead of __initcall() sh: intc - convert board specific landisk code sh: Move init_landisk_IRQ to header file ...
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c14
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c14
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c16
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c18
4 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 003008c18360..ce28141662da 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -35,6 +35,8 @@
35static struct plat_sci_port scif0_platform_data = { 35static struct plat_sci_port scif0_platform_data = {
36 .mapbase = 0xe6c40000, 36 .mapbase = 0xe6c40000,
37 .flags = UPF_BOOT_AUTOCONF, 37 .flags = UPF_BOOT_AUTOCONF,
38 .scscr = SCSCR_RE | SCSCR_TE,
39 .scbrr_algo_id = SCBRR_ALGO_4,
38 .type = PORT_SCIF, 40 .type = PORT_SCIF,
39 .irqs = { evt2irq(0xc00), evt2irq(0xc00), 41 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
40 evt2irq(0xc00), evt2irq(0xc00) }, 42 evt2irq(0xc00), evt2irq(0xc00) },
@@ -52,6 +54,8 @@ static struct platform_device scif0_device = {
52static struct plat_sci_port scif1_platform_data = { 54static struct plat_sci_port scif1_platform_data = {
53 .mapbase = 0xe6c50000, 55 .mapbase = 0xe6c50000,
54 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIF, 59 .type = PORT_SCIF,
56 .irqs = { evt2irq(0xc20), evt2irq(0xc20), 60 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
57 evt2irq(0xc20), evt2irq(0xc20) }, 61 evt2irq(0xc20), evt2irq(0xc20) },
@@ -69,6 +73,8 @@ static struct platform_device scif1_device = {
69static struct plat_sci_port scif2_platform_data = { 73static struct plat_sci_port scif2_platform_data = {
70 .mapbase = 0xe6c60000, 74 .mapbase = 0xe6c60000,
71 .flags = UPF_BOOT_AUTOCONF, 75 .flags = UPF_BOOT_AUTOCONF,
76 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4,
72 .type = PORT_SCIF, 78 .type = PORT_SCIF,
73 .irqs = { evt2irq(0xc40), evt2irq(0xc40), 79 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
74 evt2irq(0xc40), evt2irq(0xc40) }, 80 evt2irq(0xc40), evt2irq(0xc40) },
@@ -86,6 +92,8 @@ static struct platform_device scif2_device = {
86static struct plat_sci_port scif3_platform_data = { 92static struct plat_sci_port scif3_platform_data = {
87 .mapbase = 0xe6c70000, 93 .mapbase = 0xe6c70000,
88 .flags = UPF_BOOT_AUTOCONF, 94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
89 .type = PORT_SCIF, 97 .type = PORT_SCIF,
90 .irqs = { evt2irq(0xc60), evt2irq(0xc60), 98 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
91 evt2irq(0xc60), evt2irq(0xc60) }, 99 evt2irq(0xc60), evt2irq(0xc60) },
@@ -103,6 +111,8 @@ static struct platform_device scif3_device = {
103static struct plat_sci_port scif4_platform_data = { 111static struct plat_sci_port scif4_platform_data = {
104 .mapbase = 0xe6c80000, 112 .mapbase = 0xe6c80000,
105 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
114 .scscr = SCSCR_RE | SCSCR_TE,
115 .scbrr_algo_id = SCBRR_ALGO_4,
106 .type = PORT_SCIF, 116 .type = PORT_SCIF,
107 .irqs = { evt2irq(0xd20), evt2irq(0xd20), 117 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
108 evt2irq(0xd20), evt2irq(0xd20) }, 118 evt2irq(0xd20), evt2irq(0xd20) },
@@ -120,6 +130,8 @@ static struct platform_device scif4_device = {
120static struct plat_sci_port scif5_platform_data = { 130static struct plat_sci_port scif5_platform_data = {
121 .mapbase = 0xe6cb0000, 131 .mapbase = 0xe6cb0000,
122 .flags = UPF_BOOT_AUTOCONF, 132 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_RE | SCSCR_TE,
134 .scbrr_algo_id = SCBRR_ALGO_4,
123 .type = PORT_SCIF, 135 .type = PORT_SCIF,
124 .irqs = { evt2irq(0xd40), evt2irq(0xd40), 136 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
125 evt2irq(0xd40), evt2irq(0xd40) }, 137 evt2irq(0xd40), evt2irq(0xd40) },
@@ -137,6 +149,8 @@ static struct platform_device scif5_device = {
137static struct plat_sci_port scif6_platform_data = { 149static struct plat_sci_port scif6_platform_data = {
138 .mapbase = 0xe6c30000, 150 .mapbase = 0xe6c30000,
139 .flags = UPF_BOOT_AUTOCONF, 151 .flags = UPF_BOOT_AUTOCONF,
152 .scscr = SCSCR_RE | SCSCR_TE,
153 .scbrr_algo_id = SCBRR_ALGO_4,
140 .type = PORT_SCIF, 154 .type = PORT_SCIF,
141 .irqs = { evt2irq(0xd60), evt2irq(0xd60), 155 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
142 evt2irq(0xd60), evt2irq(0xd60) }, 156 evt2irq(0xd60), evt2irq(0xd60) },
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 2e3e11ee7c43..ff0494f3d00c 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -38,6 +38,8 @@
38static struct plat_sci_port scif0_platform_data = { 38static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xe6c40000, 39 .mapbase = 0xe6c40000,
40 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE,
42 .scbrr_algo_id = SCBRR_ALGO_4,
41 .type = PORT_SCIFA, 43 .type = PORT_SCIFA,
42 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), 44 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
43 evt2irq(0x0c00), evt2irq(0x0c00) }, 45 evt2irq(0x0c00), evt2irq(0x0c00) },
@@ -55,6 +57,8 @@ static struct platform_device scif0_device = {
55static struct plat_sci_port scif1_platform_data = { 57static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000, 58 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF, 59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE,
61 .scbrr_algo_id = SCBRR_ALGO_4,
58 .type = PORT_SCIFA, 62 .type = PORT_SCIFA,
59 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), 63 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
60 evt2irq(0x0c20), evt2irq(0x0c20) }, 64 evt2irq(0x0c20), evt2irq(0x0c20) },
@@ -72,6 +76,8 @@ static struct platform_device scif1_device = {
72static struct plat_sci_port scif2_platform_data = { 76static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xe6c60000, 77 .mapbase = 0xe6c60000,
74 .flags = UPF_BOOT_AUTOCONF, 78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
80 .scbrr_algo_id = SCBRR_ALGO_4,
75 .type = PORT_SCIFA, 81 .type = PORT_SCIFA,
76 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), 82 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
77 evt2irq(0x0c40), evt2irq(0x0c40) }, 83 evt2irq(0x0c40), evt2irq(0x0c40) },
@@ -89,6 +95,8 @@ static struct platform_device scif2_device = {
89static struct plat_sci_port scif3_platform_data = { 95static struct plat_sci_port scif3_platform_data = {
90 .mapbase = 0xe6c70000, 96 .mapbase = 0xe6c70000,
91 .flags = UPF_BOOT_AUTOCONF, 97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
92 .type = PORT_SCIFA, 100 .type = PORT_SCIFA,
93 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), 101 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
94 evt2irq(0x0c60), evt2irq(0x0c60) }, 102 evt2irq(0x0c60), evt2irq(0x0c60) },
@@ -106,6 +114,8 @@ static struct platform_device scif3_device = {
106static struct plat_sci_port scif4_platform_data = { 114static struct plat_sci_port scif4_platform_data = {
107 .mapbase = 0xe6c80000, 115 .mapbase = 0xe6c80000,
108 .flags = UPF_BOOT_AUTOCONF, 116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
109 .type = PORT_SCIFA, 119 .type = PORT_SCIFA,
110 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), 120 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
111 evt2irq(0x0d20), evt2irq(0x0d20) }, 121 evt2irq(0x0d20), evt2irq(0x0d20) },
@@ -123,6 +133,8 @@ static struct platform_device scif4_device = {
123static struct plat_sci_port scif5_platform_data = { 133static struct plat_sci_port scif5_platform_data = {
124 .mapbase = 0xe6cb0000, 134 .mapbase = 0xe6cb0000,
125 .flags = UPF_BOOT_AUTOCONF, 135 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_RE | SCSCR_TE,
137 .scbrr_algo_id = SCBRR_ALGO_4,
126 .type = PORT_SCIFA, 138 .type = PORT_SCIFA,
127 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), 139 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
128 evt2irq(0x0d40), evt2irq(0x0d40) }, 140 evt2irq(0x0d40), evt2irq(0x0d40) },
@@ -140,6 +152,8 @@ static struct platform_device scif5_device = {
140static struct plat_sci_port scif6_platform_data = { 152static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6c30000, 153 .mapbase = 0xe6c30000,
142 .flags = UPF_BOOT_AUTOCONF, 154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
143 .type = PORT_SCIFB, 157 .type = PORT_SCIFB,
144 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), 158 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
145 evt2irq(0x0d60), evt2irq(0x0d60) }, 159 evt2irq(0x0d60), evt2irq(0x0d60) },
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 575dbd6c2f1d..8099b0b8a934 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -36,6 +36,8 @@
36static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
39 .type = PORT_SCIF, 41 .type = PORT_SCIF,
40 .irqs = { evt2irq(0xc00), evt2irq(0xc00), 42 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
41 evt2irq(0xc00), evt2irq(0xc00) }, 43 evt2irq(0xc00), evt2irq(0xc00) },
@@ -53,6 +55,8 @@ static struct platform_device scif0_device = {
53static struct plat_sci_port scif1_platform_data = { 55static struct plat_sci_port scif1_platform_data = {
54 .mapbase = 0xe6c50000, 56 .mapbase = 0xe6c50000,
55 .flags = UPF_BOOT_AUTOCONF, 57 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE,
59 .scbrr_algo_id = SCBRR_ALGO_4,
56 .type = PORT_SCIF, 60 .type = PORT_SCIF,
57 .irqs = { evt2irq(0xc20), evt2irq(0xc20), 61 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
58 evt2irq(0xc20), evt2irq(0xc20) }, 62 evt2irq(0xc20), evt2irq(0xc20) },
@@ -70,6 +74,8 @@ static struct platform_device scif1_device = {
70static struct plat_sci_port scif2_platform_data = { 74static struct plat_sci_port scif2_platform_data = {
71 .mapbase = 0xe6c60000, 75 .mapbase = 0xe6c60000,
72 .flags = UPF_BOOT_AUTOCONF, 76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIF, 79 .type = PORT_SCIF,
74 .irqs = { evt2irq(0xc40), evt2irq(0xc40), 80 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
75 evt2irq(0xc40), evt2irq(0xc40) }, 81 evt2irq(0xc40), evt2irq(0xc40) },
@@ -87,6 +93,8 @@ static struct platform_device scif2_device = {
87static struct plat_sci_port scif3_platform_data = { 93static struct plat_sci_port scif3_platform_data = {
88 .mapbase = 0xe6c70000, 94 .mapbase = 0xe6c70000,
89 .flags = UPF_BOOT_AUTOCONF, 95 .flags = UPF_BOOT_AUTOCONF,
96 .scscr = SCSCR_RE | SCSCR_TE,
97 .scbrr_algo_id = SCBRR_ALGO_4,
90 .type = PORT_SCIF, 98 .type = PORT_SCIF,
91 .irqs = { evt2irq(0xc60), evt2irq(0xc60), 99 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
92 evt2irq(0xc60), evt2irq(0xc60) }, 100 evt2irq(0xc60), evt2irq(0xc60) },
@@ -104,6 +112,8 @@ static struct platform_device scif3_device = {
104static struct plat_sci_port scif4_platform_data = { 112static struct plat_sci_port scif4_platform_data = {
105 .mapbase = 0xe6c80000, 113 .mapbase = 0xe6c80000,
106 .flags = UPF_BOOT_AUTOCONF, 114 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE,
116 .scbrr_algo_id = SCBRR_ALGO_4,
107 .type = PORT_SCIF, 117 .type = PORT_SCIF,
108 .irqs = { evt2irq(0xd20), evt2irq(0xd20), 118 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
109 evt2irq(0xd20), evt2irq(0xd20) }, 119 evt2irq(0xd20), evt2irq(0xd20) },
@@ -121,6 +131,8 @@ static struct platform_device scif4_device = {
121static struct plat_sci_port scif5_platform_data = { 131static struct plat_sci_port scif5_platform_data = {
122 .mapbase = 0xe6cb0000, 132 .mapbase = 0xe6cb0000,
123 .flags = UPF_BOOT_AUTOCONF, 133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4,
124 .type = PORT_SCIF, 136 .type = PORT_SCIF,
125 .irqs = { evt2irq(0xd40), evt2irq(0xd40), 137 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
126 evt2irq(0xd40), evt2irq(0xd40) }, 138 evt2irq(0xd40), evt2irq(0xd40) },
@@ -138,6 +150,8 @@ static struct platform_device scif5_device = {
138static struct plat_sci_port scif6_platform_data = { 150static struct plat_sci_port scif6_platform_data = {
139 .mapbase = 0xe6cc0000, 151 .mapbase = 0xe6cc0000,
140 .flags = UPF_BOOT_AUTOCONF, 152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
141 .type = PORT_SCIF, 155 .type = PORT_SCIF,
142 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), 156 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
143 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, 157 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
@@ -155,6 +169,8 @@ static struct platform_device scif6_device = {
155static struct plat_sci_port scif7_platform_data = { 169static struct plat_sci_port scif7_platform_data = {
156 .mapbase = 0xe6c30000, 170 .mapbase = 0xe6c30000,
157 .flags = UPF_BOOT_AUTOCONF, 171 .flags = UPF_BOOT_AUTOCONF,
172 .scscr = SCSCR_RE | SCSCR_TE,
173 .scbrr_algo_id = SCBRR_ALGO_4,
158 .type = PORT_SCIF, 174 .type = PORT_SCIF,
159 .irqs = { evt2irq(0xd60), evt2irq(0xd60), 175 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
160 evt2irq(0xd60), evt2irq(0xd60) }, 176 evt2irq(0xd60), evt2irq(0xd60) },
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index f1eff8b37bd6..685c40a2f5e6 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -36,6 +36,8 @@
36static struct plat_sci_port scif0_platform_data = { 36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000, 37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF, 38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
39 .type = PORT_SCIFA, 41 .type = PORT_SCIFA,
40 .irqs = { gic_spi(72), gic_spi(72), 42 .irqs = { gic_spi(72), gic_spi(72),
41 gic_spi(72), gic_spi(72) }, 43 gic_spi(72), gic_spi(72) },
@@ -52,6 +54,8 @@ static struct platform_device scif0_device = {
52static struct plat_sci_port scif1_platform_data = { 54static struct plat_sci_port scif1_platform_data = {
53 .mapbase = 0xe6c50000, 55 .mapbase = 0xe6c50000,
54 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIFA, 59 .type = PORT_SCIFA,
56 .irqs = { gic_spi(73), gic_spi(73), 60 .irqs = { gic_spi(73), gic_spi(73),
57 gic_spi(73), gic_spi(73) }, 61 gic_spi(73), gic_spi(73) },
@@ -68,6 +72,8 @@ static struct platform_device scif1_device = {
68static struct plat_sci_port scif2_platform_data = { 72static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000, 73 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF, 74 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE,
76 .scbrr_algo_id = SCBRR_ALGO_4,
71 .type = PORT_SCIFA, 77 .type = PORT_SCIFA,
72 .irqs = { gic_spi(74), gic_spi(74), 78 .irqs = { gic_spi(74), gic_spi(74),
73 gic_spi(74), gic_spi(74) }, 79 gic_spi(74), gic_spi(74) },
@@ -84,6 +90,8 @@ static struct platform_device scif2_device = {
84static struct plat_sci_port scif3_platform_data = { 90static struct plat_sci_port scif3_platform_data = {
85 .mapbase = 0xe6c70000, 91 .mapbase = 0xe6c70000,
86 .flags = UPF_BOOT_AUTOCONF, 92 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE,
94 .scbrr_algo_id = SCBRR_ALGO_4,
87 .type = PORT_SCIFA, 95 .type = PORT_SCIFA,
88 .irqs = { gic_spi(75), gic_spi(75), 96 .irqs = { gic_spi(75), gic_spi(75),
89 gic_spi(75), gic_spi(75) }, 97 gic_spi(75), gic_spi(75) },
@@ -100,6 +108,8 @@ static struct platform_device scif3_device = {
100static struct plat_sci_port scif4_platform_data = { 108static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xe6c80000, 109 .mapbase = 0xe6c80000,
102 .flags = UPF_BOOT_AUTOCONF, 110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE,
112 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 113 .type = PORT_SCIFA,
104 .irqs = { gic_spi(78), gic_spi(78), 114 .irqs = { gic_spi(78), gic_spi(78),
105 gic_spi(78), gic_spi(78) }, 115 gic_spi(78), gic_spi(78) },
@@ -116,6 +126,8 @@ static struct platform_device scif4_device = {
116static struct plat_sci_port scif5_platform_data = { 126static struct plat_sci_port scif5_platform_data = {
117 .mapbase = 0xe6cb0000, 127 .mapbase = 0xe6cb0000,
118 .flags = UPF_BOOT_AUTOCONF, 128 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE,
130 .scbrr_algo_id = SCBRR_ALGO_4,
119 .type = PORT_SCIFA, 131 .type = PORT_SCIFA,
120 .irqs = { gic_spi(79), gic_spi(79), 132 .irqs = { gic_spi(79), gic_spi(79),
121 gic_spi(79), gic_spi(79) }, 133 gic_spi(79), gic_spi(79) },
@@ -132,6 +144,8 @@ static struct platform_device scif5_device = {
132static struct plat_sci_port scif6_platform_data = { 144static struct plat_sci_port scif6_platform_data = {
133 .mapbase = 0xe6cc0000, 145 .mapbase = 0xe6cc0000,
134 .flags = UPF_BOOT_AUTOCONF, 146 .flags = UPF_BOOT_AUTOCONF,
147 .scscr = SCSCR_RE | SCSCR_TE,
148 .scbrr_algo_id = SCBRR_ALGO_4,
135 .type = PORT_SCIFA, 149 .type = PORT_SCIFA,
136 .irqs = { gic_spi(156), gic_spi(156), 150 .irqs = { gic_spi(156), gic_spi(156),
137 gic_spi(156), gic_spi(156) }, 151 gic_spi(156), gic_spi(156) },
@@ -148,6 +162,8 @@ static struct platform_device scif6_device = {
148static struct plat_sci_port scif7_platform_data = { 162static struct plat_sci_port scif7_platform_data = {
149 .mapbase = 0xe6cd0000, 163 .mapbase = 0xe6cd0000,
150 .flags = UPF_BOOT_AUTOCONF, 164 .flags = UPF_BOOT_AUTOCONF,
165 .scscr = SCSCR_RE | SCSCR_TE,
166 .scbrr_algo_id = SCBRR_ALGO_4,
151 .type = PORT_SCIFA, 167 .type = PORT_SCIFA,
152 .irqs = { gic_spi(143), gic_spi(143), 168 .irqs = { gic_spi(143), gic_spi(143),
153 gic_spi(143), gic_spi(143) }, 169 gic_spi(143), gic_spi(143) },
@@ -164,6 +180,8 @@ static struct platform_device scif7_device = {
164static struct plat_sci_port scif8_platform_data = { 180static struct plat_sci_port scif8_platform_data = {
165 .mapbase = 0xe6c30000, 181 .mapbase = 0xe6c30000,
166 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE,
184 .scbrr_algo_id = SCBRR_ALGO_4,
167 .type = PORT_SCIFB, 185 .type = PORT_SCIFB,
168 .irqs = { gic_spi(80), gic_spi(80), 186 .irqs = { gic_spi(80), gic_spi(80),
169 gic_spi(80), gic_spi(80) }, 187 gic_spi(80), gic_spi(80) },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 08:45:34 -0500