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authorMagnus Damm <damm@opensource.se>2011-10-19 17:52:50 -0400
committerRafael J. Wysocki <rjw@sisk.pl>2011-10-21 18:20:12 -0400
commit382414b93ac1e8ee7693be710e60c83eacc97c6f (patch)
tree2b57a165a295af5468c611c553a9401a81f4b300 /arch/arm/mach-shmobile/setup-sh7372.c
parentd93f5cdea968284f05aa9905ee9752874885a6fa (diff)
ARM: mach-shmobile: sh7372 A4R support (v4)
This change adds support for the sh7372 A4R power domain. The sh7372 A4R hardware power domain contains the SH CPU Core and a set of I/O devices including multimedia accelerators and I2C controllers. One special case about A4R is the INTCS interrupt controller that needs to be saved and restored to keep working as expected. Also the LCDC hardware blocks are in a different hardware power domain but have their IRQs routed only through INTCS. So as long as LCDCs are active we cannot power down INTCS because that would risk losing interrupts. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch/arm/mach-shmobile/setup-sh7372.c')
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5f1afcc4de6e..2380389e6ac5 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -991,12 +991,14 @@ void __init sh7372_add_standard_devices(void)
991 sh7372_init_pm_domain(&sh7372_a4lc); 991 sh7372_init_pm_domain(&sh7372_a4lc);
992 sh7372_init_pm_domain(&sh7372_a4mp); 992 sh7372_init_pm_domain(&sh7372_a4mp);
993 sh7372_init_pm_domain(&sh7372_d4); 993 sh7372_init_pm_domain(&sh7372_d4);
994 sh7372_init_pm_domain(&sh7372_a4r);
994 sh7372_init_pm_domain(&sh7372_a3rv); 995 sh7372_init_pm_domain(&sh7372_a3rv);
995 sh7372_init_pm_domain(&sh7372_a3ri); 996 sh7372_init_pm_domain(&sh7372_a3ri);
996 sh7372_init_pm_domain(&sh7372_a3sg); 997 sh7372_init_pm_domain(&sh7372_a3sg);
997 sh7372_init_pm_domain(&sh7372_a3sp); 998 sh7372_init_pm_domain(&sh7372_a3sp);
998 999
999 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); 1000 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1001 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1000 1002
1001 platform_add_devices(sh7372_early_devices, 1003 platform_add_devices(sh7372_early_devices,
1002 ARRAY_SIZE(sh7372_early_devices)); 1004 ARRAY_SIZE(sh7372_early_devices));
@@ -1020,6 +1022,12 @@ void __init sh7372_add_standard_devices(void)
1020 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device); 1022 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1021 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device); 1023 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1022 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device); 1024 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1025 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1026 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1027 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1028 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1029 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1030 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1023} 1031}
1024 1032
1025void __init sh7372_add_early_devices(void) 1033void __init sh7372_add_early_devices(void)