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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-12-06 04:59:27 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-12-24 07:09:09 -0500
commitecbcd715f098bf4b870ae5bd0f9b572987b3b219 (patch)
treef73fc28c8fab2342165fafda8e4b815d31bafef6 /arch/arm/mach-shmobile/setup-r8a7778.c
parenta958a31eb021a2c8ce24c718fcbf00d915f38e78 (diff)
ARM: shmobile: r8a7778: Don't define SCIF platform data in an array
The SCIF driver is transitioning to platform resources. Board code will thus need to define an array of resources for each SCIF device. This is incompatible with the macro-based SCIF platform data definition as an array. Rework the macro to define platform data as individual structures. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a7778.c')
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c36
1 files changed, 19 insertions, 17 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 7ea6308e5da8..210c66315dd9 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -44,8 +44,8 @@
44#include <asm/hardware/cache-l2x0.h> 44#include <asm/hardware/cache-l2x0.h>
45 45
46/* SCIF */ 46/* SCIF */
47#define SCIF_INFO(baseaddr, irq) \ 47#define R8A7778_SCIF(index, baseaddr, irq) \
48{ \ 48static struct plat_sci_port scif##index##_platform_data = { \
49 .mapbase = baseaddr, \ 49 .mapbase = baseaddr, \
50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
@@ -54,14 +54,17 @@
54 .irqs = SCIx_IRQ_MUXED(irq), \ 54 .irqs = SCIx_IRQ_MUXED(irq), \
55} 55}
56 56
57static struct plat_sci_port scif_platform_data[] __initdata = { 57R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
58 SCIF_INFO(0xffe40000, gic_iid(0x66)), 58R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
59 SCIF_INFO(0xffe41000, gic_iid(0x67)), 59R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
60 SCIF_INFO(0xffe42000, gic_iid(0x68)), 60R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
61 SCIF_INFO(0xffe43000, gic_iid(0x69)), 61R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
62 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 62R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
63 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 63
64}; 64#define r8a7778_register_scif(index) \
65 platform_device_register_data(&platform_bus, "sh-sci", index, \
66 &scif##index##_platform_data, \
67 sizeof(scif##index##_platform_data))
65 68
66/* TMU */ 69/* TMU */
67static struct resource sh_tmu0_resources[] __initdata = { 70static struct resource sh_tmu0_resources[] __initdata = {
@@ -287,8 +290,6 @@ static void __init r8a7778_register_hspi(int id)
287 290
288void __init r8a7778_add_dt_devices(void) 291void __init r8a7778_add_dt_devices(void)
289{ 292{
290 int i;
291
292#ifdef CONFIG_CACHE_L2X0 293#ifdef CONFIG_CACHE_L2X0
293 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 294 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
294 if (base) { 295 if (base) {
@@ -300,11 +301,12 @@ void __init r8a7778_add_dt_devices(void)
300 } 301 }
301#endif 302#endif
302 303
303 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 304 r8a7778_register_scif(0);
304 platform_device_register_data(&platform_bus, "sh-sci", i, 305 r8a7778_register_scif(1);
305 &scif_platform_data[i], 306 r8a7778_register_scif(2);
306 sizeof(struct plat_sci_port)); 307 r8a7778_register_scif(3);
307 308 r8a7778_register_scif(4);
309 r8a7778_register_scif(5);
308 r8a7778_register_tmu(0); 310 r8a7778_register_tmu(0);
309 r8a7778_register_tmu(1); 311 r8a7778_register_tmu(1);
310} 312}