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authorSimon Horman <horms+renesas@verge.net.au>2012-11-21 07:12:43 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-01-24 22:43:48 -0500
commita3f22db5102238197d5f6bbcad2f720ec7f09e10 (patch)
treefbe330c446e6d05b7f681a0f3d87dbeba09cc7ac /arch/arm/mach-shmobile/intc-sh73a0.c
parent20aa11358d52e1a3fc037d601ffe704e6f55c5fb (diff)
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT
This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/intc-sh73a0.c')
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 45973b59dd58..91faba666d46 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -23,6 +23,7 @@
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/sh_intc.h> 25#include <linux/sh_intc.h>
26#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h> 27#include <linux/irqchip/arm-gic.h>
27#include <mach/intc.h> 28#include <mach/intc.h>
28#include <mach/irqs.h> 29#include <mach/irqs.h>
@@ -459,3 +460,11 @@ void __init sh73a0_init_irq(void)
459 sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; 460 sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
460 setup_irq(gic_spi(34), &sh73a0_pint1_cascade); 461 setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
461} 462}
463
464#ifdef CONFIG_OF
465void __init sh73a0_init_irq_dt(void)
466{
467 irqchip_init();
468 gic_arch_extn.irq_set_wake = sh73a0_set_wake;
469}
470#endif