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authorMagnus Damm <damm@opensource.se>2012-03-28 06:22:46 -0400
committerRafael J. Wysocki <rjw@sisk.pl>2012-04-11 06:11:48 -0400
commitd7e7e4ffc64f700e876a9f3b2727febaa2041221 (patch)
tree087be2bd61890b659eaec51f0437d379940ef3e4 /arch/arm/mach-shmobile/include/mach
parent0f2c9f20e4e339de30cfd5613dfa9505e7b9c58b (diff)
ARM: mach-shmobile: Introduce INTC_IRQ_PINS_16H
Add INTC_IRQ_PINS_16H to allow broken out support of the the high 16 external interrupt pins. On SoCs with 32 external interrupt pins the interrupt vectors for the low 16 and the high 16 interrupt pins are sparesly populated. The low 16 are at 0x0200 and high 16 are at 0x3200 which with current macros results in a separation of 384 linux interrupts. This sparse population makes it unsuitable with a single IRQ domain to cover the full IRQ range, so this macro breaks out the 32 pins into two separate 16 bit controllers to allow two independent INTC instances with two separate IRQ domains. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch/arm/mach-shmobile/include/mach')
-rw-r--r--arch/arm/mach-shmobile/include/mach/intc.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h
index 8b22258c8caa..a5603c76cfe0 100644
--- a/arch/arm/mach-shmobile/include/mach/intc.h
+++ b/arch/arm/mach-shmobile/include/mach/intc.h
@@ -142,6 +142,50 @@ static struct intc_desc p ## _desc __initdata = { \
142 p ## _sense_registers, p ## _ack_registers) \ 142 p ## _sense_registers, p ## _ack_registers) \
143} 143}
144 144
145#define INTC_IRQ_PINS_16H(p, base, vect, str) \
146 \
147static struct resource p ## _resources[] __initdata = { \
148 [0] = { \
149 .start = base, \
150 .end = base + 0x64, \
151 .flags = IORESOURCE_MEM, \
152 }, \
153}; \
154 \
155enum { \
156 p ## _UNUSED = 0, \
157 INTC_IRQ_PINS_ENUM_16H(p), \
158}; \
159 \
160static struct intc_vect p ## _vectors[] __initdata = { \
161 INTC_IRQ_PINS_VECT_16H(p, vect), \
162}; \
163 \
164static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
165 INTC_IRQ_PINS_MASK_16H(p, base), \
166}; \
167 \
168static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
169 INTC_IRQ_PINS_PRIO_16H(p, base), \
170}; \
171 \
172static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
173 INTC_IRQ_PINS_SENSE_16H(p, base), \
174}; \
175 \
176static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
177 INTC_IRQ_PINS_ACK_16H(p, base), \
178}; \
179 \
180static struct intc_desc p ## _desc __initdata = { \
181 .name = str, \
182 .resource = p ## _resources, \
183 .num_resources = ARRAY_SIZE(p ## _resources), \
184 .hw = INTC_HW_DESC(p ## _vectors, NULL, \
185 p ## _mask_registers, p ## _prio_registers, \
186 p ## _sense_registers, p ## _ack_registers) \
187}
188
145#define INTC_IRQ_PINS_32(p, base, vect, str) \ 189#define INTC_IRQ_PINS_32(p, base, vect, str) \
146 \ 190 \
147static struct resource p ## _resources[] __initdata = { \ 191static struct resource p ## _resources[] __initdata = { \