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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-03-27 03:55:24 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-04-01 22:02:15 -0400
commitb3186c68805911599cbacceae23f60debb5e2210 (patch)
tree5671f3780754dc84006d7f6e7b6f9d7bc12a91d7 /arch/arm/mach-shmobile/clock-sh7372.c
parent1f7ccd88717d993c5189280034f1d3b6b5af9693 (diff)
ARM: shmobile: sh7372: remove DIV4_ZT* clocks
DIV4_ZT* clocks are for debugging and trace bus clock. It is not necessary to control it from Linux/Software. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/clock-sh7372.c')
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 45d21fe317f4..6c23e3f22d62 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -342,7 +342,7 @@ static struct clk_div4_table div4_table = {
342}; 342};
343 343
344enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, 344enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
345 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, 345 DIV4_ZX, DIV4_HP,
346 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, 346 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
347 DIV4_DDRP, DIV4_NR }; 347 DIV4_DDRP, DIV4_NR };
348 348
@@ -355,8 +355,6 @@ static struct clk div4_clks[DIV4_NR] = {
355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), 356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), 357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
358 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
359 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
360 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), 358 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
361 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), 359 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
362 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), 360 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
@@ -516,8 +514,6 @@ static struct clk_lookup lookups[] = {
516 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), 514 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
517 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), 515 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
518 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), 516 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
519 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
520 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
521 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), 517 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
522 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), 518 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
523 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), 519 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),