ARM: shmobile: Initial r8a7791 SoC support

Add initial support for the r8a7791 SoC including:
 - Single Cortex-A15 CPU Core
 - GIC

No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
[damm@opensource.se: Forward ported to upstream, dropped not-yet-ready code]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

1 files changed, 198 insertions, 0 deletions

diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
new file mode 100644
index 000000000000..9929feb1b810
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -0,0 +1,198 @@
+/*
+ * r8a7791 clock framework support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/clock.h>
+#include <mach/common.h>
+
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7791_CLOCK_ROOT() below
+ */
+
+#define MD(nr)  (1 << nr)
+
+#define CPG_BASE 0xe6150000
+#define CPG_LEN 0x1000
+
+#define SMSTPCR1        0xE6150134
+#define SMSTPCR2        0xe6150138
+#define SMSTPCR3        0xE615013C
+#define SMSTPCR5        0xE6150144
+#define SMSTPCR7        0xe615014c
+#define SMSTPCR8        0xE6150990
+#define SMSTPCR9        0xE6150994
+#define SMSTPCR10       0xE6150998
+
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
+
+static struct clk_mapping cpg_mapping = {
+        .phys   = CPG_BASE,
+        .len    = CPG_LEN,
+};
+
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7791_clock_init() */
+        .mapping        = &cpg_mapping,
+};
+
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7791_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+
+static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &hp_clk,
+        &p_clk,
+        &mp_clk,
+        &cp_clk,
+};
+
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+/*      MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,*/
+        MSTP_NR
+};
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
+        [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+};
+
+static struct clk_lookup lookups[] = {
+
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+        CLKDEV_CON_ID("peripheral_clk", &hp_clk),
+};
+
+#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
+void __init r8a7791_clock_init(void)
+{
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
+        int k, ret = 0;
+
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                shmobile_clk_init();
+        else
+                goto epanic;
+
+        return;
+
+epanic:
+        panic("failed to setup r8a7791 clocks\n");
+}