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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-11-19 04:05:23 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-12-10 02:52:21 -0500
commiteb7a91749fc1c4fa4f011dad40e3faf4c0ca27b0 (patch)
tree844b3aca0eeb2877a0e5318c4292491be117fb45 /arch/arm/mach-shmobile/clock-r8a7790.c
parentd59f4be9d0c2acf6bf16b4f8361593b4bbb4490b (diff)
ARM: shmobile: r8a7790: tidyup clock table order
SuperH lookups clock is using CLKDEV_CON/DEV/ICK_ID() macro for a long term. But in these days, the ICK clock is defined in random place. This patch arranges it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/clock-r8a7790.c')
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 3a267c29cd34..a51081307934 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -266,11 +266,6 @@ static struct clk_lookup lookups[] = {
266 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), 266 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
267 267
268 /* MSTP */ 268 /* MSTP */
269 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
270 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
271 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
272 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
273 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
274 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 269 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
275 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 270 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
276 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 271 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -303,7 +298,15 @@ static struct clk_lookup lookups[] = {
303 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 298 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
304 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), 299 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
305 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), 300 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
301
302 /* ICK */
306 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), 303 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
304 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
305 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
306 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
307 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
308 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
309
307}; 310};
308 311
309#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 312#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \