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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-10-01 16:03:21 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-01 16:03:21 -0400
commitee93916efe22f767628f9d25abb8ad8548797336 (patch)
treea9f96ac741d683738518a3deac59f73b331e81ca /arch/arm/mach-sa1100
parent07f841b7c587a3cbf481509be09ba5eda05f8d31 (diff)
[ARM] mm: switch SA1100 to use sparsemem
Tested on Assabet, and Assabet with Neponset's SDRAM at 3328M phys. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100')
-rw-r--r--arch/arm/mach-sa1100/include/mach/memory.h16
1 files changed, 7 insertions, 9 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index 29f639e2afc6..1c127b68581d 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -40,23 +40,21 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
40#define __bus_to_virt(x) __phys_to_virt(x) 40#define __bus_to_virt(x) __phys_to_virt(x)
41 41
42/* 42/*
43 * Because of the wide memory address space between physical RAM banks on the 43 * Because of the wide memory address space between physical RAM banks on the
44 * SA1100, it's much convenient to use Linux's NUMA support to implement our 44 * SA1100, it's much convenient to use Linux's SparseMEM support to implement
45 * memory map representation. Assuming all memory nodes have equal access 45 * our memory map representation. Assuming all memory nodes have equal access
46 * characteristics, we then have generic discontiguous memory support. 46 * characteristics, we then have generic discontiguous memory support.
47 * 47 *
48 * Of course, all this isn't mandatory for SA1100 implementations with only 48 * The sparsemem banks are matched with the physical memory bank addresses
49 * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. 49 * which are incidentally the same as virtual addresses.
50 *
51 * The nodes are matched with the physical memory bank addresses which are
52 * incidentally the same as virtual addresses.
53 * 50 *
54 * node 0: 0xc0000000 - 0xc7ffffff 51 * node 0: 0xc0000000 - 0xc7ffffff
55 * node 1: 0xc8000000 - 0xcfffffff 52 * node 1: 0xc8000000 - 0xcfffffff
56 * node 2: 0xd0000000 - 0xd7ffffff 53 * node 2: 0xd0000000 - 0xd7ffffff
57 * node 3: 0xd8000000 - 0xdfffffff 54 * node 3: 0xd8000000 - 0xdfffffff
58 */ 55 */
59#define NODE_MEM_SIZE_BITS 27 56#define MAX_PHYSMEM_BITS 32
57#define SECTION_SIZE_BITS 27
60 58
61/* 59/*
62 * Cache flushing area - SA1100 zero bank 60 * Cache flushing area - SA1100 zero bank