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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-01-14 11:57:02 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-03-25 18:55:12 -0400
commitc21320104ec5b8ffa0d62865d43ee56cbfccc2de (patch)
tree3f97e63255b40dddf150f56860ea46fe698febb8 /arch/arm/mach-sa1100
parent9903405be58c481e926d485b8fe50a1b9e4048be (diff)
ARM: sa11x0: remove unused DMA controller definitions
Remove the new unused DMA controller definitions from mach/SA-1100.h. These are now private to the SA-11x0 DMA engine driver and contained within the driver. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100')
-rw-r--r--arch/arm/mach-sa1100/generic.c2
-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h219
2 files changed, 3 insertions, 218 deletions
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 1752686e9abc..01a20ea35b53 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -291,7 +291,7 @@ static struct platform_device sa11x0rtc_device = {
291}; 291};
292 292
293static struct resource sa11x0dma_resources[] = { 293static struct resource sa11x0dma_resources[] = {
294 DEFINE_RES_MEM(__PREG(DDAR(0)), 6 * DMASp), 294 DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
295 DEFINE_RES_IRQ(IRQ_DMA0), 295 DEFINE_RES_IRQ(IRQ_DMA0),
296 DEFINE_RES_IRQ(IRQ_DMA1), 296 DEFINE_RES_IRQ(IRQ_DMA1),
297 DEFINE_RES_IRQ(IRQ_DMA2), 297 DEFINE_RES_IRQ(IRQ_DMA2),
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index bae8296f5dbf..335a1ff21faf 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1590,224 +1590,9 @@
1590 1590
1591/* 1591/*
1592 * Direct Memory Access (DMA) control registers 1592 * Direct Memory Access (DMA) control registers
1593 *
1594 * Registers
1595 * DDAR0 Direct Memory Access (DMA) Device Address Register
1596 * channel 0 (read/write).
1597 * DCSR0 Direct Memory Access (DMA) Control and Status
1598 * Register channel 0 (read/write).
1599 * DBSA0 Direct Memory Access (DMA) Buffer Start address
1600 * register A channel 0 (read/write).
1601 * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
1602 * register A channel 0 (read/write).
1603 * DBSB0 Direct Memory Access (DMA) Buffer Start address
1604 * register B channel 0 (read/write).
1605 * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
1606 * register B channel 0 (read/write).
1607 *
1608 * DDAR1 Direct Memory Access (DMA) Device Address Register
1609 * channel 1 (read/write).
1610 * DCSR1 Direct Memory Access (DMA) Control and Status
1611 * Register channel 1 (read/write).
1612 * DBSA1 Direct Memory Access (DMA) Buffer Start address
1613 * register A channel 1 (read/write).
1614 * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
1615 * register A channel 1 (read/write).
1616 * DBSB1 Direct Memory Access (DMA) Buffer Start address
1617 * register B channel 1 (read/write).
1618 * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
1619 * register B channel 1 (read/write).
1620 *
1621 * DDAR2 Direct Memory Access (DMA) Device Address Register
1622 * channel 2 (read/write).
1623 * DCSR2 Direct Memory Access (DMA) Control and Status
1624 * Register channel 2 (read/write).
1625 * DBSA2 Direct Memory Access (DMA) Buffer Start address
1626 * register A channel 2 (read/write).
1627 * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
1628 * register A channel 2 (read/write).
1629 * DBSB2 Direct Memory Access (DMA) Buffer Start address
1630 * register B channel 2 (read/write).
1631 * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
1632 * register B channel 2 (read/write).
1633 *
1634 * DDAR3 Direct Memory Access (DMA) Device Address Register
1635 * channel 3 (read/write).
1636 * DCSR3 Direct Memory Access (DMA) Control and Status
1637 * Register channel 3 (read/write).
1638 * DBSA3 Direct Memory Access (DMA) Buffer Start address
1639 * register A channel 3 (read/write).
1640 * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
1641 * register A channel 3 (read/write).
1642 * DBSB3 Direct Memory Access (DMA) Buffer Start address
1643 * register B channel 3 (read/write).
1644 * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
1645 * register B channel 3 (read/write).
1646 *
1647 * DDAR4 Direct Memory Access (DMA) Device Address Register
1648 * channel 4 (read/write).
1649 * DCSR4 Direct Memory Access (DMA) Control and Status
1650 * Register channel 4 (read/write).
1651 * DBSA4 Direct Memory Access (DMA) Buffer Start address
1652 * register A channel 4 (read/write).
1653 * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
1654 * register A channel 4 (read/write).
1655 * DBSB4 Direct Memory Access (DMA) Buffer Start address
1656 * register B channel 4 (read/write).
1657 * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
1658 * register B channel 4 (read/write).
1659 *
1660 * DDAR5 Direct Memory Access (DMA) Device Address Register
1661 * channel 5 (read/write).
1662 * DCSR5 Direct Memory Access (DMA) Control and Status
1663 * Register channel 5 (read/write).
1664 * DBSA5 Direct Memory Access (DMA) Buffer Start address
1665 * register A channel 5 (read/write).
1666 * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
1667 * register A channel 5 (read/write).
1668 * DBSB5 Direct Memory Access (DMA) Buffer Start address
1669 * register B channel 5 (read/write).
1670 * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
1671 * register B channel 5 (read/write).
1672 */ 1593 */
1673 1594#define DMA_SIZE (6 * 0x20)
1674#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ 1595#define DMA_PHYS 0xb0000000
1675
1676#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
1677#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
1678#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
1679#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
1680#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
1681#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
1682#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
1683#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
1684
1685#define DDAR_RW 0x00000001 /* device data Read/Write */
1686#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
1687 /* (memory -> device) */
1688#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
1689 /* (device -> memory) */
1690#define DDAR_E 0x00000002 /* big/little Endian device */
1691#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
1692#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
1693#define DDAR_BS 0x00000004 /* device Burst Size */
1694#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
1695#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
1696#define DDAR_DW 0x00000008 /* device Data Width */
1697#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
1698#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
1699#define DDAR_DS Fld (4, 4) /* Device Select */
1700#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
1701 (0x0 << FShft (DDAR_DS))
1702#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
1703 (0x1 << FShft (DDAR_DS))
1704#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
1705 (0x2 << FShft (DDAR_DS))
1706#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
1707 (0x3 << FShft (DDAR_DS))
1708#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
1709 (0x4 << FShft (DDAR_DS))
1710#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
1711 (0x5 << FShft (DDAR_DS))
1712#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
1713 (0x6 << FShft (DDAR_DS))
1714#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
1715 (0x7 << FShft (DDAR_DS))
1716#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
1717 (0x8 << FShft (DDAR_DS))
1718#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
1719 (0x9 << FShft (DDAR_DS))
1720#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
1721 /* (audio) */ \
1722 (0xA << FShft (DDAR_DS))
1723#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
1724 /* (audio) */ \
1725 (0xB << FShft (DDAR_DS))
1726#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
1727 /* (telecom) */ \
1728 (0xC << FShft (DDAR_DS))
1729#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
1730 /* (telecom) */ \
1731 (0xD << FShft (DDAR_DS))
1732#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
1733 (0xE << FShft (DDAR_DS))
1734#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
1735 (0xF << FShft (DDAR_DS))
1736#define DDAR_DA Fld (24, 8) /* Device Address */
1737#define DDAR_DevAdd(Add) /* Device Address */ \
1738 (((Add) & 0xF0000000) | \
1739 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
1740#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
1741 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1742 DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1743#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
1744 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1745 DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1746#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
1747 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1748 DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
1749#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
1750 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1751 DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
1752#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
1753 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1754 DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
1755#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
1756 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1757 DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
1758#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
1759 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1760 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
1761#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
1762 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1763 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
1764#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
1765 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1766 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
1767#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
1768 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1769 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
1770#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
1771 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1772 DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
1773#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
1774 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1775 DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
1776#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
1777 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1778 DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1779#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
1780 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1781 DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1782#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
1783 /* (telecom) */ \
1784 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1785 DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1786#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
1787 /* (telecom) */ \
1788 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1789 DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1790#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
1791 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1792 DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
1793#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
1794 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1795 DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
1796
1797#define DCSR_RUN 0x00000001 /* DMA running */
1798#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
1799#define DCSR_ERROR 0x00000004 /* DMA ERROR */
1800#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
1801#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
1802#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
1803#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
1804#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
1805#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
1806#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
1807
1808#define DBT_TC Fld (13, 0) /* Transfer Count */
1809#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
1810#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
1811 1596
1812 1597
1813/* 1598/*
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