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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 13:00:22 -0400 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 13:00:22 -0400 |
commit | d07b3c25327c5ae3792d0ed0c135dee4727200a1 (patch) | |
tree | 2ffad8da1f9004bdeb32bf76faa08fa104797b89 /arch/arm/mach-sa1100/time.c | |
parent | dde33348e53ecab687a9768bf5262f0b8f79b7f2 (diff) | |
parent | 6cbdc8c5357276307a77deeada3f04626ff17da6 (diff) |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits)
[ARM] spelling fixes
[ARM] at91_adc parenthesis balance
[ARM] 4400/1: S3C24XX: Add high-speed MMC device definition
[ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings
[ARM] 4398/1: S3C2443: Fix watchdog IRQ number
[ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity
[ARM] 4396/1: S3C2443: Add missing HCLK clocks
[ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines
[ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu
[ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts
[ARM] ARMv6: add CPU_HAS_ASID configuration
[ARM] integrator: fix pci_v3 compile error with DEBUG_LL
[ARM] gic: Fix gic cascade irq handling
[ARM] Silence OMAP kernel configuration warning
[ARM] Update ARM syscalls
[ARM] 4384/1: S3C2412/13 SPI registers offset correction
[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
[ARM] 4382/1: iop13xx: fix msi support
[ARM] Remove Integrator/CP SMP platform support
[ARM] 4378/1: KS8695: Serial driver fix
...
Diffstat (limited to 'arch/arm/mach-sa1100/time.c')
-rw-r--r-- | arch/arm/mach-sa1100/time.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 416e277054c2..29cb0c1604ab 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c | |||
@@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void) | |||
25 | { | 25 | { |
26 | /* | 26 | /* |
27 | * According to the manual we should be able to let RTTR be zero | 27 | * According to the manual we should be able to let RTTR be zero |
28 | * and then a default diviser for a 32.768KHz clock is used. | 28 | * and then a default divisor for a 32.768KHz clock is used. |
29 | * Apparently this doesn't work, at least for my SA1110 rev 5. | 29 | * Apparently this doesn't work, at least for my SA1110 rev 5. |
30 | * If the clock divider is uninitialized then reset it to the | 30 | * If the clock divider is uninitialized then reset it to the |
31 | * default value to get the 1Hz clock. | 31 | * default value to get the 1Hz clock. |