ARM: 7452/1: delay: allow timer-based delay implementation to be selected

This patch allows a timer-based delay implementation to be selected by
switching the delay routines over to use get_cycles, which is
implemented in terms of read_current_timer. This further allows us to
skip the loop calibration and have a consistent delay function in the
face of core frequency scaling.

To avoid the pain of dealing with memory-mapped counters, this
implementation uses the co-processor interface to the architected timers
when they are available. The previous loop-based implementation is
kept around for CPUs without the architected timers and we retain both
the maximum delay (2ms) and the corresponding conversion factors for
determining the number of loops required for a given interval. Since the
indirection of the timer routines will only work when called from C,
the sa1100 sleep routines are modified to branch to the loop-based delay
functions directly.

Tested-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 30cc6721665b..85863741ef8b 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -38,9 +38,9 @@ ENTRY(sa1100_finish_suspend)
         orr     r4, r4, #MDREFR_K1DB2
         ldr     r5, =PPCR
 
-        @ Pre-load __udelay into the I-cache
+        @ Pre-load __loop_udelay into the I-cache
         mov     r0, #1
-        bl      __udelay
+        bl      __loop_udelay
         mov     r0, r0
 
         @ The following must all exist in a single cache line to
@@ -53,11 +53,11 @@ ENTRY(sa1100_finish_suspend)
         @ delay 90us and set CPU PLL to lowest speed
         @ fixes resume problem on high speed SA1110
         mov     r0, #90
-        bl      __udelay
+        bl      __loop_udelay
         mov     r1, #0
         str     r1, [r5]
         mov     r0, #90
-        bl      __udelay
+        bl      __loop_udelay
 
         /*
          * SA1110 SDRAM controller workaround.  register values: