diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-06-08 12:59:31 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-08 12:59:31 -0400 |
commit | d782f33df706f1b8a4496b41fd7d339c6e23aa59 (patch) | |
tree | ab3241bfff98d3114f5f1337ca3885720f396276 /arch/arm/mach-sa1100/neponset.c | |
parent | 1def630a6a49dda5bc89dfbd86656293640456f0 (diff) |
[ARM] Fix Neponset IRQ handling
While testing the genirq code on ARM, a condition was found whereby
the Neponset IRQ handler was being re-entered, causing the system
to deadlock.
Under the ARM IRQ code, this would not have been a visible problem
because the "simple" IRQ handling had no re-entrancy protection.
Resolve this by acknowledging the parent interrupt after we mask it
when we are going to handle one of our "special" level-based sources
(from ethernet or USAR chip.)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100/neponset.c')
-rw-r--r-- | arch/arm/mach-sa1100/neponset.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 9e02bc3712a0..af6d2775cf82 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c | |||
@@ -59,6 +59,14 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg | |||
59 | if (irr & (IRR_ETHERNET | IRR_USAR)) { | 59 | if (irr & (IRR_ETHERNET | IRR_USAR)) { |
60 | desc->chip->mask(irq); | 60 | desc->chip->mask(irq); |
61 | 61 | ||
62 | /* | ||
63 | * Ack the interrupt now to prevent re-entering | ||
64 | * this neponset handler. Again, this is safe | ||
65 | * since we'll check the IRR register prior to | ||
66 | * leaving. | ||
67 | */ | ||
68 | desc->chip->ack(irq); | ||
69 | |||
62 | if (irr & IRR_ETHERNET) { | 70 | if (irr & IRR_ETHERNET) { |
63 | d = irq_desc + IRQ_NEPONSET_SMC9196; | 71 | d = irq_desc + IRQ_NEPONSET_SMC9196; |
64 | desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); | 72 | desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); |