Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.

3 files changed, 25 insertions, 25 deletions

diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 62aaf04a3906..4f7ea012e1e5 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -2054,19 +2054,3 @@
                                         /* active display mode)            */
 #define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High      */
 #define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low       */
-
-#ifndef __ASSEMBLY__
-extern unsigned int processor_id;
-#endif
-
-#define CPU_REVISION    (processor_id & 15)
-#define CPU_SA1110_A0   (0)
-#define CPU_SA1110_B0   (4)
-#define CPU_SA1110_B1   (5)
-#define CPU_SA1110_B2   (6)
-#define CPU_SA1110_B4   (8)
-
-#define CPU_SA1100_ID   (0x4401a110)
-#define CPU_SA1100_MASK (0xfffffff0)
-#define CPU_SA1110_ID   (0x6901b110)
-#define CPU_SA1110_MASK (0xfffffff0)
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 5976435f42c2..b70846c096aa 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -36,8 +36,26 @@
 #define io_v2p( x )             \
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
+#define CPU_SA1110_A0   (0)
+#define CPU_SA1110_B0   (4)
+#define CPU_SA1110_B1   (5)
+#define CPU_SA1110_B2   (6)
+#define CPU_SA1110_B4   (8)
+
+#define CPU_SA1100_ID   (0x4401a110)
+#define CPU_SA1100_MASK (0xfffffff0)
+#define CPU_SA1110_ID   (0x6901b110)
+#define CPU_SA1110_MASK (0xfffffff0)
+
 #ifndef __ASSEMBLY__
 
+#include <asm/cputype.h>
+
+#define CPU_REVISION    (read_cpuid_id() & 15)
+
+#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
+#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
+
 # define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
 # define __PREG(x)      (io_v2p((unsigned long)&(x)))
 
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index 29f639e2afc6..1c127b68581d 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -40,23 +40,21 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
 /*
- * Because of the wide memory address space between physical RAM banks on the 
- * SA1100, it's much convenient to use Linux's NUMA support to implement our 
- * memory map representation.  Assuming all memory nodes have equal access 
+ * Because of the wide memory address space between physical RAM banks on the
+ * SA1100, it's much convenient to use Linux's SparseMEM support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access
  * characteristics, we then have generic discontiguous memory support.
  *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are 
- * incidentally the same as virtual addresses.
+ * The sparsemem banks are matched with the physical memory bank addresses
+ * which are incidentally the same as virtual addresses.
  * 
  *      node 0:  0xc0000000 - 0xc7ffffff
  *      node 1:  0xc8000000 - 0xcfffffff
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-#define NODE_MEM_SIZE_BITS      27
+#define MAX_PHYSMEM_BITS        32
+#define SECTION_SIZE_BITS       27
 
 /*
  * Cache flushing area - SA1100 zero bank