aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-sa1100/include/mach
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2012-01-13 18:06:09 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-02-21 09:27:02 -0500
commit3b61436a792517848ee386bd2ccf4fc3a75f1a0f (patch)
tree86c0b6149e5bbdf488aee3f2eb479cc37905e358 /arch/arm/mach-sa1100/include/mach
parent76346a4eabf85a44dc425c0197ba46a8884e6090 (diff)
PCMCIA: sa11x0: shannon: convert to use new irq/gpio management
Convert Shannon socket driver to use the new irq/gpio management. This is slightly more involved because we have to touch the private platform header file to modify the GPIO bitmasks to be GPIO numbers. Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach')
-rw-r--r--arch/arm/mach-sa1100/include/mach/shannon.h12
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e12140..019f857a7938 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -23,14 +23,10 @@
23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ 24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */
25/* XXX GPIO 23 unaccounted for */ 25/* XXX GPIO 23 unaccounted for */
26#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ 26#define SHANNON_GPIO_EJECT_0 24 /* in */
27#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 27#define SHANNON_GPIO_EJECT_1 25 /* in */
28#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ 28#define SHANNON_GPIO_RDY_0 26 /* in */
29#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 29#define SHANNON_GPIO_RDY_1 27 /* in */
30#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */
31#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26
32#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */
33#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27
34 30
35/* MCP UCB codec GPIO pins... */ 31/* MCP UCB codec GPIO pins... */
36 32