aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pv310
diff options
context:
space:
mode:
authorKukjin Kim <kgene.kim@samsung.com>2011-01-03 05:20:21 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-01-03 05:20:21 -0500
commitf651ef6575d8816143afbad4492584979589bd46 (patch)
tree48d8cd0acd54822e7732158ed012caff44dc7100 /arch/arm/mach-s5pv310
parentc6906c3e29a4a28660f70421935c91cf6b8ab1e1 (diff)
parent04ea1cc8ab0f1e9db9aeaef79476e5c1a2027f6a (diff)
Merge branch 'next-samsung-irq_data' into for-next
Diffstat (limited to 'arch/arm/mach-s5pv310')
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c26
-rw-r--r--arch/arm/mach-s5pv310/irq-eint.c53
2 files changed, 41 insertions, 38 deletions
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index aad5c3d525d1..1ea4a9e83bbe 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -30,24 +30,26 @@ struct combiner_chip_data {
30 30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; 31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32 32
33static inline void __iomem *combiner_base(unsigned int irq) 33static inline void __iomem *combiner_base(struct irq_data *data)
34{ 34{
35 struct combiner_chip_data *combiner_data = get_irq_chip_data(irq); 35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
36 return combiner_data->base; 38 return combiner_data->base;
37} 39}
38 40
39static void combiner_mask_irq(unsigned int irq) 41static void combiner_mask_irq(struct irq_data *data)
40{ 42{
41 u32 mask = 1 << (irq % 32); 43 u32 mask = 1 << (data->irq % 32);
42 44
43 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR); 45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
44} 46}
45 47
46static void combiner_unmask_irq(unsigned int irq) 48static void combiner_unmask_irq(struct irq_data *data)
47{ 49{
48 u32 mask = 1 << (irq % 32); 50 u32 mask = 1 << (data->irq % 32);
49 51
50 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET); 52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
51} 53}
52 54
53static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -58,7 +60,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
58 unsigned long status; 60 unsigned long status;
59 61
60 /* primary controller ack'ing */ 62 /* primary controller ack'ing */
61 chip->ack(irq); 63 chip->irq_ack(&desc->irq_data);
62 64
63 spin_lock(&irq_controller_lock); 65 spin_lock(&irq_controller_lock);
64 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -78,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
78 80
79 out: 81 out:
80 /* primary controller unmasking */ 82 /* primary controller unmasking */
81 chip->unmask(irq); 83 chip->irq_unmask(&desc->irq_data);
82} 84}
83 85
84static struct irq_chip combiner_chip = { 86static struct irq_chip combiner_chip = {
85 .name = "COMBINER", 87 .name = "COMBINER",
86 .mask = combiner_mask_irq, 88 .irq_mask = combiner_mask_irq,
87 .unmask = combiner_unmask_irq, 89 .irq_unmask = combiner_unmask_irq,
88}; 90};
89 91
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 92void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
index f5a415edc0b6..477bd9e97f0f 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -48,42 +48,43 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
48 return ret; 48 return ret;
49} 49}
50 50
51static inline void s5pv310_irq_eint_mask(unsigned int irq) 51static inline void s5pv310_irq_eint_mask(struct irq_data *data)
52{ 52{
53 u32 mask; 53 u32 mask;
54 54
55 spin_lock(&eint_lock); 55 spin_lock(&eint_lock);
56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
57 mask |= eint_irq_to_bit(irq); 57 mask |= eint_irq_to_bit(data->irq);
58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 spin_unlock(&eint_lock); 59 spin_unlock(&eint_lock);
60} 60}
61 61
62static void s5pv310_irq_eint_unmask(unsigned int irq) 62static void s5pv310_irq_eint_unmask(struct irq_data *data)
63{ 63{
64 u32 mask; 64 u32 mask;
65 65
66 spin_lock(&eint_lock); 66 spin_lock(&eint_lock);
67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
68 mask &= ~(eint_irq_to_bit(irq)); 68 mask &= ~(eint_irq_to_bit(data->irq));
69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 spin_unlock(&eint_lock); 70 spin_unlock(&eint_lock);
71} 71}
72 72
73static inline void s5pv310_irq_eint_ack(unsigned int irq) 73static inline void s5pv310_irq_eint_ack(struct irq_data *data)
74{ 74{
75 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); 75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
76} 77}
77 78
78static void s5pv310_irq_eint_maskack(unsigned int irq) 79static void s5pv310_irq_eint_maskack(struct irq_data *data)
79{ 80{
80 s5pv310_irq_eint_mask(irq); 81 s5pv310_irq_eint_mask(data);
81 s5pv310_irq_eint_ack(irq); 82 s5pv310_irq_eint_ack(data);
82} 83}
83 84
84static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) 85static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
85{ 86{
86 int offs = EINT_OFFSET(irq); 87 int offs = EINT_OFFSET(data->irq);
87 int shift; 88 int shift;
88 u32 ctrl, mask; 89 u32 ctrl, mask;
89 u32 newvalue = 0; 90 u32 newvalue = 0;
@@ -118,10 +119,10 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
118 mask = 0x7 << shift; 119 mask = 0x7 << shift;
119 120
120 spin_lock(&eint_lock); 121 spin_lock(&eint_lock);
121 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); 122 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
122 ctrl &= ~mask; 123 ctrl &= ~mask;
123 ctrl |= newvalue << shift; 124 ctrl |= newvalue << shift;
124 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); 125 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 spin_unlock(&eint_lock); 126 spin_unlock(&eint_lock);
126 127
127 switch (offs) { 128 switch (offs) {
@@ -146,11 +147,11 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
146 147
147static struct irq_chip s5pv310_irq_eint = { 148static struct irq_chip s5pv310_irq_eint = {
148 .name = "s5pv310-eint", 149 .name = "s5pv310-eint",
149 .mask = s5pv310_irq_eint_mask, 150 .irq_mask = s5pv310_irq_eint_mask,
150 .unmask = s5pv310_irq_eint_unmask, 151 .irq_unmask = s5pv310_irq_eint_unmask,
151 .mask_ack = s5pv310_irq_eint_maskack, 152 .irq_mask_ack = s5pv310_irq_eint_maskack,
152 .ack = s5pv310_irq_eint_ack, 153 .irq_ack = s5pv310_irq_eint_ack,
153 .set_type = s5pv310_irq_eint_set_type, 154 .irq_set_type = s5pv310_irq_eint_set_type,
154#ifdef CONFIG_PM 155#ifdef CONFIG_PM
155 .irq_set_wake = s3c_irqext_wake, 156 .irq_set_wake = s3c_irqext_wake,
156#endif 157#endif
@@ -192,14 +193,14 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = get_irq_data(irq);
193 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = get_irq_chip(irq);
194 195
195 chip->mask(irq); 196 chip->irq_mask(&desc->irq_data);
196 197
197 if (chip->ack) 198 if (chip->irq_ack)
198 chip->ack(irq); 199 chip->irq_ack(&desc->irq_data);
199 200
200 generic_handle_irq(*irq_data); 201 generic_handle_irq(*irq_data);
201 202
202 chip->unmask(irq); 203 chip->irq_unmask(&desc->irq_data);
203} 204}
204 205
205int __init s5pv310_init_irq_eint(void) 206int __init s5pv310_init_irq_eint(void)