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authorKukjin Kim <kgene.kim@samsung.com>2011-02-14 02:33:10 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-02-21 23:51:14 -0500
commit7d30e8b3815f804139271dfc31962ab74ce89650 (patch)
tree711d4830705e0147cb8184ca1a8e6e3c97bc02fe /arch/arm/mach-s5pv310
parentf5412be599602124d2bdd49947b231dd77c0bf99 (diff)
ARM: EXYNOS4: Add EXYNOS4 CPU initialization support
This patch adds EXYNOS4 CPU support files in mach-exynos4, and basically they are moved from mach-s5pv310 so that it can support Samsung's new CPU name, EXYNOS4. The EXYNOS4 ingegrates a ARM Cortex A9 multi-core. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv310')
-rw-r--r--arch/arm/mach-s5pv310/cpu.c202
-rw-r--r--arch/arm/mach-s5pv310/cpufreq.c580
-rw-r--r--arch/arm/mach-s5pv310/dma.c168
-rw-r--r--arch/arm/mach-s5pv310/gpiolib.c304
-rw-r--r--arch/arm/mach-s5pv310/headsmp.S41
-rw-r--r--arch/arm/mach-s5pv310/hotplug.c130
-rw-r--r--arch/arm/mach-s5pv310/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-s5pv310/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pv310/include/mach/entry-macro.S84
-rw-r--r--arch/arm/mach-s5pv310/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-s5pv310/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5pv310/include/mach/io.h26
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h144
-rw-r--r--arch/arm/mach-s5pv310/include/mach/memory.h22
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-mem.h23
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-pmu.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h24
-rw-r--r--arch/arm/mach-s5pv310/include/mach/smp.h19
-rw-r--r--arch/arm/mach-s5pv310/include/mach/sysmmu.h122
-rw-r--r--arch/arm/mach-s5pv310/include/mach/system.h22
-rw-r--r--arch/arm/mach-s5pv310/include/mach/timex.h29
-rw-r--r--arch/arm/mach-s5pv310/include/mach/uncompress.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/vmalloc.h22
-rw-r--r--arch/arm/mach-s5pv310/init.c41
-rw-r--r--arch/arm/mach-s5pv310/platsmp.c172
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c0.c26
27 files changed, 0 insertions, 2517 deletions
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
deleted file mode 100644
index 0db0fb65bd70..000000000000
--- a/arch/arm/mach-s5pv310/cpu.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/cpu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h>
19
20#include <plat/cpu.h>
21#include <plat/clock.h>
22#include <plat/s5pv310.h>
23#include <plat/sdhci.h>
24
25#include <mach/regs-irq.h>
26
27extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
28 unsigned int irq_start);
29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
30
31/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = {
33 {
34 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU),
41 .length = SZ_128K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = (unsigned long)S5P_VA_PMU,
45 .pfn = __phys_to_pfn(S5PV310_PA_PMU),
46 .length = SZ_64K,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
55 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
56 .length = SZ_8K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)S5P_VA_L2CC,
60 .pfn = __phys_to_pfn(S5PV310_PA_L2CC),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (unsigned long)S5P_VA_GPIO1,
65 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (unsigned long)S5P_VA_GPIO2,
70 .pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = (unsigned long)S5P_VA_GPIO3,
75 .pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
76 .length = SZ_256,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (unsigned long)S5P_VA_DMC0,
80 .pfn = __phys_to_pfn(S5PV310_PA_DMC0),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 }, {
84 .virtual = (unsigned long)S3C_VA_UART,
85 .pfn = __phys_to_pfn(S3C_PA_UART),
86 .length = SZ_512K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S5P_VA_SROMC,
90 .pfn = __phys_to_pfn(S5PV310_PA_SROMC),
91 .length = SZ_4K,
92 .type = MT_DEVICE,
93 },
94};
95
96static void s5pv310_idle(void)
97{
98 if (!need_resched())
99 cpu_do_idle();
100
101 local_irq_enable();
102}
103
104/* s5pv310_map_io
105 *
106 * register the standard cpu IO areas
107*/
108void __init s5pv310_map_io(void)
109{
110 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
111
112 /* initialize device information early */
113 s5pv310_default_sdhci0();
114 s5pv310_default_sdhci1();
115 s5pv310_default_sdhci2();
116 s5pv310_default_sdhci3();
117}
118
119void __init s5pv310_init_clocks(int xtal)
120{
121 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
122
123 s3c24xx_register_baseclocks(xtal);
124 s5p_register_clocks(xtal);
125 s5pv310_register_clocks();
126 s5pv310_setup_clocks();
127}
128
129void __init s5pv310_init_irq(void)
130{
131 int irq;
132
133 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
134
135 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
136
137 /*
138 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
139 * connected to the interrupt combiner. These irqs
140 * should be initialized to support cascade interrupt.
141 */
142 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
143 continue;
144
145 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
146 COMBINER_IRQ(irq, 0));
147 combiner_cascade_irq(irq, IRQ_SPI(irq));
148 }
149
150 /* The parameters of s5p_init_irq() are for VIC init.
151 * Theses parameters should be NULL and 0 because S5PV310
152 * uses GIC instead of VIC.
153 */
154 s5p_init_irq(NULL, 0);
155}
156
157struct sysdev_class s5pv310_sysclass = {
158 .name = "s5pv310-core",
159};
160
161static struct sys_device s5pv310_sysdev = {
162 .cls = &s5pv310_sysclass,
163};
164
165static int __init s5pv310_core_init(void)
166{
167 return sysdev_class_register(&s5pv310_sysclass);
168}
169
170core_initcall(s5pv310_core_init);
171
172#ifdef CONFIG_CACHE_L2X0
173static int __init s5pv310_l2x0_cache_init(void)
174{
175 /* TAG, Data Latency Control: 2cycle */
176 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
177 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
178
179 /* L2X0 Prefetch Control */
180 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
181
182 /* L2X0 Power Control */
183 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
184 S5P_VA_L2CC + L2X0_POWER_CTRL);
185
186 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
187
188 return 0;
189}
190
191early_initcall(s5pv310_l2x0_cache_init);
192#endif
193
194int __init s5pv310_init(void)
195{
196 printk(KERN_INFO "S5PV310: Initializing architecture\n");
197
198 /* set idle function */
199 pm_idle = s5pv310_idle;
200
201 return sysdev_register(&s5pv310_sysdev);
202}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c
deleted file mode 100644
index b04cbc731128..000000000000
--- a/arch/arm/mach-s5pv310/cpufreq.c
+++ /dev/null
@@ -1,580 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - CPU frequency scaling support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/regulator/consumer.h>
20#include <linux/cpufreq.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24#include <mach/regs-mem.h>
25
26#include <plat/clock.h>
27#include <plat/pm.h>
28
29static struct clk *cpu_clk;
30static struct clk *moutcore;
31static struct clk *mout_mpll;
32static struct clk *mout_apll;
33
34#ifdef CONFIG_REGULATOR
35static struct regulator *arm_regulator;
36static struct regulator *int_regulator;
37#endif
38
39static struct cpufreq_freqs freqs;
40static unsigned int memtype;
41
42enum s5pv310_memory_type {
43 DDR2 = 4,
44 LPDDR2,
45 DDR3,
46};
47
48enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50};
51
52static struct cpufreq_frequency_table s5pv310_freq_table[] = {
53 {L0, 1000*1000},
54 {L1, 800*1000},
55 {L2, 400*1000},
56 {L3, 100*1000},
57 {0, CPUFREQ_TABLE_END},
58};
59
60static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
61 /*
62 * Clock divider value for following
63 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
64 * DIVATB, DIVPCLK_DBG, DIVAPLL }
65 */
66
67 /* ARM L0: 1000MHz */
68 { 0, 3, 7, 3, 3, 0, 1 },
69
70 /* ARM L1: 800MHz */
71 { 0, 3, 7, 3, 3, 0, 1 },
72
73 /* ARM L2: 400MHz */
74 { 0, 1, 3, 1, 3, 0, 1 },
75
76 /* ARM L3: 100MHz */
77 { 0, 0, 1, 0, 3, 1, 1 },
78};
79
80static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
81 /*
82 * Clock divider value for following
83 * { DIVCOPY, DIVHPM }
84 */
85
86 /* ARM L0: 1000MHz */
87 { 3, 0 },
88
89 /* ARM L1: 800MHz */
90 { 3, 0 },
91
92 /* ARM L2: 400MHz */
93 { 3, 0 },
94
95 /* ARM L3: 100MHz */
96 { 3, 0 },
97};
98
99static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
100 /*
101 * Clock divider value for following
102 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
103 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
104 */
105
106 /* DMC L0: 400MHz */
107 { 3, 1, 1, 1, 1, 1, 3, 1 },
108
109 /* DMC L1: 400MHz */
110 { 3, 1, 1, 1, 1, 1, 3, 1 },
111
112 /* DMC L2: 266.7MHz */
113 { 7, 1, 1, 2, 1, 1, 3, 1 },
114
115 /* DMC L3: 200MHz */
116 { 7, 1, 1, 3, 1, 1, 3, 1 },
117};
118
119static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
120 /*
121 * Clock divider value for following
122 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
123 */
124
125 /* ACLK200 L0: 200MHz */
126 { 3, 7, 4, 5, 1 },
127
128 /* ACLK200 L1: 200MHz */
129 { 3, 7, 4, 5, 1 },
130
131 /* ACLK200 L2: 160MHz */
132 { 4, 7, 5, 7, 1 },
133
134 /* ACLK200 L3: 133.3MHz */
135 { 5, 7, 7, 7, 1 },
136};
137
138static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
139 /*
140 * Clock divider value for following
141 * { DIVGDL/R, DIVGPL/R }
142 */
143
144 /* ACLK_GDL/R L0: 200MHz */
145 { 3, 1 },
146
147 /* ACLK_GDL/R L1: 200MHz */
148 { 3, 1 },
149
150 /* ACLK_GDL/R L2: 160MHz */
151 { 4, 1 },
152
153 /* ACLK_GDL/R L3: 133.3MHz */
154 { 5, 1 },
155};
156
157struct cpufreq_voltage_table {
158 unsigned int index; /* any */
159 unsigned int arm_volt; /* uV */
160 unsigned int int_volt;
161};
162
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
164 {
165 .index = L0,
166 .arm_volt = 1200000,
167 .int_volt = 1100000,
168 }, {
169 .index = L1,
170 .arm_volt = 1100000,
171 .int_volt = 1100000,
172 }, {
173 .index = L2,
174 .arm_volt = 1000000,
175 .int_volt = 1000000,
176 }, {
177 .index = L3,
178 .arm_volt = 900000,
179 .int_volt = 1000000,
180 },
181};
182
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1),
186
187 /* APLL FOUT L1: 800MHz */
188 ((200 << 16) | (6 << 8) | 1),
189
190 /* APLL FOUT L2 : 400MHz */
191 ((200 << 16) | (6 << 8) | 2),
192
193 /* APLL FOUT L3: 100MHz */
194 ((200 << 16) | (6 << 8) | 4),
195};
196
197int s5pv310_verify_speed(struct cpufreq_policy *policy)
198{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
200}
201
202unsigned int s5pv310_getspeed(unsigned int cpu)
203{
204 return clk_get_rate(cpu_clk) / 1000;
205}
206
207void s5pv310_set_clkdiv(unsigned int div_index)
208{
209 unsigned int tmp;
210
211 /* Change Divider - CPU0 */
212
213 tmp = __raw_readl(S5P_CLKDIV_CPU);
214
215 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
216 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
217 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
218 S5P_CLKDIV_CPU0_APLL_MASK);
219
220 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
221 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
222 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
223 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
224 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
225 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
226 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
227
228 __raw_writel(tmp, S5P_CLKDIV_CPU);
229
230 do {
231 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
232 } while (tmp & 0x1111111);
233
234 /* Change Divider - CPU1 */
235
236 tmp = __raw_readl(S5P_CLKDIV_CPU1);
237
238 tmp &= ~((0x7 << 4) | 0x7);
239
240 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
241 (clkdiv_cpu1[div_index][1] << 0));
242
243 __raw_writel(tmp, S5P_CLKDIV_CPU1);
244
245 do {
246 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
247 } while (tmp & 0x11);
248
249 /* Change Divider - DMC0 */
250
251 tmp = __raw_readl(S5P_CLKDIV_DMC0);
252
253 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
254 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
255 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
256 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
257
258 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
259 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
260 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
261 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
262 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
263 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
264 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
265 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
266
267 __raw_writel(tmp, S5P_CLKDIV_DMC0);
268
269 do {
270 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
271 } while (tmp & 0x11111111);
272
273 /* Change Divider - TOP */
274
275 tmp = __raw_readl(S5P_CLKDIV_TOP);
276
277 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
278 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
279 S5P_CLKDIV_TOP_ONENAND_MASK);
280
281 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
282 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
283 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
284 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
285 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
286
287 __raw_writel(tmp, S5P_CLKDIV_TOP);
288
289 do {
290 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
291 } while (tmp & 0x11111);
292
293 /* Change Divider - LEFTBUS */
294
295 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
296
297 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
298
299 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
300 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
301
302 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
303
304 do {
305 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
306 } while (tmp & 0x11);
307
308 /* Change Divider - RIGHTBUS */
309
310 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
311
312 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
313
314 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
315 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
316
317 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
318
319 do {
320 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
321 } while (tmp & 0x11);
322}
323
324static void s5pv310_set_apll(unsigned int index)
325{
326 unsigned int tmp;
327
328 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
329 clk_set_parent(moutcore, mout_mpll);
330
331 do {
332 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
333 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
334 tmp &= 0x7;
335 } while (tmp != 0x2);
336
337 /* 2. Set APLL Lock time */
338 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
339
340 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0);
345
346 /* 4. wait_lock_time */
347 do {
348 tmp = __raw_readl(S5P_APLL_CON0);
349 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
350
351 /* 5. MUX_CORE_SEL = APLL */
352 clk_set_parent(moutcore, mout_apll);
353
354 do {
355 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
356 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358}
359
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
361{
362 unsigned int tmp;
363
364 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index);
369
370 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index);
372 } else {
373 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index);
375
376 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0);
381 }
382 }
383
384 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index);
389
390 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index);
392 } else {
393 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0);
398
399 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index);
401 }
402 }
403}
404
405static int s5pv310_target(struct cpufreq_policy *policy,
406 unsigned int target_freq,
407 unsigned int relation)
408{
409 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt;
411
412 freqs.old = s5pv310_getspeed(policy->cpu);
413
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
415 freqs.old, relation, &old_index))
416 return -EINVAL;
417
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
419 target_freq, relation, &index))
420 return -EINVAL;
421
422 freqs.new = s5pv310_freq_table[index].frequency;
423 freqs.cpu = policy->cpu;
424
425 if (freqs.new == freqs.old)
426 return 0;
427
428 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt;
431
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433
434 /* control regulator */
435 if (freqs.new > freqs.old) {
436 /* Voltage up */
437#ifdef CONFIG_REGULATOR
438 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
439 regulator_set_voltage(int_regulator, int_volt, int_volt);
440#endif
441 }
442
443 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index);
445
446 /* control regulator */
447 if (freqs.new < freqs.old) {
448 /* Voltage down */
449#ifdef CONFIG_REGULATOR
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt);
452#endif
453 }
454
455 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
456
457 return 0;
458}
459
460#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
462 pm_message_t pmsg)
463{
464 return 0;
465}
466
467static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
468{
469 return 0;
470}
471#endif
472
473static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
474{
475 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
476
477 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
478
479 /* set the transition latency value */
480 policy->cpuinfo.transition_latency = 100000;
481
482 /*
483 * S5PV310 multi-core processors has 2 cores
484 * that the frequency cannot be set independently.
485 * Each cpu is bound to the same speed.
486 * So the affected cpu is all of the cpus.
487 */
488 cpumask_setall(policy->cpus);
489
490 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
491}
492
493static struct cpufreq_driver s5pv310_driver = {
494 .flags = CPUFREQ_STICKY,
495 .verify = s5pv310_verify_speed,
496 .target = s5pv310_target,
497 .get = s5pv310_getspeed,
498 .init = s5pv310_cpufreq_cpu_init,
499 .name = "s5pv310_cpufreq",
500#ifdef CONFIG_PM
501 .suspend = s5pv310_cpufreq_suspend,
502 .resume = s5pv310_cpufreq_resume,
503#endif
504};
505
506static int __init s5pv310_cpufreq_init(void)
507{
508 cpu_clk = clk_get(NULL, "armclk");
509 if (IS_ERR(cpu_clk))
510 return PTR_ERR(cpu_clk);
511
512 moutcore = clk_get(NULL, "moutcore");
513 if (IS_ERR(moutcore))
514 goto out;
515
516 mout_mpll = clk_get(NULL, "mout_mpll");
517 if (IS_ERR(mout_mpll))
518 goto out;
519
520 mout_apll = clk_get(NULL, "mout_apll");
521 if (IS_ERR(mout_apll))
522 goto out;
523
524#ifdef CONFIG_REGULATOR
525 arm_regulator = regulator_get(NULL, "vdd_arm");
526 if (IS_ERR(arm_regulator)) {
527 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
528 goto out;
529 }
530
531 int_regulator = regulator_get(NULL, "vdd_int");
532 if (IS_ERR(int_regulator)) {
533 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
534 goto out;
535 }
536#endif
537
538 /*
539 * Check DRAM type.
540 * Because DVFS level is different according to DRAM type.
541 */
542 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
543 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
544 memtype &= S5P_DMC0_MEMTYPE_MASK;
545
546 if ((memtype < DDR2) && (memtype > DDR3)) {
547 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
548 goto out;
549 } else {
550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
551 }
552
553 return cpufreq_register_driver(&s5pv310_driver);
554
555out:
556 if (!IS_ERR(cpu_clk))
557 clk_put(cpu_clk);
558
559 if (!IS_ERR(moutcore))
560 clk_put(moutcore);
561
562 if (!IS_ERR(mout_mpll))
563 clk_put(mout_mpll);
564
565 if (!IS_ERR(mout_apll))
566 clk_put(mout_apll);
567
568#ifdef CONFIG_REGULATOR
569 if (!IS_ERR(arm_regulator))
570 regulator_put(arm_regulator);
571
572 if (!IS_ERR(int_regulator))
573 regulator_put(int_regulator);
574#endif
575
576 printk(KERN_ERR "%s: failed initialization\n", __func__);
577
578 return -EINVAL;
579}
580late_initcall(s5pv310_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-s5pv310/dma.c
deleted file mode 100644
index 20066c7c9e56..000000000000
--- a/arch/arm/mach-s5pv310/dma.c
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h>
27#include <mach/irqs.h>
28
29#include <plat/s3c-pl330-pdata.h>
30
31static u64 dma_dmamask = DMA_BIT_MASK(32);
32
33static struct resource s5pv310_pdma0_resource[] = {
34 [0] = {
35 .start = S5PV310_PA_PDMA0,
36 .end = S5PV310_PA_PDMA0 + SZ_4K,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_PDMA0,
41 .end = IRQ_PDMA0,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
47 .peri = {
48 [0] = DMACH_PCM0_RX,
49 [1] = DMACH_PCM0_TX,
50 [2] = DMACH_PCM2_RX,
51 [3] = DMACH_PCM2_TX,
52 [4] = DMACH_MSM_REQ0,
53 [5] = DMACH_MSM_REQ2,
54 [6] = DMACH_SPI0_RX,
55 [7] = DMACH_SPI0_TX,
56 [8] = DMACH_SPI2_RX,
57 [9] = DMACH_SPI2_TX,
58 [10] = DMACH_I2S0S_TX,
59 [11] = DMACH_I2S0_RX,
60 [12] = DMACH_I2S0_TX,
61 [13] = DMACH_I2S2_RX,
62 [14] = DMACH_I2S2_TX,
63 [15] = DMACH_UART0_RX,
64 [16] = DMACH_UART0_TX,
65 [17] = DMACH_UART2_RX,
66 [18] = DMACH_UART2_TX,
67 [19] = DMACH_UART4_RX,
68 [20] = DMACH_UART4_TX,
69 [21] = DMACH_SLIMBUS0_RX,
70 [22] = DMACH_SLIMBUS0_TX,
71 [23] = DMACH_SLIMBUS2_RX,
72 [24] = DMACH_SLIMBUS2_TX,
73 [25] = DMACH_SLIMBUS4_RX,
74 [26] = DMACH_SLIMBUS4_TX,
75 [27] = DMACH_AC97_MICIN,
76 [28] = DMACH_AC97_PCMIN,
77 [29] = DMACH_AC97_PCMOUT,
78 [30] = DMACH_MAX,
79 [31] = DMACH_MAX,
80 },
81};
82
83static struct platform_device s5pv310_device_pdma0 = {
84 .name = "s3c-pl330",
85 .id = 0,
86 .num_resources = ARRAY_SIZE(s5pv310_pdma0_resource),
87 .resource = s5pv310_pdma0_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv310_pdma0_pdata,
92 },
93};
94
95static struct resource s5pv310_pdma1_resource[] = {
96 [0] = {
97 .start = S5PV310_PA_PDMA1,
98 .end = S5PV310_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM,
100 },
101 [1] = {
102 .start = IRQ_PDMA1,
103 .end = IRQ_PDMA1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
109 .peri = {
110 [0] = DMACH_PCM0_RX,
111 [1] = DMACH_PCM0_TX,
112 [2] = DMACH_PCM1_RX,
113 [3] = DMACH_PCM1_TX,
114 [4] = DMACH_MSM_REQ1,
115 [5] = DMACH_MSM_REQ3,
116 [6] = DMACH_SPI1_RX,
117 [7] = DMACH_SPI1_TX,
118 [8] = DMACH_I2S0S_TX,
119 [9] = DMACH_I2S0_RX,
120 [10] = DMACH_I2S0_TX,
121 [11] = DMACH_I2S1_RX,
122 [12] = DMACH_I2S1_TX,
123 [13] = DMACH_UART0_RX,
124 [14] = DMACH_UART0_TX,
125 [15] = DMACH_UART1_RX,
126 [16] = DMACH_UART1_TX,
127 [17] = DMACH_UART3_RX,
128 [18] = DMACH_UART3_TX,
129 [19] = DMACH_SLIMBUS1_RX,
130 [20] = DMACH_SLIMBUS1_TX,
131 [21] = DMACH_SLIMBUS3_RX,
132 [22] = DMACH_SLIMBUS3_TX,
133 [23] = DMACH_SLIMBUS5_RX,
134 [24] = DMACH_SLIMBUS5_TX,
135 [25] = DMACH_SLIMBUS0AUX_RX,
136 [26] = DMACH_SLIMBUS0AUX_TX,
137 [27] = DMACH_SPDIF,
138 [28] = DMACH_MAX,
139 [29] = DMACH_MAX,
140 [30] = DMACH_MAX,
141 [31] = DMACH_MAX,
142 },
143};
144
145static struct platform_device s5pv310_device_pdma1 = {
146 .name = "s3c-pl330",
147 .id = 1,
148 .num_resources = ARRAY_SIZE(s5pv310_pdma1_resource),
149 .resource = s5pv310_pdma1_resource,
150 .dev = {
151 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv310_pdma1_pdata,
154 },
155};
156
157static struct platform_device *s5pv310_dmacs[] __initdata = {
158 &s5pv310_device_pdma0,
159 &s5pv310_device_pdma1,
160};
161
162static int __init s5pv310_dma_init(void)
163{
164 platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
165
166 return 0;
167}
168arch_initcall(s5pv310_dma_init);
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c
deleted file mode 100644
index 55217b8923ec..000000000000
--- a/arch/arm/mach-s5pv310/gpiolib.c
+++ /dev/null
@@ -1,304 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = S5PV310_GPA0(0),
50 .ngpio = S5PV310_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = S5PV310_GPA1(0),
56 .ngpio = S5PV310_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = S5PV310_GPB(0),
62 .ngpio = S5PV310_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = S5PV310_GPC0(0),
68 .ngpio = S5PV310_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = S5PV310_GPC1(0),
74 .ngpio = S5PV310_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = S5PV310_GPD0(0),
80 .ngpio = S5PV310_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = S5PV310_GPD1(0),
86 .ngpio = S5PV310_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = S5PV310_GPE0(0),
92 .ngpio = S5PV310_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = S5PV310_GPE1(0),
98 .ngpio = S5PV310_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = S5PV310_GPE2(0),
104 .ngpio = S5PV310_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = S5PV310_GPE3(0),
110 .ngpio = S5PV310_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = S5PV310_GPE4(0),
116 .ngpio = S5PV310_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = S5PV310_GPF0(0),
122 .ngpio = S5PV310_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = S5PV310_GPF1(0),
128 .ngpio = S5PV310_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = S5PV310_GPF2(0),
134 .ngpio = S5PV310_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = S5PV310_GPF3(0),
140 .ngpio = S5PV310_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = S5PV310_GPJ0(0),
150 .ngpio = S5PV310_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = S5PV310_GPJ1(0),
156 .ngpio = S5PV310_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = S5PV310_GPK0(0),
162 .ngpio = S5PV310_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV310_GPK1(0),
168 .ngpio = S5PV310_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV310_GPK2(0),
174 .ngpio = S5PV310_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV310_GPK3(0),
180 .ngpio = S5PV310_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV310_GPL0(0),
186 .ngpio = S5PV310_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = S5PV310_GPL1(0),
192 .ngpio = S5PV310_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = S5PV310_GPL2(0),
198 .ngpio = S5PV310_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .base = (S5P_VA_GPIO2 + 0xC00),
203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0),
205 .chip = {
206 .base = S5PV310_GPX0(0),
207 .ngpio = S5PV310_GPIO_X0_NR,
208 .label = "GPX0",
209 .to_irq = samsung_gpiolib_to_irq,
210 },
211 }, {
212 .base = (S5P_VA_GPIO2 + 0xC20),
213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8),
215 .chip = {
216 .base = S5PV310_GPX1(0),
217 .ngpio = S5PV310_GPIO_X1_NR,
218 .label = "GPX1",
219 .to_irq = samsung_gpiolib_to_irq,
220 },
221 }, {
222 .base = (S5P_VA_GPIO2 + 0xC40),
223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16),
225 .chip = {
226 .base = S5PV310_GPX2(0),
227 .ngpio = S5PV310_GPIO_X2_NR,
228 .label = "GPX2",
229 .to_irq = samsung_gpiolib_to_irq,
230 },
231 }, {
232 .base = (S5P_VA_GPIO2 + 0xC60),
233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24),
235 .chip = {
236 .base = S5PV310_GPX3(0),
237 .ngpio = S5PV310_GPIO_X3_NR,
238 .label = "GPX3",
239 .to_irq = samsung_gpiolib_to_irq,
240 },
241 },
242};
243
244static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
245 {
246 .chip = {
247 .base = S5PV310_GPZ(0),
248 .ngpio = S5PV310_GPIO_Z_NR,
249 .label = "GPZ",
250 },
251 },
252};
253
254static __init int s5pv310_gpiolib_init(void)
255{
256 struct s3c_gpio_chip *chip;
257 int i;
258 int nr_chips;
259
260 /* GPIO part 1 */
261
262 chip = s5pv310_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
264
265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL)
267 chip->config = &gpio_cfg;
268 if (chip->base == NULL)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
270 }
271
272 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
273
274 /* GPIO part 2 */
275
276 chip = s5pv310_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
278
279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL)
281 chip->config = &gpio_cfg;
282 if (chip->base == NULL)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
284 }
285
286 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
287
288 /* GPIO part 3 */
289
290 chip = s5pv310_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
292
293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL)
295 chip->config = &gpio_cfg;
296 if (chip->base == NULL)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
298 }
299
300 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
301
302 return 0;
303}
304core_initcall(s5pv310_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-s5pv310/headsmp.S
deleted file mode 100644
index 164b7b045713..000000000000
--- a/arch/arm/mach-s5pv310/headsmp.S
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/headsmp.S
3 *
4 * Cloned from linux/arch/arm/mach-realview/headsmp.S
5 *
6 * Copyright (c) 2003 ARM Limited
7 * All Rights Reserved
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15
16 __INIT
17
18/*
19 * s5pv310 specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise.
22 */
23ENTRY(s5pv310_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15
26 adr r4, 1f
27 ldmia r4, {r5, r6}
28 sub r4, r4, r5
29 add r6, r6, r4
30pen: ldr r7, [r6]
31 cmp r7, r0
32 bne pen
33
34 /*
35 * we've been released from the holding pen: secondary_stack
36 * should now contain the SVC stack for this core
37 */
38 b secondary_startup
39
401: .long .
41 .long pen_release
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c
deleted file mode 100644
index c24235c89eed..000000000000
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux arch/arm/mach-s5pv310/hotplug.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/smp.h>
16
17#include <asm/cacheflush.h>
18
19extern volatile int pen_release;
20
21static inline void cpu_enter_lowpower(void)
22{
23 unsigned int v;
24
25 flush_cache_all();
26 asm volatile(
27 " mcr p15, 0, %1, c7, c5, 0\n"
28 " mcr p15, 0, %1, c7, c10, 4\n"
29 /*
30 * Turn off coherency
31 */
32 " mrc p15, 0, %0, c1, c0, 1\n"
33 " bic %0, %0, #0x20\n"
34 " mcr p15, 0, %0, c1, c0, 1\n"
35 " mrc p15, 0, %0, c1, c0, 0\n"
36 " bic %0, %0, %2\n"
37 " mcr p15, 0, %0, c1, c0, 0\n"
38 : "=&r" (v)
39 : "r" (0), "Ir" (CR_C)
40 : "cc");
41}
42
43static inline void cpu_leave_lowpower(void)
44{
45 unsigned int v;
46
47 asm volatile(
48 "mrc p15, 0, %0, c1, c0, 0\n"
49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x20\n"
53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v)
55 : "Ir" (CR_C)
56 : "cc");
57}
58
59static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
60{
61 /*
62 * there is no power-control hardware on this platform, so all
63 * we can do is put the core into WFI; this is safe as the calling
64 * code will have already disabled interrupts
65 */
66 for (;;) {
67 /*
68 * here's the WFI
69 */
70 asm(".word 0xe320f003\n"
71 :
72 :
73 : "memory", "cc");
74
75 if (pen_release == cpu) {
76 /*
77 * OK, proper wakeup, we're done
78 */
79 break;
80 }
81
82 /*
83 * Getting here, means that we have come out of WFI without
84 * having been woken up - this shouldn't happen
85 *
86 * Just note it happening - when we're woken, we can report
87 * its occurrence.
88 */
89 (*spurious)++;
90 }
91}
92
93int platform_cpu_kill(unsigned int cpu)
94{
95 return 1;
96}
97
98/*
99 * platform-specific code to shutdown a CPU
100 *
101 * Called with IRQs disabled
102 */
103void platform_cpu_die(unsigned int cpu)
104{
105 int spurious = 0;
106
107 /*
108 * we're ready for shutdown now, so do it
109 */
110 cpu_enter_lowpower();
111 platform_do_lowpower(cpu, &spurious);
112
113 /*
114 * bring this CPU back into the world of cache
115 * coherency, and then restore interrupts
116 */
117 cpu_leave_lowpower();
118
119 if (spurious)
120 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
121}
122
123int platform_cpu_disable(unsigned int cpu)
124{
125 /*
126 * we don't allow CPU 0 to be shutdown (it is still too special
127 * e.g. clock tick interrupts)
128 */
129 return cpu == 0 ? -EPERM : 0;
130}
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
deleted file mode 100644
index b0d920c474d3..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16
17 /* note, for the boot process to work we have to keep the UART
18 * virtual address aligned to an 1MiB boundary for the L1
19 * mapping the head code makes. We keep the UART virtual address
20 * aligned and add in the offset when we load the value here.
21 */
22
23 .macro addruart, rp, rv
24 ldreq \rp, = S3C_PA_UART
25 ldrne \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32#define fifo_full fifo_full_s5pv210
33#define fifo_level fifo_level_s5pv210
34
35#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-s5pv310/include/mach/dma.h
deleted file mode 100644
index 81209eb1409b..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-s5pv310/include/mach/entry-macro.S
deleted file mode 100644
index e600e1d522df..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/entry-macro.S
+++ /dev/null
@@ -1,84 +0,0 @@
1/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 *
5 * Low-level IRQ helper macros for S5PV310 platforms
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10*/
11
12#include <mach/hardware.h>
13#include <asm/hardware/gic.h>
14
15 .macro disable_fiq
16 .endm
17
18 .macro get_irqnr_preamble, base, tmp
19 ldr \base, =gic_cpu_base_addr
20 ldr \base, [\base]
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 /*
27 * The interrupt numbering scheme is defined in the
28 * interrupt controller spec. To wit:
29 *
30 * Interrupts 0-15 are IPI
31 * 16-28 are reserved
32 * 29-31 are local. We allow 30 to be used for the watchdog.
33 * 32-1020 are global
34 * 1021-1022 are reserved
35 * 1023 is "spurious" (no interrupt)
36 *
37 * For now, we ignore all local interrupts so only return an interrupt if it's
38 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
39 *
40 * A simple read from the controller will tell us the number of the highest
41 * priority enabled interrupt. We then just need to check whether it is in the
42 * valid range for an IRQ (30-1020 inclusive).
43 */
44
45 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
46
47 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
48
49 ldr \tmp, =1021
50
51 bic \irqnr, \irqstat, #0x1c00
52
53 cmp \irqnr, #29
54 cmpcc \irqnr, \irqnr
55 cmpne \irqnr, \tmp
56 cmpcs \irqnr, \irqnr
57 addne \irqnr, \irqnr, #32
58
59 .endm
60
61 /* We assume that irqstat (the raw value of the IRQ acknowledge
62 * register) is preserved from the macro above.
63 * If there is an IPI, we immediately signal end of interrupt on the
64 * controller, since this requires the original irqstat value which
65 * we won't easily be able to recreate later.
66 */
67
68 .macro test_for_ipi, irqnr, irqstat, base, tmp
69 bic \irqnr, \irqstat, #0x1c00
70 cmp \irqnr, #16
71 strcc \irqstat, [\base, #GIC_CPU_EOI]
72 cmpcs \irqnr, \irqnr
73 .endm
74
75 /* As above, this assumes that irqstat and base are preserved.. */
76
77 .macro test_for_ltirq, irqnr, irqstat, base, tmp
78 bic \irqnr, \irqstat, #0x1c00
79 mov \tmp, #0
80 cmp \irqnr, #29
81 moveq \tmp, #1
82 streq \irqstat, [\base, #GIC_CPU_EOI]
83 cmp \tmp, #0
84 .endm
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
deleted file mode 100644
index 20cb80c23466..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/gpio.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define S5PV310_GPIO_A0_NR (8)
25#define S5PV310_GPIO_A1_NR (6)
26#define S5PV310_GPIO_B_NR (8)
27#define S5PV310_GPIO_C0_NR (5)
28#define S5PV310_GPIO_C1_NR (5)
29#define S5PV310_GPIO_D0_NR (4)
30#define S5PV310_GPIO_D1_NR (4)
31#define S5PV310_GPIO_E0_NR (5)
32#define S5PV310_GPIO_E1_NR (8)
33#define S5PV310_GPIO_E2_NR (6)
34#define S5PV310_GPIO_E3_NR (8)
35#define S5PV310_GPIO_E4_NR (8)
36#define S5PV310_GPIO_F0_NR (8)
37#define S5PV310_GPIO_F1_NR (8)
38#define S5PV310_GPIO_F2_NR (8)
39#define S5PV310_GPIO_F3_NR (6)
40#define S5PV310_GPIO_J0_NR (8)
41#define S5PV310_GPIO_J1_NR (5)
42#define S5PV310_GPIO_K0_NR (7)
43#define S5PV310_GPIO_K1_NR (7)
44#define S5PV310_GPIO_K2_NR (7)
45#define S5PV310_GPIO_K3_NR (7)
46#define S5PV310_GPIO_L0_NR (8)
47#define S5PV310_GPIO_L1_NR (3)
48#define S5PV310_GPIO_L2_NR (8)
49#define S5PV310_GPIO_X0_NR (8)
50#define S5PV310_GPIO_X1_NR (8)
51#define S5PV310_GPIO_X2_NR (8)
52#define S5PV310_GPIO_X3_NR (8)
53#define S5PV310_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define S5PV310_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 S5PV310_GPIO_A0_START = 0,
62 S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
63 S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
64 S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
65 S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
66 S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
67 S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
68 S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
69 S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
70 S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
71 S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
72 S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
73 S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
74 S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
75 S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
76 S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
77 S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
78 S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
79 S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
80 S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
81 S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
82 S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
83 S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
84 S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
85 S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
86 S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
87 S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
88 S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
89 S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
90 S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
91};
92
93/* S5PV310 GPIO number definitions */
94#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
95#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
96#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
97#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
98#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
99#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
100#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
101#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
102#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
103#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
104#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
105#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
106#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
107#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
108#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
109#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
110#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
111#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
112#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
113#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
114#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
115#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
116#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
117#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
118#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
119#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
120#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
121#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
122#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
123#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
124
125/* the end of the S5PV310 specific gpios */
126#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END S5PV310_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-s5pv310/include/mach/hardware.h
deleted file mode 100644
index 28ff9881f1a6..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-s5pv310/include/mach/io.h
deleted file mode 100644
index 8a7f9128391f..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/io.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6442/include/mach/io.h
9 *
10 * Default IO routines for S5PV310
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#ifndef __ASM_ARM_ARCH_IO_H
18#define __ASM_ARM_ARCH_IO_H __FILE__
19
20/* No current ISA/PCI bus support. */
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23
24#define IO_SPACE_LIMIT (0xFFFFFFFF)
25
26#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
deleted file mode 100644
index 901657fa7a12..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define S5PV310_PA_SYSRAM 0x02025000
27
28#define S5PV310_PA_I2S0 0x03830000
29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PV310_PA_I2S2 0xE2A00000
31
32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
35
36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
40
41#define S5PV310_PA_CHIPID 0x10000000
42
43#define S5PV310_PA_SYSCON 0x10010000
44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
46
47#define S5PV310_PA_WATCHDOG 0x10060000
48#define S5PV310_PA_RTC 0x10070000
49
50#define S5PV310_PA_DMC0 0x10400000
51
52#define S5PV310_PA_COMBINER 0x10448000
53
54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
59
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
66#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
67#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
68#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
69#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
70#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
71#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
72#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
73#define S5PV310_PA_SYSMMU_PCIe 0x12620000
74#define S5PV310_PA_SYSMMU_G2D 0x12A20000
75#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
76#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
77#define S5PV310_PA_SYSMMU_TV 0x12E20000
78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
80
81#define S5PV310_PA_GPIO1 0x11400000
82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
109#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
110#define S3C_PA_IIC S5PV310_PA_IIC(0)
111#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
112#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
113#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
114#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
115#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
116#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
118#define S3C_PA_RTC S5PV310_PA_RTC
119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
143
144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h
deleted file mode 100644
index 1dffb4823245..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H __FILE__
15
16#define PHYS_OFFSET UL(0x40000000)
17
18/* Maximum of 256MiB in one bank */
19#define MAX_PHYSMEM_BITS 32
20#define SECTION_SIZE_BITS 28
21
22#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
deleted file mode 100644
index 82e9e0c9d452..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
21
22#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
24
25#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
27
28#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) S5PV310_GPX0(x)
38#define EINT_GPIO_1(x) S5PV310_GPX1(x)
39#define EINT_GPIO_2(x) S5PV310_GPX2(x)
40#define EINT_GPIO_3(x) S5PV310_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
deleted file mode 100644
index 834227140eaa..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC and DMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MEM_H
14#define __ASM_ARCH_REGS_MEM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_DMC0_MEMCON_OFFSET 0x04
19
20#define S5P_DMC0_MEMTYPE_SHIFT 8
21#define S5P_DMC0_MEMTYPE_MASK 0xF
22
23#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
deleted file mode 100644
index fb333d0f6073..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
25#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
26#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
27
28#define S5P_INT_LOCAL_PWR_EN 0x7
29
30#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
deleted file mode 100644
index 0b28e81a16f7..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - System MMU register
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SYSMMU_H
14#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
15
16#define S5P_MMU_CTRL 0x000
17#define S5P_MMU_CFG 0x004
18#define S5P_MMU_STATUS 0x008
19#define S5P_MMU_FLUSH 0x00C
20#define S5P_PT_BASE_ADDR 0x014
21#define S5P_INT_STATUS 0x018
22#define S5P_PAGE_FAULT_ADDR 0x024
23
24#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
deleted file mode 100644
index 393ccbd52c4a..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/smp.h
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/
5
6#ifndef ASM_ARCH_SMP_H
7#define ASM_ARCH_SMP_H __FILE__
8
9#include <asm/hardware/gic.h>
10
11/*
12 * We use IRQ1 as the IPI
13 */
14static inline void smp_cross_call(const struct cpumask *mask, int ipi)
15{
16 gic_raise_softirq(mask, ipi);
17}
18
19#endif
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
deleted file mode 100644
index 598fc5c9211b..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Samsung sysmmu driver for S5PV310
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15
16#define S5PV310_SYSMMU_TOTAL_IPNUM 16
17#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
18
19enum s5pv310_sysmmu_ips {
20 SYSMMU_MDMA,
21 SYSMMU_SSS,
22 SYSMMU_FIMC0,
23 SYSMMU_FIMC1,
24 SYSMMU_FIMC2,
25 SYSMMU_FIMC3,
26 SYSMMU_JPEG,
27 SYSMMU_FIMD0,
28 SYSMMU_FIMD1,
29 SYSMMU_PCIe,
30 SYSMMU_G2D,
31 SYSMMU_ROTATOR,
32 SYSMMU_MDMA2,
33 SYSMMU_TV,
34 SYSMMU_MFC_L,
35 SYSMMU_MFC_R,
36};
37
38static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
39 "SYSMMU_MDMA" ,
40 "SYSMMU_SSS" ,
41 "SYSMMU_FIMC0" ,
42 "SYSMMU_FIMC1" ,
43 "SYSMMU_FIMC2" ,
44 "SYSMMU_FIMC3" ,
45 "SYSMMU_JPEG" ,
46 "SYSMMU_FIMD0" ,
47 "SYSMMU_FIMD1" ,
48 "SYSMMU_PCIe" ,
49 "SYSMMU_G2D" ,
50 "SYSMMU_ROTATOR",
51 "SYSMMU_MDMA2" ,
52 "SYSMMU_TV" ,
53 "SYSMMU_MFC_L" ,
54 "SYSMMU_MFC_R" ,
55};
56
57typedef enum s5pv310_sysmmu_ips sysmmu_ips;
58
59struct sysmmu_tt_info {
60 unsigned long *pgd;
61 unsigned long pgd_paddr;
62 unsigned long *pte;
63};
64
65struct sysmmu_controller {
66 const char *name;
67
68 /* channels registers */
69 void __iomem *regs;
70
71 /* channel irq */
72 unsigned int irq;
73
74 sysmmu_ips ips;
75
76 /* Translation Table Info. */
77 struct sysmmu_tt_info *tt_info;
78
79 struct resource *mem;
80 struct device *dev;
81
82 /* SysMMU controller enable - true : enable */
83 bool enable;
84};
85
86/**
87 * s5p_sysmmu_enable() - enable system mmu of ip
88 * @ips: The ip connected system mmu.
89 *
90 * This function enable system mmu to transfer address
91 * from virtual address to physical address
92 */
93int s5p_sysmmu_enable(sysmmu_ips ips);
94
95/**
96 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
97 * @ips: The ip connected system mmu.
98 *
99 * This function disable system mmu to transfer address
100 * from virtual address to physical address
101 */
102int s5p_sysmmu_disable(sysmmu_ips ips);
103
104/**
105 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
106 * @ips: The ip connected system mmu.
107 * @pgd: The page table base address.
108 *
109 * This function set page table base address
110 * When system mmu transfer address from virtaul address to physical address,
111 * system mmu refer address information from page table
112 */
113int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
114
115/**
116 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
117 * @ips: The ip connected system mmu.
118 *
119 * This function flush all TLB entry in system mmu
120 */
121int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
122#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-s5pv310/include/mach/system.h
deleted file mode 100644
index d10c009cf0f1..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/system.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/system.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16#include <plat/system-reset.h>
17
18static void arch_idle(void)
19{
20 /* nothing here yet */
21}
22#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-s5pv310/include/mach/timex.h
deleted file mode 100644
index bd2359b952b4..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/timex.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/timex.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright (c) 2003-2010 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h
10 *
11 * S5PV310 - time parameters
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_ARCH_TIMEX_H
19#define __ASM_ARCH_TIMEX_H __FILE__
20
21/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
22 * a variable is useless. It seems as long as we make our timers an
23 * exact multiple of HZ, any value that makes a 1->1 correspondence
24 * for the time conversion functions to/from jiffies is acceptable.
25*/
26
27#define CLOCK_TICK_RATE 12000000
28
29#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-s5pv310/include/mach/uncompress.h
deleted file mode 100644
index 59593c1e2416..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/uncompress.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22
23 /*
24 * For preventing FIFO overrun or infinite loop of UART console,
25 * fifo_max should be the minimum fifo size of all of the UART channels
26 */
27 fifo_mask = S5PV210_UFSTAT_TXMASK;
28 fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
29}
30#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
deleted file mode 100644
index 65759fb97581..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * S5PV310 vmalloc definition
15*/
16
17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__
19
20#define VMALLOC_END 0xF6000000UL
21
22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-s5pv310/init.c
deleted file mode 100644
index 182dcf42cfb4..000000000000
--- a/arch/arm/mach-s5pv310/init.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12
13#include <plat/cpu.h>
14#include <plat/devs.h>
15#include <plat/regs-serial.h>
16
17static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
18 [0] = {
19 .name = "uclk1",
20 .divisor = 1,
21 .min_baud = 0,
22 .max_baud = 0,
23 },
24};
25
26/* uart registration process */
27void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{
29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt;
31
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1;
35 tcfg->clocks = s5pv310_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks);
37 }
38 }
39
40 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
41}
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
deleted file mode 100644
index 34093b069f67..000000000000
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ /dev/null
@@ -1,172 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/platsmp.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 *
8 * Copyright (C) 2002 ARM Ltd.
9 * All Rights Reserved
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <linux/jiffies.h>
21#include <linux/smp.h>
22#include <linux/io.h>
23
24#include <asm/cacheflush.h>
25#include <asm/smp_scu.h>
26#include <asm/unified.h>
27
28#include <mach/hardware.h>
29#include <mach/regs-clock.h>
30
31extern void s5pv310_secondary_startup(void);
32
33/*
34 * control for which core is the next to come out of the secondary
35 * boot "holding pen"
36 */
37
38volatile int __cpuinitdata pen_release = -1;
39
40/*
41 * Write pen_release in a way that is guaranteed to be visible to all
42 * observers, irrespective of whether they're taking part in coherency
43 * or not. This is necessary for the hotplug code to work reliably.
44 */
45static void write_pen_release(int val)
46{
47 pen_release = val;
48 smp_wmb();
49 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
50 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
51}
52
53static void __iomem *scu_base_addr(void)
54{
55 return (void __iomem *)(S5P_VA_SCU);
56}
57
58static DEFINE_SPINLOCK(boot_lock);
59
60void __cpuinit platform_secondary_init(unsigned int cpu)
61{
62 /*
63 * if any interrupts are already enabled for the primary
64 * core (e.g. timer irq), then they will not have been enabled
65 * for us: do so
66 */
67 gic_secondary_init(0);
68
69 /*
70 * let the primary processor know we're out of the
71 * pen, then head off into the C entry point
72 */
73 write_pen_release(-1);
74
75 /*
76 * Synchronise with the boot thread.
77 */
78 spin_lock(&boot_lock);
79 spin_unlock(&boot_lock);
80}
81
82int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
83{
84 unsigned long timeout;
85
86 /*
87 * Set synchronisation state between this boot processor
88 * and the secondary one
89 */
90 spin_lock(&boot_lock);
91
92 /*
93 * The secondary processor is waiting to be released from
94 * the holding pen - release it, then wait for it to flag
95 * that it has been released by resetting pen_release.
96 *
97 * Note that "pen_release" is the hardware CPU ID, whereas
98 * "cpu" is Linux's internal ID.
99 */
100 write_pen_release(cpu);
101
102 /*
103 * Send the secondary CPU a soft interrupt, thereby causing
104 * the boot monitor to read the system wide flags register,
105 * and branch to the address found there.
106 */
107 smp_cross_call(cpumask_of(cpu), 1);
108
109 timeout = jiffies + (1 * HZ);
110 while (time_before(jiffies, timeout)) {
111 smp_rmb();
112 if (pen_release == -1)
113 break;
114
115 udelay(10);
116 }
117
118 /*
119 * now the secondary core is starting up let it run its
120 * calibrations, then wait for it to finish
121 */
122 spin_unlock(&boot_lock);
123
124 return pen_release != -1 ? -ENOSYS : 0;
125}
126
127/*
128 * Initialise the CPU possible map early - this describes the CPUs
129 * which may be present or become present in the system.
130 */
131
132void __init smp_init_cpus(void)
133{
134 void __iomem *scu_base = scu_base_addr();
135 unsigned int i, ncores;
136
137 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
138
139 /* sanity check */
140 if (ncores > NR_CPUS) {
141 printk(KERN_WARNING
142 "S5PV310: no. of cores (%d) greater than configured "
143 "maximum of %d - clipping\n",
144 ncores, NR_CPUS);
145 ncores = NR_CPUS;
146 }
147
148 for (i = 0; i < ncores; i++)
149 set_cpu_possible(i, true);
150}
151
152void __init platform_smp_prepare_cpus(unsigned int max_cpus)
153{
154 int i;
155
156 /*
157 * Initialise the present map, which describes the set of CPUs
158 * actually populated at the present time.
159 */
160 for (i = 0; i < max_cpus; i++)
161 set_cpu_present(i, true);
162
163 scu_enable(scu_base_addr());
164
165 /*
166 * Write the address of secondary startup into the
167 * system-wide flags register. The boot monitor waits
168 * until it receives a soft interrupt, and then the
169 * secondary CPU branches to this address.
170 */
171 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
172}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c
deleted file mode 100644
index f47f8f3152ec..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c0.c
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * I2C0 GPIO configuration.
8 *
9 * Based on plat-s3c64xx/setup-i2c0.c
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16struct platform_device; /* don't need the contents */
17
18#include <linux/gpio.h>
19#include <plat/iic.h>
20#include <plat/gpio-cfg.h>
21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{
24 s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 15:24:42 -0500