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authorKukjin Kim <kgene.kim@samsung.com>2010-08-18 09:03:19 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-20 18:52:15 -0400
commita6aa7a55848ff84b2f296ad30726f0e1ebc5f0ea (patch)
tree90ab945de2122557b7320a92be1450c8d9ee831a /arch/arm/mach-s5pv310
parente33ed879f02182b01a601ae3de70acd536c894c2 (diff)
ARM: S5PV310: Removed unused clock
This pach removed unused clock on S5PV310/S5PC210. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv310')
-rw-r--r--arch/arm/mach-s5pv310/clock.c46
1 files changed, 2 insertions, 44 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 26a0f03df8ea..823c29f68067 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -150,24 +150,6 @@ static struct clksrc_clk clk_periphclk = {
150 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 150 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
151}; 151};
152 152
153static struct clksrc_clk clk_atclk = {
154 .clk = {
155 .name = "atclk",
156 .id = -1,
157 .parent = &clk_moutcore.clk,
158 },
159 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
160};
161
162static struct clksrc_clk clk_pclk_dbg = {
163 .clk = {
164 .name = "pclk_dbg",
165 .id = -1,
166 .parent = &clk_atclk.clk,
167 },
168 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
169};
170
171/* Core list of CMU_CORE side */ 153/* Core list of CMU_CORE side */
172 154
173static struct clk *clkset_corebus_list[] = { 155static struct clk *clkset_corebus_list[] = {
@@ -464,8 +446,6 @@ static struct clksrc_clk *sysclks[] = {
464 &clk_aclk_cores, 446 &clk_aclk_cores,
465 &clk_aclk_corem1, 447 &clk_aclk_corem1,
466 &clk_periphclk, 448 &clk_periphclk,
467 &clk_atclk,
468 &clk_pclk_dbg,
469 &clk_mout_corebus, 449 &clk_mout_corebus,
470 &clk_sclk_dmc, 450 &clk_sclk_dmc,
471 &clk_aclk_cored, 451 &clk_aclk_cored,
@@ -490,15 +470,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
490 unsigned long vpllsrc; 470 unsigned long vpllsrc;
491 unsigned long xtal; 471 unsigned long xtal;
492 unsigned long armclk; 472 unsigned long armclk;
493 unsigned long aclk_corem0;
494 unsigned long aclk_cores;
495 unsigned long aclk_corem1;
496 unsigned long periphclk;
497 unsigned long sclk_dmc; 473 unsigned long sclk_dmc;
498 unsigned long aclk_cored;
499 unsigned long aclk_corep;
500 unsigned long aclk_acp;
501 unsigned long pclk_acp;
502 unsigned int ptr; 474 unsigned int ptr;
503 475
504 printk(KERN_DEBUG "%s: registering clocks\n", __func__); 476 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
@@ -529,26 +501,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
529 apll, mpll, epll, vpll); 501 apll, mpll, epll, vpll);
530 502
531 armclk = clk_get_rate(&clk_armclk.clk); 503 armclk = clk_get_rate(&clk_armclk.clk);
532 aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
533 aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
534 aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
535 periphclk = clk_get_rate(&clk_periphclk.clk);
536 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); 504 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
537 aclk_cored = clk_get_rate(&clk_aclk_cored.clk); 505
538 aclk_corep = clk_get_rate(&clk_aclk_corep.clk); 506 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc);
539 aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
540 pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
541
542 printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
543 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
544 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
545 armclk, aclk_corem0, aclk_cores, aclk_corem1,
546 periphclk, sclk_dmc, aclk_cored, aclk_corep,
547 aclk_acp, pclk_acp);
548 507
549 clk_f.rate = armclk; 508 clk_f.rate = armclk;
550 clk_h.rate = sclk_dmc; 509 clk_h.rate = sclk_dmc;
551 clk_p.rate = periphclk;
552 510
553 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 511 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
554 s3c_set_clksrc(&clksrcs[ptr], true); 512 s3c_set_clksrc(&clksrcs[ptr], true);