diff options
author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2011-03-10 07:53:40 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-03-11 01:49:01 -0500 |
commit | 1d45ac49daa15fd0a64c58744ac9ea6451e607e6 (patch) | |
tree | 8db8bb0dd987dfd3c4a166893040de29ba9482e9 /arch/arm/mach-s5pv210 | |
parent | e24d208de6bc779c6bd97523cde2665a33f2be4d (diff) |
ARM: S5P: Add support for common MIPI CSIS/DSIM D-PHY control
Add common code for MIPI-CSIS and MIPI-DSIM drivers to support
their corresponding D-PHY's enable and reset control.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/regs-clock.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 4c45b74def5f..78925c516346 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h | |||
@@ -146,6 +146,10 @@ | |||
146 | #define S5P_OM_STAT S5P_CLKREG(0xE100) | 146 | #define S5P_OM_STAT S5P_CLKREG(0xE100) |
147 | #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) | 147 | #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) |
148 | #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) | 148 | #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) |
149 | #define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) | ||
150 | #define S5P_MIPI_DPHY_ENABLE (1 << 0) | ||
151 | #define S5P_MIPI_DPHY_SRESETN (1 << 1) | ||
152 | #define S5P_MIPI_DPHY_MRESETN (1 << 2) | ||
149 | 153 | ||
150 | #define S5P_INFORM0 S5P_CLKREG(0xF000) | 154 | #define S5P_INFORM0 S5P_CLKREG(0xF000) |
151 | #define S5P_INFORM1 S5P_CLKREG(0xF004) | 155 | #define S5P_INFORM1 S5P_CLKREG(0xF004) |
@@ -161,7 +165,6 @@ | |||
161 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) | 165 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) |
162 | #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) | 166 | #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) |
163 | #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) | 167 | #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) |
164 | #define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814) | ||
165 | 168 | ||
166 | #define S5P_IDLE_CFG_TL_MASK (3 << 30) | 169 | #define S5P_IDLE_CFG_TL_MASK (3 << 30) |
167 | #define S5P_IDLE_CFG_TM_MASK (3 << 28) | 170 | #define S5P_IDLE_CFG_TM_MASK (3 << 28) |