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authorKukjin Kim <kgene.kim@samsung.com>2011-10-04 07:18:36 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 07:18:36 -0400
commitdb3c94a7edc6b29f8d52ba5884dec6a15feeadad (patch)
treeac9207a44cecafb9104ca4e1f46aecb9fe01383d /arch/arm/mach-s5pv210
parentc9477f38cba225870862fd9e08868ae3d4abdfe0 (diff)
parent568f0e278c6dd33dc11bd19c4ad781d1f8d86800 (diff)
Merge branch 'next-samsung-devel' into next-samsung-devel-2
Conflicts: arch/arm/mach-exynos4/clock.c arch/arm/mach-s3c2412/gpio.c arch/arm/mach-s5p64x0/dma.c arch/arm/mach-s5p64x0/gpiolib.c
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/Kconfig4
-rw-r--r--arch/arm/mach-s5pv210/clock.c151
-rw-r--r--arch/arm/mach-s5pv210/cpu.c4
-rw-r--r--arch/arm/mach-s5pv210/dma.c317
-rw-r--r--arch/arm/mach-s5pv210/include/mach/dma.h4
-rw-r--r--arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h16
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h13
-rw-r--r--arch/arm/mach-s5pv210/include/mach/pm-core.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h3
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c62
11 files changed, 446 insertions, 134 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index aaeb44a73716..f22c683272d3 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -11,7 +11,7 @@ if ARCH_S5PV210
11 11
12config CPU_S5PV210 12config CPU_S5PV210
13 bool 13 bool
14 select S3C_PL330_DMA 14 select SAMSUNG_DMADEV
15 select S5P_EXT_INT 15 select S5P_EXT_INT
16 select S5P_HRT 16 select S5P_HRT
17 help 17 help
@@ -93,11 +93,13 @@ config MACH_GONI
93 select S3C_DEV_USB_HSOTG 93 select S3C_DEV_USB_HSOTG
94 select S5P_DEV_ONENAND 94 select S5P_DEV_ONENAND
95 select SAMSUNG_DEV_KEYPAD 95 select SAMSUNG_DEV_KEYPAD
96 select S5P_DEV_TV
96 select S5PV210_SETUP_FB_24BPP 97 select S5PV210_SETUP_FB_24BPP
97 select S5PV210_SETUP_I2C1 98 select S5PV210_SETUP_I2C1
98 select S5PV210_SETUP_I2C2 99 select S5PV210_SETUP_I2C2
99 select S5PV210_SETUP_KEYPAD 100 select S5PV210_SETUP_KEYPAD
100 select S5PV210_SETUP_SDHCI 101 select S5PV210_SETUP_SDHCI
102 select S5PV210_SETUP_FIMC
101 help 103 help
102 Machine support for Samsung GONI board 104 Machine support for Samsung GONI board
103 S5PC110(MCP) is one of package option of S5PV210 105 S5PC110(MCP) is one of package option of S5PV210
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index f5f8fa89679c..4c5ac7a69e9e 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -174,6 +174,16 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
174 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); 174 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
175} 175}
176 176
177static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
178{
179 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
180}
181
182static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
183{
184 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
185}
186
177static struct clk clk_sclk_hdmi27m = { 187static struct clk clk_sclk_hdmi27m = {
178 .name = "sclk_hdmi27m", 188 .name = "sclk_hdmi27m",
179 .rate = 27000000, 189 .rate = 27000000,
@@ -203,6 +213,11 @@ static struct clk clk_pcmcdclk2 = {
203 .name = "pcmcdclk", 213 .name = "pcmcdclk",
204}; 214};
205 215
216static struct clk dummy_apb_pclk = {
217 .name = "apb_pclk",
218 .id = -1,
219};
220
206static struct clk *clkset_vpllsrc_list[] = { 221static struct clk *clkset_vpllsrc_list[] = {
207 [0] = &clk_fin_vpll, 222 [0] = &clk_fin_vpll,
208 [1] = &clk_sclk_hdmi27m, 223 [1] = &clk_sclk_hdmi27m,
@@ -289,14 +304,14 @@ static struct clk_ops clk_fout_apll_ops = {
289 304
290static struct clk init_clocks_off[] = { 305static struct clk init_clocks_off[] = {
291 { 306 {
292 .name = "pdma", 307 .name = "dma",
293 .devname = "s3c-pl330.0", 308 .devname = "dma-pl330.0",
294 .parent = &clk_hclk_psys.clk, 309 .parent = &clk_hclk_psys.clk,
295 .enable = s5pv210_clk_ip0_ctrl, 310 .enable = s5pv210_clk_ip0_ctrl,
296 .ctrlbit = (1 << 3), 311 .ctrlbit = (1 << 3),
297 }, { 312 }, {
298 .name = "pdma", 313 .name = "dma",
299 .devname = "s3c-pl330.1", 314 .devname = "dma-pl330.1",
300 .parent = &clk_hclk_psys.clk, 315 .parent = &clk_hclk_psys.clk,
301 .enable = s5pv210_clk_ip0_ctrl, 316 .enable = s5pv210_clk_ip0_ctrl,
302 .ctrlbit = (1 << 4), 317 .ctrlbit = (1 << 4),
@@ -330,6 +345,40 @@ static struct clk init_clocks_off[] = {
330 .enable = s5pv210_clk_ip0_ctrl, 345 .enable = s5pv210_clk_ip0_ctrl,
331 .ctrlbit = (1 << 16), 346 .ctrlbit = (1 << 16),
332 }, { 347 }, {
348 .name = "dac",
349 .devname = "s5p-sdo",
350 .parent = &clk_hclk_dsys.clk,
351 .enable = s5pv210_clk_ip1_ctrl,
352 .ctrlbit = (1 << 10),
353 }, {
354 .name = "mixer",
355 .devname = "s5p-mixer",
356 .parent = &clk_hclk_dsys.clk,
357 .enable = s5pv210_clk_ip1_ctrl,
358 .ctrlbit = (1 << 9),
359 }, {
360 .name = "vp",
361 .devname = "s5p-mixer",
362 .parent = &clk_hclk_dsys.clk,
363 .enable = s5pv210_clk_ip1_ctrl,
364 .ctrlbit = (1 << 8),
365 }, {
366 .name = "hdmi",
367 .devname = "s5pv210-hdmi",
368 .parent = &clk_hclk_dsys.clk,
369 .enable = s5pv210_clk_ip1_ctrl,
370 .ctrlbit = (1 << 11),
371 }, {
372 .name = "hdmiphy",
373 .devname = "s5pv210-hdmi",
374 .enable = exynos4_clk_hdmiphy_ctrl,
375 .ctrlbit = (1 << 0),
376 }, {
377 .name = "dacphy",
378 .devname = "s5p-sdo",
379 .enable = exynos4_clk_dac_ctrl,
380 .ctrlbit = (1 << 0),
381 }, {
333 .name = "otg", 382 .name = "otg",
334 .parent = &clk_hclk_psys.clk, 383 .parent = &clk_hclk_psys.clk,
335 .enable = s5pv210_clk_ip1_ctrl, 384 .enable = s5pv210_clk_ip1_ctrl,
@@ -407,6 +456,12 @@ static struct clk init_clocks_off[] = {
407 .enable = s5pv210_clk_ip3_ctrl, 456 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<9), 457 .ctrlbit = (1<<9),
409 }, { 458 }, {
459 .name = "i2c",
460 .devname = "s3c2440-hdmiphy-i2c",
461 .parent = &clk_pclk_psys.clk,
462 .enable = s5pv210_clk_ip3_ctrl,
463 .ctrlbit = (1 << 11),
464 }, {
410 .name = "spi", 465 .name = "spi",
411 .devname = "s3c64xx-spi.0", 466 .devname = "s3c64xx-spi.0",
412 .parent = &clk_pclk_psys.clk, 467 .parent = &clk_pclk_psys.clk,
@@ -594,6 +649,23 @@ static struct clksrc_sources clkset_sclk_mixer = {
594 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), 649 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
595}; 650};
596 651
652static struct clksrc_clk clk_sclk_mixer = {
653 .clk = {
654 .name = "sclk_mixer",
655 .enable = s5pv210_clk_mask0_ctrl,
656 .ctrlbit = (1 << 1),
657 },
658 .sources = &clkset_sclk_mixer,
659 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
660};
661
662static struct clksrc_clk *sclk_tv[] = {
663 &clk_sclk_dac,
664 &clk_sclk_pixel,
665 &clk_sclk_hdmi,
666 &clk_sclk_mixer,
667};
668
597static struct clk *clkset_sclk_audio0_list[] = { 669static struct clk *clkset_sclk_audio0_list[] = {
598 [0] = &clk_ext_xtal_mux, 670 [0] = &clk_ext_xtal_mux,
599 [1] = &clk_pcmcdclk0, 671 [1] = &clk_pcmcdclk0,
@@ -777,14 +849,6 @@ static struct clksrc_clk clksrcs[] = {
777 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, 849 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
778 }, { 850 }, {
779 .clk = { 851 .clk = {
780 .name = "sclk_mixer",
781 .enable = s5pv210_clk_mask0_ctrl,
782 .ctrlbit = (1 << 1),
783 },
784 .sources = &clkset_sclk_mixer,
785 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
786 }, {
787 .clk = {
788 .name = "sclk_fimc", 852 .name = "sclk_fimc",
789 .devname = "s5pv210-fimc.0", 853 .devname = "s5pv210-fimc.0",
790 .enable = s5pv210_clk_mask1_ctrl, 854 .enable = s5pv210_clk_mask1_ctrl,
@@ -973,9 +1037,6 @@ static struct clksrc_clk *sysclks[] = {
973 &clk_pclk_psys, 1037 &clk_pclk_psys,
974 &clk_vpllsrc, 1038 &clk_vpllsrc,
975 &clk_sclk_vpll, 1039 &clk_sclk_vpll,
976 &clk_sclk_dac,
977 &clk_sclk_pixel,
978 &clk_sclk_hdmi,
979 &clk_mout_dmc0, 1040 &clk_mout_dmc0,
980 &clk_sclk_dmc0, 1041 &clk_sclk_dmc0,
981 &clk_sclk_audio0, 1042 &clk_sclk_audio0,
@@ -1060,6 +1121,61 @@ static struct clk_ops s5pv210_epll_ops = {
1060 .get_rate = s5p_epll_get_rate, 1121 .get_rate = s5p_epll_get_rate,
1061}; 1122};
1062 1123
1124static u32 vpll_div[][5] = {
1125 { 54000000, 3, 53, 3, 0 },
1126 { 108000000, 3, 53, 2, 0 },
1127};
1128
1129static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
1130{
1131 return clk->rate;
1132}
1133
1134static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
1135{
1136 unsigned int vpll_con;
1137 unsigned int i;
1138
1139 /* Return if nothing changed */
1140 if (clk->rate == rate)
1141 return 0;
1142
1143 vpll_con = __raw_readl(S5P_VPLL_CON);
1144 vpll_con &= ~(0x1 << 27 | \
1145 PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
1146 PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
1147 PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
1148
1149 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1150 if (vpll_div[i][0] == rate) {
1151 vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
1152 vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
1153 vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
1154 vpll_con |= vpll_div[i][4] << 27;
1155 break;
1156 }
1157 }
1158
1159 if (i == ARRAY_SIZE(vpll_div)) {
1160 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1161 __func__);
1162 return -EINVAL;
1163 }
1164
1165 __raw_writel(vpll_con, S5P_VPLL_CON);
1166
1167 /* Wait for VPLL lock */
1168 while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
1169 continue;
1170
1171 clk->rate = rate;
1172 return 0;
1173}
1174static struct clk_ops s5pv210_vpll_ops = {
1175 .get_rate = s5pv210_vpll_get_rate,
1176 .set_rate = s5pv210_vpll_set_rate,
1177};
1178
1063void __init_or_cpufreq s5pv210_setup_clocks(void) 1179void __init_or_cpufreq s5pv210_setup_clocks(void)
1064{ 1180{
1065 struct clk *xtal_clk; 1181 struct clk *xtal_clk;
@@ -1108,6 +1224,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
1108 clk_fout_apll.ops = &clk_fout_apll_ops; 1224 clk_fout_apll.ops = &clk_fout_apll_ops;
1109 clk_fout_mpll.rate = mpll; 1225 clk_fout_mpll.rate = mpll;
1110 clk_fout_epll.rate = epll; 1226 clk_fout_epll.rate = epll;
1227 clk_fout_vpll.ops = &s5pv210_vpll_ops;
1111 clk_fout_vpll.rate = vpll; 1228 clk_fout_vpll.rate = vpll;
1112 1229
1113 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", 1230 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1153,11 +1270,15 @@ void __init s5pv210_register_clocks(void)
1153 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 1270 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1154 s3c_register_clksrc(sysclks[ptr], 1); 1271 s3c_register_clksrc(sysclks[ptr], 1);
1155 1272
1273 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1274 s3c_register_clksrc(sclk_tv[ptr], 1);
1275
1156 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1276 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1157 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1277 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1158 1278
1159 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1279 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1160 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1280 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1161 1281
1282 s3c24xx_register_clock(&dummy_apb_pclk);
1162 s3c_pwmclk_init(); 1283 s3c_pwmclk_init();
1163} 1284}
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 79907ec78d43..6b8cdccbe931 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -41,6 +41,7 @@
41#include <plat/keypad-core.h> 41#include <plat/keypad-core.h>
42#include <plat/sdhci.h> 42#include <plat/sdhci.h>
43#include <plat/reset.h> 43#include <plat/reset.h>
44#include <plat/tv-core.h>
44 45
45/* Initial IO mappings */ 46/* Initial IO mappings */
46 47
@@ -143,6 +144,9 @@ void __init s5pv210_map_io(void)
143 144
144 /* Use s5pv210-keypad instead of samsung-keypad */ 145 /* Use s5pv210-keypad instead of samsung-keypad */
145 samsung_keypad_setname("s5pv210-keypad"); 146 samsung_keypad_setname("s5pv210-keypad");
147
148 /* setup TV devices */
149 s5p_hdmi_setname("s5pv210-hdmi");
146} 150}
147 151
148void __init s5pv210_init_clocks(int xtal) 152void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 497d3439a142..86b749c18b77 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -1,4 +1,8 @@
1/* 1/* linux/arch/arm/mach-s5pv210/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
4 * 8 *
@@ -17,151 +21,240 @@
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 22 */
19 23
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
22 27
28#include <asm/irq.h>
23#include <plat/devs.h> 29#include <plat/devs.h>
24#include <plat/irqs.h> 30#include <plat/irqs.h>
25 31
26#include <mach/map.h> 32#include <mach/map.h>
27#include <mach/irqs.h> 33#include <mach/irqs.h>
28 34#include <mach/dma.h>
29#include <plat/s3c-pl330-pdata.h>
30 35
31static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
32 37
33static struct resource s5pv210_pdma0_resource[] = { 38struct dma_pl330_peri pdma0_peri[28] = {
34 [0] = { 39 {
35 .start = S5PV210_PA_PDMA0, 40 .peri_id = (u8)DMACH_UART0_RX,
36 .end = S5PV210_PA_PDMA0 + SZ_4K, 41 .rqtype = DEVTOMEM,
37 .flags = IORESOURCE_MEM, 42 }, {
38 }, 43 .peri_id = (u8)DMACH_UART0_TX,
39 [1] = { 44 .rqtype = MEMTODEV,
40 .start = IRQ_PDMA0, 45 }, {
41 .end = IRQ_PDMA0, 46 .peri_id = (u8)DMACH_UART1_RX,
42 .flags = IORESOURCE_IRQ, 47 .rqtype = DEVTOMEM,
48 }, {
49 .peri_id = (u8)DMACH_UART1_TX,
50 .rqtype = MEMTODEV,
51 }, {
52 .peri_id = (u8)DMACH_UART2_RX,
53 .rqtype = DEVTOMEM,
54 }, {
55 .peri_id = (u8)DMACH_UART2_TX,
56 .rqtype = MEMTODEV,
57 }, {
58 .peri_id = (u8)DMACH_UART3_RX,
59 .rqtype = DEVTOMEM,
60 }, {
61 .peri_id = (u8)DMACH_UART3_TX,
62 .rqtype = MEMTODEV,
63 }, {
64 .peri_id = DMACH_MAX,
65 }, {
66 .peri_id = (u8)DMACH_I2S0_RX,
67 .rqtype = DEVTOMEM,
68 }, {
69 .peri_id = (u8)DMACH_I2S0_TX,
70 .rqtype = MEMTODEV,
71 }, {
72 .peri_id = (u8)DMACH_I2S0S_TX,
73 .rqtype = MEMTODEV,
74 }, {
75 .peri_id = (u8)DMACH_I2S1_RX,
76 .rqtype = DEVTOMEM,
77 }, {
78 .peri_id = (u8)DMACH_I2S1_TX,
79 .rqtype = MEMTODEV,
80 }, {
81 .peri_id = (u8)DMACH_MAX,
82 }, {
83 .peri_id = (u8)DMACH_MAX,
84 }, {
85 .peri_id = (u8)DMACH_SPI0_RX,
86 .rqtype = DEVTOMEM,
87 }, {
88 .peri_id = (u8)DMACH_SPI0_TX,
89 .rqtype = MEMTODEV,
90 }, {
91 .peri_id = (u8)DMACH_SPI1_RX,
92 .rqtype = DEVTOMEM,
93 }, {
94 .peri_id = (u8)DMACH_SPI1_TX,
95 .rqtype = MEMTODEV,
96 }, {
97 .peri_id = (u8)DMACH_MAX,
98 }, {
99 .peri_id = (u8)DMACH_MAX,
100 }, {
101 .peri_id = (u8)DMACH_AC97_MICIN,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_AC97_PCMIN,
105 .rqtype = DEVTOMEM,
106 }, {
107 .peri_id = (u8)DMACH_AC97_PCMOUT,
108 .rqtype = MEMTODEV,
109 }, {
110 .peri_id = (u8)DMACH_MAX,
111 }, {
112 .peri_id = (u8)DMACH_PWM,
113 }, {
114 .peri_id = (u8)DMACH_SPDIF,
115 .rqtype = MEMTODEV,
43 }, 116 },
44}; 117};
45 118
46static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { 119struct dma_pl330_platdata s5pv210_pdma0_pdata = {
47 .peri = { 120 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
48 [0] = DMACH_UART0_RX, 121 .peri = pdma0_peri,
49 [1] = DMACH_UART0_TX,
50 [2] = DMACH_UART1_RX,
51 [3] = DMACH_UART1_TX,
52 [4] = DMACH_UART2_RX,
53 [5] = DMACH_UART2_TX,
54 [6] = DMACH_UART3_RX,
55 [7] = DMACH_UART3_TX,
56 [8] = DMACH_MAX,
57 [9] = DMACH_I2S0_RX,
58 [10] = DMACH_I2S0_TX,
59 [11] = DMACH_I2S0S_TX,
60 [12] = DMACH_I2S1_RX,
61 [13] = DMACH_I2S1_TX,
62 [14] = DMACH_MAX,
63 [15] = DMACH_MAX,
64 [16] = DMACH_SPI0_RX,
65 [17] = DMACH_SPI0_TX,
66 [18] = DMACH_SPI1_RX,
67 [19] = DMACH_SPI1_TX,
68 [20] = DMACH_MAX,
69 [21] = DMACH_MAX,
70 [22] = DMACH_AC97_MICIN,
71 [23] = DMACH_AC97_PCMIN,
72 [24] = DMACH_AC97_PCMOUT,
73 [25] = DMACH_MAX,
74 [26] = DMACH_PWM,
75 [27] = DMACH_SPDIF,
76 [28] = DMACH_MAX,
77 [29] = DMACH_MAX,
78 [30] = DMACH_MAX,
79 [31] = DMACH_MAX,
80 },
81}; 122};
82 123
83static struct platform_device s5pv210_device_pdma0 = { 124struct amba_device s5pv210_device_pdma0 = {
84 .name = "s3c-pl330", 125 .dev = {
85 .id = 0, 126 .init_name = "dma-pl330.0",
86 .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource),
87 .resource = s5pv210_pdma0_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask, 127 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32), 128 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv210_pdma0_pdata, 129 .platform_data = &s5pv210_pdma0_pdata,
92 }, 130 },
93}; 131 .res = {
94 132 .start = S5PV210_PA_PDMA0,
95static struct resource s5pv210_pdma1_resource[] = { 133 .end = S5PV210_PA_PDMA0 + SZ_4K,
96 [0] = {
97 .start = S5PV210_PA_PDMA1,
98 .end = S5PV210_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM, 134 .flags = IORESOURCE_MEM,
100 }, 135 },
101 [1] = { 136 .irq = {IRQ_PDMA0, NO_IRQ},
102 .start = IRQ_PDMA1, 137 .periphid = 0x00041330,
103 .end = IRQ_PDMA1,
104 .flags = IORESOURCE_IRQ,
105 },
106}; 138};
107 139
108static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { 140struct dma_pl330_peri pdma1_peri[32] = {
109 .peri = { 141 {
110 [0] = DMACH_UART0_RX, 142 .peri_id = (u8)DMACH_UART0_RX,
111 [1] = DMACH_UART0_TX, 143 .rqtype = DEVTOMEM,
112 [2] = DMACH_UART1_RX, 144 }, {
113 [3] = DMACH_UART1_TX, 145 .peri_id = (u8)DMACH_UART0_TX,
114 [4] = DMACH_UART2_RX, 146 .rqtype = MEMTODEV,
115 [5] = DMACH_UART2_TX, 147 }, {
116 [6] = DMACH_UART3_RX, 148 .peri_id = (u8)DMACH_UART1_RX,
117 [7] = DMACH_UART3_TX, 149 .rqtype = DEVTOMEM,
118 [8] = DMACH_MAX, 150 }, {
119 [9] = DMACH_I2S0_RX, 151 .peri_id = (u8)DMACH_UART1_TX,
120 [10] = DMACH_I2S0_TX, 152 .rqtype = MEMTODEV,
121 [11] = DMACH_I2S0S_TX, 153 }, {
122 [12] = DMACH_I2S1_RX, 154 .peri_id = (u8)DMACH_UART2_RX,
123 [13] = DMACH_I2S1_TX, 155 .rqtype = DEVTOMEM,
124 [14] = DMACH_I2S2_RX, 156 }, {
125 [15] = DMACH_I2S2_TX, 157 .peri_id = (u8)DMACH_UART2_TX,
126 [16] = DMACH_SPI0_RX, 158 .rqtype = MEMTODEV,
127 [17] = DMACH_SPI0_TX, 159 }, {
128 [18] = DMACH_SPI1_RX, 160 .peri_id = (u8)DMACH_UART3_RX,
129 [19] = DMACH_SPI1_TX, 161 .rqtype = DEVTOMEM,
130 [20] = DMACH_MAX, 162 }, {
131 [21] = DMACH_MAX, 163 .peri_id = (u8)DMACH_UART3_TX,
132 [22] = DMACH_PCM0_RX, 164 .rqtype = MEMTODEV,
133 [23] = DMACH_PCM0_TX, 165 }, {
134 [24] = DMACH_PCM1_RX, 166 .peri_id = DMACH_MAX,
135 [25] = DMACH_PCM1_TX, 167 }, {
136 [26] = DMACH_MSM_REQ0, 168 .peri_id = (u8)DMACH_I2S0_RX,
137 [27] = DMACH_MSM_REQ1, 169 .rqtype = DEVTOMEM,
138 [28] = DMACH_MSM_REQ2, 170 }, {
139 [29] = DMACH_MSM_REQ3, 171 .peri_id = (u8)DMACH_I2S0_TX,
140 [30] = DMACH_PCM2_RX, 172 .rqtype = MEMTODEV,
141 [31] = DMACH_PCM2_TX, 173 }, {
174 .peri_id = (u8)DMACH_I2S0S_TX,
175 .rqtype = MEMTODEV,
176 }, {
177 .peri_id = (u8)DMACH_I2S1_RX,
178 .rqtype = DEVTOMEM,
179 }, {
180 .peri_id = (u8)DMACH_I2S1_TX,
181 .rqtype = MEMTODEV,
182 }, {
183 .peri_id = (u8)DMACH_I2S2_RX,
184 .rqtype = DEVTOMEM,
185 }, {
186 .peri_id = (u8)DMACH_I2S2_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_SPI0_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_SPI0_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_SPI1_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_SPI1_TX,
199 .rqtype = MEMTODEV,
200 }, {
201 .peri_id = (u8)DMACH_MAX,
202 }, {
203 .peri_id = (u8)DMACH_MAX,
204 }, {
205 .peri_id = (u8)DMACH_PCM0_RX,
206 .rqtype = DEVTOMEM,
207 }, {
208 .peri_id = (u8)DMACH_PCM0_TX,
209 .rqtype = MEMTODEV,
210 }, {
211 .peri_id = (u8)DMACH_PCM1_RX,
212 .rqtype = DEVTOMEM,
213 }, {
214 .peri_id = (u8)DMACH_PCM1_TX,
215 .rqtype = MEMTODEV,
216 }, {
217 .peri_id = (u8)DMACH_MSM_REQ0,
218 }, {
219 .peri_id = (u8)DMACH_MSM_REQ1,
220 }, {
221 .peri_id = (u8)DMACH_MSM_REQ2,
222 }, {
223 .peri_id = (u8)DMACH_MSM_REQ3,
224 }, {
225 .peri_id = (u8)DMACH_PCM2_RX,
226 .rqtype = DEVTOMEM,
227 }, {
228 .peri_id = (u8)DMACH_PCM2_TX,
229 .rqtype = MEMTODEV,
142 }, 230 },
143}; 231};
144 232
145static struct platform_device s5pv210_device_pdma1 = { 233struct dma_pl330_platdata s5pv210_pdma1_pdata = {
146 .name = "s3c-pl330", 234 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
147 .id = 1, 235 .peri = pdma1_peri,
148 .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), 236};
149 .resource = s5pv210_pdma1_resource, 237
150 .dev = { 238struct amba_device s5pv210_device_pdma1 = {
239 .dev = {
240 .init_name = "dma-pl330.1",
151 .dma_mask = &dma_dmamask, 241 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32), 242 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv210_pdma1_pdata, 243 .platform_data = &s5pv210_pdma1_pdata,
154 }, 244 },
155}; 245 .res = {
156 246 .start = S5PV210_PA_PDMA1,
157static struct platform_device *s5pv210_dmacs[] __initdata = { 247 .end = S5PV210_PA_PDMA1 + SZ_4K,
158 &s5pv210_device_pdma0, 248 .flags = IORESOURCE_MEM,
159 &s5pv210_device_pdma1, 249 },
250 .irq = {IRQ_PDMA1, NO_IRQ},
251 .periphid = 0x00041330,
160}; 252};
161 253
162static int __init s5pv210_dma_init(void) 254static int __init s5pv210_dma_init(void)
163{ 255{
164 platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs)); 256 amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
257 amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
165 258
166 return 0; 259 return 0;
167} 260}
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h
index 81209eb1409b..201842a3769e 100644
--- a/arch/arm/mach-s5pv210/include/mach/dma.h
+++ b/arch/arm/mach-s5pv210/include/mach/dma.h
@@ -20,7 +20,7 @@
20#ifndef __MACH_DMA_H 20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H 21#define __MACH_DMA_H
22 22
23/* This platform uses the common S3C DMA API driver for PL330 */ 23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h> 24#include <plat/dma-pl330.h>
25 25
26#endif /* __MACH_DMA_H */ 26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h b/arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h
new file mode 100644
index 000000000000..6afa6242c588
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series i2c hdmiphy helper definitions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef PLAT_S5P_I2C_HDMIPHY_H_
12#define PLAT_S5P_I2C_HDMIPHY_H_
13
14#define S5P_I2C_HDMIPHY_BUS_NUM (3)
15
16#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index b9f9ec33384d..5e0de3a31f3d 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -56,7 +56,7 @@
56#define IRQ_SPI2 S5P_IRQ_VIC1(17) 56#define IRQ_SPI2 S5P_IRQ_VIC1(17)
57#define IRQ_IRDA S5P_IRQ_VIC1(18) 57#define IRQ_IRDA S5P_IRQ_VIC1(18)
58#define IRQ_IIC2 S5P_IRQ_VIC1(19) 58#define IRQ_IIC2 S5P_IRQ_VIC1(19)
59#define IRQ_IIC3 S5P_IRQ_VIC1(20) 59#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20)
60#define IRQ_HSIRX S5P_IRQ_VIC1(21) 60#define IRQ_HSIRX S5P_IRQ_VIC1(21)
61#define IRQ_HSITX S5P_IRQ_VIC1(22) 61#define IRQ_HSITX S5P_IRQ_VIC1(22)
62#define IRQ_UHOST S5P_IRQ_VIC1(23) 62#define IRQ_UHOST S5P_IRQ_VIC1(23)
@@ -86,7 +86,7 @@
86#define IRQ_HDMI S5P_IRQ_VIC2(12) 86#define IRQ_HDMI S5P_IRQ_VIC2(12)
87#define IRQ_IIC1 S5P_IRQ_VIC2(13) 87#define IRQ_IIC1 S5P_IRQ_VIC2(13)
88#define IRQ_MFC S5P_IRQ_VIC2(14) 88#define IRQ_MFC S5P_IRQ_VIC2(14)
89#define IRQ_TVENC S5P_IRQ_VIC2(15) 89#define IRQ_SDO S5P_IRQ_VIC2(15)
90#define IRQ_I2S0 S5P_IRQ_VIC2(16) 90#define IRQ_I2S0 S5P_IRQ_VIC2(16)
91#define IRQ_I2S1 S5P_IRQ_VIC2(17) 91#define IRQ_I2S1 S5P_IRQ_VIC2(17)
92#define IRQ_I2S2 S5P_IRQ_VIC2(18) 92#define IRQ_I2S2 S5P_IRQ_VIC2(18)
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index aac343c180b2..7ff609f1568b 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -90,6 +90,12 @@
90#define S5PV210_PA_FIMC1 0xFB300000 90#define S5PV210_PA_FIMC1 0xFB300000
91#define S5PV210_PA_FIMC2 0xFB400000 91#define S5PV210_PA_FIMC2 0xFB400000
92 92
93#define S5PV210_PA_SDO 0xF9000000
94#define S5PV210_PA_VP 0xF9100000
95#define S5PV210_PA_MIXER 0xF9200000
96#define S5PV210_PA_HDMI 0xFA100000
97#define S5PV210_PA_IIC_HDMIPHY 0xFA900000
98
93/* Compatibiltiy Defines */ 99/* Compatibiltiy Defines */
94 100
95#define S3C_PA_FB S5PV210_PA_FB 101#define S3C_PA_FB S5PV210_PA_FB
@@ -110,6 +116,13 @@
110#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 116#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
111#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS 117#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
112#define S5P_PA_MFC S5PV210_PA_MFC 118#define S5P_PA_MFC S5PV210_PA_MFC
119#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY
120
121#define S5P_PA_SDO S5PV210_PA_SDO
122#define S5P_PA_VP S5PV210_PA_VP
123#define S5P_PA_MIXER S5PV210_PA_MIXER
124#define S5P_PA_HDMI S5PV210_PA_HDMI
125
113#define S5P_PA_ONENAND S5PC110_PA_ONENAND 126#define S5P_PA_ONENAND S5PC110_PA_ONENAND
114#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 127#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
115#define S5P_PA_SDRAM S5PV210_PA_SDRAM 128#define S5P_PA_SDRAM S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index 3e22109e1b7b..eba8aea63ed8 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -43,4 +43,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
43} 43}
44 44
45static inline void s3c_pm_restored_gpios(void) { } 45static inline void s3c_pm_restored_gpios(void) { }
46static inline void s3c_pm_saved_gpios(void) { } 46static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 78925c516346..032de66fb8be 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -144,8 +144,9 @@
144 144
145#define S5P_OTHERS S5P_CLKREG(0xE000) 145#define S5P_OTHERS S5P_CLKREG(0xE000)
146#define S5P_OM_STAT S5P_CLKREG(0xE100) 146#define S5P_OM_STAT S5P_CLKREG(0xE100)
147#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804)
147#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) 148#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C)
148#define S5P_DAC_CONTROL S5P_CLKREG(0xE810) 149#define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810)
149#define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) 150#define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814)
150#define S5P_MIPI_DPHY_ENABLE (1 << 0) 151#define S5P_MIPI_DPHY_ENABLE (1 << 0)
151#define S5P_MIPI_DPHY_SRESETN (1 << 1) 152#define S5P_MIPI_DPHY_SRESETN (1 << 1)
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 85c2d51a0956..01e4867e25ad 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -48,6 +48,11 @@
48#include <plat/s5p-time.h> 48#include <plat/s5p-time.h>
49#include <plat/mfc.h> 49#include <plat/mfc.h>
50#include <plat/regs-fb-v4.h> 50#include <plat/regs-fb-v4.h>
51#include <plat/camport.h>
52
53#include <media/v4l2-mediabus.h>
54#include <media/s5p_fimc.h>
55#include <media/noon010pc30.h>
51 56
52/* Following are default values for UCON, ULCON and UFCON UART registers */ 57/* Following are default values for UCON, ULCON and UFCON UART registers */
53#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 58#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -272,6 +277,14 @@ static void __init goni_tsp_init(void)
272 i2c2_devs[0].irq = gpio_to_irq(gpio); 277 i2c2_devs[0].irq = gpio_to_irq(gpio);
273} 278}
274 279
280static void goni_camera_init(void)
281{
282 s5pv210_fimc_setup_gpio(S5P_CAMPORT_A);
283
284 /* Set max driver strength on CAM_A_CLKOUT pin. */
285 s5p_gpio_set_drvstr(S5PV210_GPE1(3), S5P_GPIO_DRVSTR_LV4);
286}
287
275/* MAX8998 regulators */ 288/* MAX8998 regulators */
276#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) 289#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
277 290
@@ -285,6 +298,7 @@ static struct regulator_consumer_supply goni_ldo5_consumers[] = {
285 298
286static struct regulator_consumer_supply goni_ldo8_consumers[] = { 299static struct regulator_consumer_supply goni_ldo8_consumers[] = {
287 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), 300 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
301 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
288}; 302};
289 303
290static struct regulator_consumer_supply goni_ldo11_consumers[] = { 304static struct regulator_consumer_supply goni_ldo11_consumers[] = {
@@ -475,6 +489,10 @@ static struct regulator_consumer_supply buck1_consumer =
475static struct regulator_consumer_supply buck2_consumer = 489static struct regulator_consumer_supply buck2_consumer =
476 REGULATOR_SUPPLY("vddint", NULL); 490 REGULATOR_SUPPLY("vddint", NULL);
477 491
492static struct regulator_consumer_supply buck3_consumer =
493 REGULATOR_SUPPLY("vdet", "s5p-sdo");
494
495
478static struct regulator_init_data goni_buck1_data = { 496static struct regulator_init_data goni_buck1_data = {
479 .constraints = { 497 .constraints = {
480 .name = "VARM_1.2V", 498 .name = "VARM_1.2V",
@@ -511,6 +529,8 @@ static struct regulator_init_data goni_buck3_data = {
511 .enabled = 1, 529 .enabled = 1,
512 }, 530 },
513 }, 531 },
532 .num_consumer_supplies = 1,
533 .consumer_supplies = &buck3_consumer,
514}; 534};
515 535
516static struct regulator_init_data goni_buck4_data = { 536static struct regulator_init_data goni_buck4_data = {
@@ -801,6 +821,39 @@ static void goni_setup_sdhci(void)
801 s3c_sdhci2_set_platdata(&goni_hsmmc2_data); 821 s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
802}; 822};
803 823
824static struct noon010pc30_platform_data noon010pc30_pldata = {
825 .clk_rate = 16000000UL,
826 .gpio_nreset = S5PV210_GPB(2), /* CAM_CIF_NRST */
827 .gpio_nstby = S5PV210_GPB(0), /* CAM_CIF_NSTBY */
828};
829
830static struct i2c_board_info noon010pc30_board_info = {
831 I2C_BOARD_INFO("NOON010PC30", 0x60 >> 1),
832 .platform_data = &noon010pc30_pldata,
833};
834
835static struct s5p_fimc_isp_info goni_camera_sensors[] = {
836 {
837 .mux_id = 0,
838 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
839 V4L2_MBUS_VSYNC_ACTIVE_LOW,
840 .bus_type = FIMC_ITU_601,
841 .board_info = &noon010pc30_board_info,
842 .i2c_bus_num = 0,
843 .clk_frequency = 16000000UL,
844 },
845};
846
847struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
848 .isp_info = goni_camera_sensors,
849 .num_clients = ARRAY_SIZE(goni_camera_sensors),
850};
851
852struct platform_device s5p_device_fimc_md = {
853 .name = "s5p-fimc-md",
854 .id = -1,
855};
856
804static struct platform_device *goni_devices[] __initdata = { 857static struct platform_device *goni_devices[] __initdata = {
805 &s3c_device_fb, 858 &s3c_device_fb,
806 &s5p_device_onenand, 859 &s5p_device_onenand,
@@ -812,10 +865,13 @@ static struct platform_device *goni_devices[] __initdata = {
812 &s5p_device_mfc, 865 &s5p_device_mfc,
813 &s5p_device_mfc_l, 866 &s5p_device_mfc_l,
814 &s5p_device_mfc_r, 867 &s5p_device_mfc_r,
868 &s5p_device_mixer,
869 &s5p_device_sdo,
815 &s3c_device_i2c0, 870 &s3c_device_i2c0,
816 &s5p_device_fimc0, 871 &s5p_device_fimc0,
817 &s5p_device_fimc1, 872 &s5p_device_fimc1,
818 &s5p_device_fimc2, 873 &s5p_device_fimc2,
874 &s5p_device_fimc_md,
819 &s3c_device_hsmmc0, 875 &s3c_device_hsmmc0,
820 &s3c_device_hsmmc1, 876 &s3c_device_hsmmc1,
821 &s3c_device_hsmmc2, 877 &s3c_device_hsmmc2,
@@ -884,6 +940,12 @@ static void __init goni_machine_init(void)
884 /* FB */ 940 /* FB */
885 s3c_fb_set_platdata(&goni_lcd_pdata); 941 s3c_fb_set_platdata(&goni_lcd_pdata);
886 942
943 /* FIMC */
944 s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata),
945 &s5p_device_fimc_md);
946
947 goni_camera_init();
948
887 /* SPI */ 949 /* SPI */
888 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); 950 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
889 951
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 04:24:22 -0500