ARM: pm: convert samsung platforms to generic suspend/resume support

Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 4 insertions, 101 deletions

diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index d4d222b716b4..a3d649466fb1 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -35,50 +35,24 @@
         /* s3c_cpu_save
          *
          * entry:
-         *      r0 = save address (virtual addr of s3c_sleep_save_phys)
+         *      r1 = v:p offset
         */
 
 ENTRY(s3c_cpu_save)
 
         stmfd   sp!, { r3 - r12, lr }
-
-        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
-        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
-        mrc     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
-        mrc     p15, 0, r8, c2, c0, 2   @ Translation Table Control
-        mrc     p15, 0, r9, c1, c0, 0   @ Control register
-        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
-        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
-        mrc     p15, 0, r12, c10, c2, 0 @ Read PRRR
-        mrc     p15, 0, r3, c10, c2, 1  @ READ NMRR
-
-        stmia   r0, { r3 - r13 }
-
-        bl      s3c_pm_cb_flushcache
+        ldr     r3, =resume_with_mmu
+        bl      cpu_suspend
 
         ldr     r0, =pm_cpu_sleep
         ldr     r0, [ r0 ]
         mov     pc, r0
 
 resume_with_mmu:
-        /*
-         * After MMU is turned on, restore the previous MMU table.
-         */
-        ldr     r9 , =(PAGE_OFFSET - PHYS_OFFSET)
-        add     r4, r4, r9
-        str     r12, [r4]
-
         ldmfd   sp!, { r3 - r12, pc }
 
         .ltorg
 
-        .data
-
-        .global s3c_sleep_save_phys
-s3c_sleep_save_phys:
-        .word   0
-
         /* sleep magic, to allow the bootloader to check for an valid
          * image to resume to. Must be the first word before the
          * s3c_cpu_resume entry.
@@ -96,75 +70,4 @@ s3c_sleep_save_phys:
         */
 
 ENTRY(s3c_cpu_resume)
-        mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
-        msr     cpsr_c, r0
-
-        mov     r1, #0
-        mcr     p15, 0, r1, c8, c7, 0           @ invalidate TLBs
-        mcr     p15, 0, r1, c7, c5, 0           @ invalidate I Cache
-
-        ldr     r0, s3c_sleep_save_phys         @ address of restore block
-        ldmia   r0, { r3 - r13 }
-
-        mcr     p15, 0, r4, c13, c0, 0          @ FCSE/PID
-        mcr     p15, 0, r5, c3, c0, 0           @ Domain ID
-
-        mcr     p15, 0, r8, c2, c0, 2           @ Translation Table Control
-        mcr     p15, 0, r7, c2, c0, 1           @ Translation Table BASE1
-        mcr     p15, 0, r6, c2, c0, 0           @ Translation Table BASE0
-
-        mcr     p15, 0, r10, c1, c0, 1          @ Auxiliary control register
-
-        mov     r0, #0
-        mcr     p15, 0, r0, c8, c7, 0           @ Invalidate I & D TLB
-
-        mov     r0, #0                          @ restore copro access
-        mcr     p15, 0, r11, c1, c0, 2          @ Co-processor access
-        mcr     p15, 0, r0, c7, c5, 4
-
-        mcr     p15, 0, r12, c10, c2, 0         @ write PRRR
-        mcr     p15, 0, r3, c10, c2, 1          @ write NMRR
-
-        /*
-         * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
-         * And there are no valid entries in the MMU table at this point.
-         * So before turning on the MMU, the MMU entry for the DRAM address
-         * range is added. After the MMU is turned on, the other entries
-         * in the MMU table will be restored.
-        */
-
-        /* r6 = Translation Table BASE0 */
-        mov     r4, r6
-        mov     r4, r4, LSR #14
-        mov     r4, r4, LSL #14
-
-        /* Load address for adding to MMU table list */
-        ldr     r11, =0xE010F000                @ INFORM0 reg.
-        ldr     r10, [r11, #0]
-        mov     r10, r10, LSR #18
-        bic     r10, r10, #0x3
-        orr     r4, r4, r10
-
-        /* Calculate MMU table entry */
-        mov     r10, r10, LSL #18
-        ldr     r5, =0x40E
-        orr     r10, r10, r5
-
-        /* Back up originally data */
-        ldr     r12, [r4]
-
-        /* Add calculated MMU table entry into MMU table list */
-        str     r10, [r4]
-
-        ldr     r2, =resume_with_mmu
-        mcr     p15, 0, r9, c1, c0, 0           @ turn on MMU, etc
-
-        nop
-        nop
-        nop
-        nop
-        nop                                     @ second-to-last before mmu
-
-        mov     pc, r2                          @ go back to virtual address
-
-        .ltorg
+        b       cpu_resume