diff options
author | Jaecheol Lee <jc.lee@samsung.com> | 2010-09-15 02:57:37 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-20 18:52:17 -0400 |
commit | 1d826d14cc2783d0c09750c2e1eeb2bdd358769b (patch) | |
tree | 639f9e039291ac3c152eb2158d8f5678f5e25107 /arch/arm/mach-s5pv210 | |
parent | 2a5555822ea83d583b46437cff6829eec0166475 (diff) |
ARM: S5PV210: Add DMC map_desc table for supporting DMC access
This patch adds DMC(DRAM Memory Controller) map_desc table.
Because some driver such as CPUFREQ need to access DMC register.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r-- | arch/arm/mach-s5pv210/cpu.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/map.h | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 2f16bfc0a116..3347a23074b4 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c | |||
@@ -85,6 +85,16 @@ static struct map_desc s5pv210_iodesc[] __initdata = { | |||
85 | .pfn = __phys_to_pfn(S5PV210_PA_SROMC), | 85 | .pfn = __phys_to_pfn(S5PV210_PA_SROMC), |
86 | .length = SZ_4K, | 86 | .length = SZ_4K, |
87 | .type = MT_DEVICE, | 87 | .type = MT_DEVICE, |
88 | }, { | ||
89 | .virtual = (unsigned long)S5P_VA_DMC0, | ||
90 | .pfn = __phys_to_pfn(S5PV210_PA_DMC0), | ||
91 | .length = SZ_4K, | ||
92 | .type = MT_DEVICE, | ||
93 | }, { | ||
94 | .virtual = (unsigned long)S5P_VA_DMC1, | ||
95 | .pfn = __phys_to_pfn(S5PV210_PA_DMC1), | ||
96 | .length = SZ_4K, | ||
97 | .type = MT_DEVICE, | ||
88 | } | 98 | } |
89 | }; | 99 | }; |
90 | 100 | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index bd9afd52466a..3e89c22412a3 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h | |||
@@ -96,6 +96,9 @@ | |||
96 | 96 | ||
97 | #define S5PV210_PA_ADC (0xE1700000) | 97 | #define S5PV210_PA_ADC (0xE1700000) |
98 | 98 | ||
99 | #define S5PV210_PA_DMC0 (0xF0000000) | ||
100 | #define S5PV210_PA_DMC1 (0xF1400000) | ||
101 | |||
99 | /* compatibiltiy defines. */ | 102 | /* compatibiltiy defines. */ |
100 | #define S3C_PA_UART S5PV210_PA_UART | 103 | #define S3C_PA_UART S5PV210_PA_UART |
101 | #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) | 104 | #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) |