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authorKukjin Kim <kgene.kim@samsung.com>2010-10-01 07:54:56 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-22 22:51:09 -0400
commit818ac8c134250c2f57425d1e3b3a0e19636b5506 (patch)
treeec67576a1e6feeb66f197315caed0347ba02f9d1 /arch/arm/mach-s5pv210/setup-ide.c
parente27ecd7306992fbe58ab03f20aa3452a8b40499a (diff)
ARM: S5PV210: 2nd Change to using s3c_gpio_cfgall_range()
This patch changes the code setting range of GPIO pins' configuration and pull state to use the recently introduced s3c_gpio_cfgpin_range(). NOTE: This is for missed things from the previous patch. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210/setup-ide.c')
-rw-r--r--arch/arm/mach-s5pv210/setup-ide.c49
1 files changed, 19 insertions, 30 deletions
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
index b558b1cc8d60..d7cd10f9230a 100644
--- a/arch/arm/mach-s5pv210/setup-ide.c
+++ b/arch/arm/mach-s5pv210/setup-ide.c
@@ -15,36 +15,25 @@
15 15
16#include <plat/gpio-cfg.h> 16#include <plat/gpio-cfg.h>
17 17
18static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
19{
20 s3c_gpio_cfgall_range(base, nr, S3C_GPIO_SFN(4), S3C_GPIO_PULL_NONE);
21
22 for (; nr > 0; nr--, base++)
23 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
24}
25
18void s5pv210_ide_setup_gpio(void) 26void s5pv210_ide_setup_gpio(void)
19{ 27{
20 unsigned int gpio = 0; 28 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
21 29 s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
22 for (gpio = S5PV210_GPJ0(0); gpio <= S5PV210_GPJ0(7); gpio++) { 30
23 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, 31 /* CF_Data[0 - 7] */
24 CF_DMACK */ 32 s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
25 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); 33
26 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 34 /* CF_Data[8 - 15] */
27 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 35 s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
28 } 36
29 37 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
30 for (gpio = S5PV210_GPJ2(0); gpio <= S5PV210_GPJ2(7); gpio++) { 38 s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
31 /*CF_Data[0 - 7] */
32 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
33 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
34 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
35 }
36
37 for (gpio = S5PV210_GPJ3(0); gpio <= S5PV210_GPJ3(7); gpio++) {
38 /* CF_Data[8 - 15] */
39 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
40 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
41 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
42 }
43
44 for (gpio = S5PV210_GPJ4(0); gpio <= S5PV210_GPJ4(3); gpio++) {
45 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
46 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
47 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
48 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
49 }
50} 39}