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authorBen Dooks <ben-linux@fluff.org>2010-05-27 04:02:32 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-22 22:50:29 -0400
commit53134a740e3b9ce3c04e853e231a624bd4260480 (patch)
tree8c7a4a0b4a0bc5245d455329f46dacae3fefe11c /arch/arm/mach-s5pv210/setup-fb-24bpp.c
parenta40af06655f97d88fc1b0fcc9b5f2a5c06a27a4a (diff)
ARM: S5PV210: Change to using s3c_gpio_cfgall_range()
Change the code setting a range of GPIO pins' configuration and pull state to use the recently introduced s3c_gpio_cfgall_range(). Mop up a few missed s3c_gpio_cfgpin_range() changes. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210/setup-fb-24bpp.c')
-rw-r--r--arch/arm/mach-s5pv210/setup-fb-24bpp.c34
1 files changed, 11 insertions, 23 deletions
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index 928cf1f125fa..a33fe96191d2 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -21,33 +21,21 @@
21#include <mach/regs-clock.h> 21#include <mach/regs-clock.h>
22#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
23 23
24void s5pv210_fb_gpio_setup_24bpp(void) 24static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
25{ 25{
26 unsigned int gpio = 0; 26 s3c_gpio_cfgall_range(base, nr, S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE);
27
28 for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) {
29 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
30 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
31 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
32 }
33 27
34 for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) { 28 for (; nr > 0; nr--, base++)
35 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 29 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
36 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 30}
37 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
38 }
39 31
40 for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) {
41 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
42 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
43 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
44 }
45 32
46 for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) { 33void s5pv210_fb_gpio_setup_24bpp(void)
47 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 34{
48 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 35 s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
49 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 36 s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
50 } 37 s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
38 s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
51 39
52 /* Set DISPLAY_CONTROL register for Display path selection. 40 /* Set DISPLAY_CONTROL register for Display path selection.
53 * 41 *