diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-06 08:34:55 -0400 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-06 08:34:55 -0400 |
commit | f2b7e3c54a304677a1142829fb5913595885379f (patch) | |
tree | 1eb941524c7325672f947dab525d96228b362e20 /arch/arm/mach-s5pv210/mach-goni.c | |
parent | 6b8eda04ffdc24b68d379a32358f4f09a425a380 (diff) | |
parent | 0fdb480e7fb1ecdd4076ddf8b6ab16b0d77406c1 (diff) |
Merge branch 'next-s5p' into for-next
Conflicts:
arch/arm/mach-s5pv210/mach-aquila.c
arch/arm/mach-s5pv210/mach-goni.c
Diffstat (limited to 'arch/arm/mach-s5pv210/mach-goni.c')
-rw-r--r-- | arch/arm/mach-s5pv210/mach-goni.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index a094b44a43e8..0be739e5bfe6 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c | |||
@@ -38,48 +38,48 @@ | |||
38 | #include <plat/sdhci.h> | 38 | #include <plat/sdhci.h> |
39 | 39 | ||
40 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 40 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
41 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 41 | #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
42 | S3C2410_UCON_RXILEVEL | \ | 42 | S3C2410_UCON_RXILEVEL | \ |
43 | S3C2410_UCON_TXIRQMODE | \ | 43 | S3C2410_UCON_TXIRQMODE | \ |
44 | S3C2410_UCON_RXIRQMODE | \ | 44 | S3C2410_UCON_RXIRQMODE | \ |
45 | S3C2410_UCON_RXFIFO_TOI | \ | 45 | S3C2410_UCON_RXFIFO_TOI | \ |
46 | S3C2443_UCON_RXERR_IRQEN) | 46 | S3C2443_UCON_RXERR_IRQEN) |
47 | 47 | ||
48 | #define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 | 48 | #define GONI_ULCON_DEFAULT S3C2410_LCON_CS8 |
49 | 49 | ||
50 | #define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE | 50 | #define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE |
51 | 51 | ||
52 | static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { | 52 | static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { |
53 | [0] = { | 53 | [0] = { |
54 | .hwport = 0, | 54 | .hwport = 0, |
55 | .flags = 0, | 55 | .flags = 0, |
56 | .ucon = S5PV210_UCON_DEFAULT, | 56 | .ucon = GONI_UCON_DEFAULT, |
57 | .ulcon = S5PV210_ULCON_DEFAULT, | 57 | .ulcon = GONI_ULCON_DEFAULT, |
58 | .ufcon = S5PV210_UFCON_DEFAULT | | 58 | .ufcon = GONI_UFCON_DEFAULT | |
59 | S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, | 59 | S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, |
60 | }, | 60 | }, |
61 | [1] = { | 61 | [1] = { |
62 | .hwport = 1, | 62 | .hwport = 1, |
63 | .flags = 0, | 63 | .flags = 0, |
64 | .ucon = S5PV210_UCON_DEFAULT, | 64 | .ucon = GONI_UCON_DEFAULT, |
65 | .ulcon = S5PV210_ULCON_DEFAULT, | 65 | .ulcon = GONI_ULCON_DEFAULT, |
66 | .ufcon = S5PV210_UFCON_DEFAULT | | 66 | .ufcon = GONI_UFCON_DEFAULT | |
67 | S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, | 67 | S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, |
68 | }, | 68 | }, |
69 | [2] = { | 69 | [2] = { |
70 | .hwport = 2, | 70 | .hwport = 2, |
71 | .flags = 0, | 71 | .flags = 0, |
72 | .ucon = S5PV210_UCON_DEFAULT, | 72 | .ucon = GONI_UCON_DEFAULT, |
73 | .ulcon = S5PV210_ULCON_DEFAULT, | 73 | .ulcon = GONI_ULCON_DEFAULT, |
74 | .ufcon = S5PV210_UFCON_DEFAULT | | 74 | .ufcon = GONI_UFCON_DEFAULT | |
75 | S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, | 75 | S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, |
76 | }, | 76 | }, |
77 | [3] = { | 77 | [3] = { |
78 | .hwport = 3, | 78 | .hwport = 3, |
79 | .flags = 0, | 79 | .flags = 0, |
80 | .ucon = S5PV210_UCON_DEFAULT, | 80 | .ucon = GONI_UCON_DEFAULT, |
81 | .ulcon = S5PV210_ULCON_DEFAULT, | 81 | .ulcon = GONI_ULCON_DEFAULT, |
82 | .ufcon = S5PV210_UFCON_DEFAULT | | 82 | .ufcon = GONI_UFCON_DEFAULT | |
83 | S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, | 83 | S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, |
84 | }, | 84 | }, |
85 | }; | 85 | }; |