aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pv210/mach-aquila.c
diff options
context:
space:
mode:
authorKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:34:55 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:34:55 -0400
commitf2b7e3c54a304677a1142829fb5913595885379f (patch)
tree1eb941524c7325672f947dab525d96228b362e20 /arch/arm/mach-s5pv210/mach-aquila.c
parent6b8eda04ffdc24b68d379a32358f4f09a425a380 (diff)
parent0fdb480e7fb1ecdd4076ddf8b6ab16b0d77406c1 (diff)
Merge branch 'next-s5p' into for-next
Conflicts: arch/arm/mach-s5pv210/mach-aquila.c arch/arm/mach-s5pv210/mach-goni.c
Diffstat (limited to 'arch/arm/mach-s5pv210/mach-aquila.c')
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0c894010e278..a6b4ed364840 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,52 +38,52 @@
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39 39
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 40/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 41#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 42 S3C2410_UCON_RXILEVEL | \
43 S3C2410_UCON_TXIRQMODE | \ 43 S3C2410_UCON_TXIRQMODE | \
44 S3C2410_UCON_RXIRQMODE | \ 44 S3C2410_UCON_RXIRQMODE | \
45 S3C2410_UCON_RXFIFO_TOI | \ 45 S3C2410_UCON_RXFIFO_TOI | \
46 S3C2443_UCON_RXERR_IRQEN) 46 S3C2443_UCON_RXERR_IRQEN)
47 47
48#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 48#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
49 49
50#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE 50#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
51 51
52static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = { 52static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
53 [0] = { 53 [0] = {
54 .hwport = 0, 54 .hwport = 0,
55 .flags = 0, 55 .flags = 0,
56 .ucon = S5PV210_UCON_DEFAULT, 56 .ucon = AQUILA_UCON_DEFAULT,
57 .ulcon = S5PV210_ULCON_DEFAULT, 57 .ulcon = AQUILA_ULCON_DEFAULT,
58 /* 58 /*
59 * Actually UART0 can support 256 bytes fifo, but aquila board 59 * Actually UART0 can support 256 bytes fifo, but aquila board
60 * supports 128 bytes fifo because of initial chip bug 60 * supports 128 bytes fifo because of initial chip bug
61 */ 61 */
62 .ufcon = S5PV210_UFCON_DEFAULT | 62 .ufcon = AQUILA_UFCON_DEFAULT |
63 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128, 63 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
64 }, 64 },
65 [1] = { 65 [1] = {
66 .hwport = 1, 66 .hwport = 1,
67 .flags = 0, 67 .flags = 0,
68 .ucon = S5PV210_UCON_DEFAULT, 68 .ucon = AQUILA_UCON_DEFAULT,
69 .ulcon = S5PV210_ULCON_DEFAULT, 69 .ulcon = AQUILA_ULCON_DEFAULT,
70 .ufcon = S5PV210_UFCON_DEFAULT | 70 .ufcon = AQUILA_UFCON_DEFAULT |
71 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, 71 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
72 }, 72 },
73 [2] = { 73 [2] = {
74 .hwport = 2, 74 .hwport = 2,
75 .flags = 0, 75 .flags = 0,
76 .ucon = S5PV210_UCON_DEFAULT, 76 .ucon = AQUILA_UCON_DEFAULT,
77 .ulcon = S5PV210_ULCON_DEFAULT, 77 .ulcon = AQUILA_ULCON_DEFAULT,
78 .ufcon = S5PV210_UFCON_DEFAULT | 78 .ufcon = AQUILA_UFCON_DEFAULT |
79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
80 }, 80 },
81 [3] = { 81 [3] = {
82 .hwport = 3, 82 .hwport = 3,
83 .flags = 0, 83 .flags = 0,
84 .ucon = S5PV210_UCON_DEFAULT, 84 .ucon = AQUILA_UCON_DEFAULT,
85 .ulcon = S5PV210_ULCON_DEFAULT, 85 .ulcon = AQUILA_ULCON_DEFAULT,
86 .ufcon = S5PV210_UFCON_DEFAULT | 86 .ufcon = AQUILA_UFCON_DEFAULT |
87 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 87 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
88 }, 88 },
89}; 89};