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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-08-06 13:13:54 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-08-06 13:13:54 -0400
commit11e4afb49b7fa1fc8e1ffd850c1806dd86a08204 (patch)
tree9e57efcb106ae912f7bec718feb3f8ec607559bb /arch/arm/mach-s5pv210/include/mach/irqs.h
parent162500b3a3ff39d941d29db49b41a16667ae44f0 (diff)
parent9b2a606d3898fcb2eedb6faded3bb37549590ac4 (diff)
Merge branches 'gemini' and 'misc' into devel
Diffstat (limited to 'arch/arm/mach-s5pv210/include/mach/irqs.h')
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h28
1 files changed, 7 insertions, 21 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 62c5175ef291..96895378ea27 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -17,22 +17,6 @@
17 17
18/* VIC0: System, DMA, Timer */ 18/* VIC0: System, DMA, Timer */
19 19
20#define IRQ_EINT0 S5P_IRQ_VIC0(0)
21#define IRQ_EINT1 S5P_IRQ_VIC0(1)
22#define IRQ_EINT2 S5P_IRQ_VIC0(2)
23#define IRQ_EINT3 S5P_IRQ_VIC0(3)
24#define IRQ_EINT4 S5P_IRQ_VIC0(4)
25#define IRQ_EINT5 S5P_IRQ_VIC0(5)
26#define IRQ_EINT6 S5P_IRQ_VIC0(6)
27#define IRQ_EINT7 S5P_IRQ_VIC0(7)
28#define IRQ_EINT8 S5P_IRQ_VIC0(8)
29#define IRQ_EINT9 S5P_IRQ_VIC0(9)
30#define IRQ_EINT10 S5P_IRQ_VIC0(10)
31#define IRQ_EINT11 S5P_IRQ_VIC0(11)
32#define IRQ_EINT12 S5P_IRQ_VIC0(12)
33#define IRQ_EINT13 S5P_IRQ_VIC0(13)
34#define IRQ_EINT14 S5P_IRQ_VIC0(14)
35#define IRQ_EINT15 S5P_IRQ_VIC0(15)
36#define IRQ_EINT16_31 S5P_IRQ_VIC0(16) 20#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
37#define IRQ_BATF S5P_IRQ_VIC0(17) 21#define IRQ_BATF S5P_IRQ_VIC0(17)
38#define IRQ_MDMA S5P_IRQ_VIC0(18) 22#define IRQ_MDMA S5P_IRQ_VIC0(18)
@@ -134,13 +118,15 @@
134#define IRQ_MDNIE3 S5P_IRQ_VIC3(8) 118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
135#define IRQ_VIC_END S5P_IRQ_VIC3(31) 119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
136 120
137#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) 121#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
138 122#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
139#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
140#define IRQ_EINT(x) S5P_EINT(x)
141 123
142/* Set the default NR_IRQS */ 124/* Set the default NR_IRQS */
125#define NR_IRQS (IRQ_EINT(31) + 1)
143 126
144#define NR_IRQS (IRQ_EINT(31) + 1) 127/* Compatibility */
128#define IRQ_LCD_FIFO IRQ_LCD0
129#define IRQ_LCD_VSYNC IRQ_LCD1
130#define IRQ_LCD_SYSTEM IRQ_LCD2
145 131
146#endif /* ASM_ARCH_IRQS_H */ 132#endif /* ASM_ARCH_IRQS_H */