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authorThomas Abraham <thomas.ab@samsung.com>2010-05-16 20:38:01 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-16 21:37:33 -0400
commit59cda520881a1caf4332d6b03634c96fba361591 (patch)
tree4448f691315f16180073a013ff0e02cbbff42771 /arch/arm/mach-s5pv210/clock.c
parent7ebd467551ed6ae200d7835a84bbda0dcadaa511 (diff)
ARM: S5PV210: Rearrange the system clock definitions
The system clock definitions are currently defined below the peripheral clock definitions in the V210 clock code. For the V210 clock updates that follow this patch, it is required that the system clock definitions such as the mout_apll and mout_mpll be defined prior to the device clock definitions. This patch re-arranges the system clock defintions for the clock updates that follow this patch. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5pv210/clock.c')
-rw-r--r--arch/arm/mach-s5pv210/clock.c54
1 files changed, 27 insertions, 27 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index ccccae262351..a620cd8d347c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -31,6 +31,33 @@
31#include <plat/clock-clksrc.h> 31#include <plat/clock-clksrc.h>
32#include <plat/s5pv210.h> 32#include <plat/s5pv210.h>
33 33
34static struct clksrc_clk clk_mout_apll = {
35 .clk = {
36 .name = "mout_apll",
37 .id = -1,
38 },
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
41};
42
43static struct clksrc_clk clk_mout_epll = {
44 .clk = {
45 .name = "mout_epll",
46 .id = -1,
47 },
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
50};
51
52static struct clksrc_clk clk_mout_mpll = {
53 .clk = {
54 .name = "mout_mpll",
55 .id = -1,
56 },
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59};
60
34static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) 61static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
35{ 62{
36 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); 63 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
@@ -272,33 +299,6 @@ static struct clk init_clocks[] = {
272 }, 299 },
273}; 300};
274 301
275static struct clksrc_clk clk_mout_apll = {
276 .clk = {
277 .name = "mout_apll",
278 .id = -1,
279 },
280 .sources = &clk_src_apll,
281 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
282};
283
284static struct clksrc_clk clk_mout_epll = {
285 .clk = {
286 .name = "mout_epll",
287 .id = -1,
288 },
289 .sources = &clk_src_epll,
290 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
291};
292
293static struct clksrc_clk clk_mout_mpll = {
294 .clk = {
295 .name = "mout_mpll",
296 .id = -1,
297 },
298 .sources = &clk_src_mpll,
299 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
300};
301
302static struct clk *clkset_uart_list[] = { 302static struct clk *clkset_uart_list[] = {
303 [6] = &clk_mout_mpll.clk, 303 [6] = &clk_mout_mpll.clk,
304 [7] = &clk_mout_epll.clk, 304 [7] = &clk_mout_epll.clk,