diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-01-04 03:51:30 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-01-04 04:27:43 -0500 |
commit | 3c0fa647159895139d4a25f3d87b90af26789a5c (patch) | |
tree | 1ec43f87471c0ddabd3a89ce9bae8c7d32484609 /arch/arm/mach-s5pv210/clock.c | |
parent | 96ee39c445243dc58b71d72456a5bd19d9b04f31 (diff) |
ARM: S5PV210: Tidy init+disable clock usage and s3c24xx_register_clocks cleanup
This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using and cleanups
the return of s3c24xx_register_clocks() because it includes it.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pv210/clock.c')
-rw-r--r-- | arch/arm/mach-s5pv210/clock.c | 19 |
1 files changed, 4 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 019c3a69b0e4..061a9b67fa99 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -309,7 +309,7 @@ static struct clk_ops clk_fout_apll_ops = { | |||
309 | .get_rate = s5pv210_clk_fout_apll_get_rate, | 309 | .get_rate = s5pv210_clk_fout_apll_get_rate, |
310 | }; | 310 | }; |
311 | 311 | ||
312 | static struct clk init_clocks_disable[] = { | 312 | static struct clk init_clocks_off[] = { |
313 | { | 313 | { |
314 | .name = "pdma", | 314 | .name = "pdma", |
315 | .id = 0, | 315 | .id = 0, |
@@ -1220,13 +1220,9 @@ static struct clk *clks[] __initdata = { | |||
1220 | 1220 | ||
1221 | void __init s5pv210_register_clocks(void) | 1221 | void __init s5pv210_register_clocks(void) |
1222 | { | 1222 | { |
1223 | struct clk *clkp; | ||
1224 | int ret; | ||
1225 | int ptr; | 1223 | int ptr; |
1226 | 1224 | ||
1227 | ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | 1225 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
1228 | if (ret > 0) | ||
1229 | printk(KERN_ERR "Failed to register %u clocks\n", ret); | ||
1230 | 1226 | ||
1231 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | 1227 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) |
1232 | s3c_register_clksrc(sysclks[ptr], 1); | 1228 | s3c_register_clksrc(sysclks[ptr], 1); |
@@ -1234,15 +1230,8 @@ void __init s5pv210_register_clocks(void) | |||
1234 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | 1230 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
1235 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | 1231 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
1236 | 1232 | ||
1237 | clkp = init_clocks_disable; | 1233 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1238 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | 1234 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1239 | ret = s3c24xx_register_clock(clkp); | ||
1240 | if (ret < 0) { | ||
1241 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
1242 | clkp->name, ret); | ||
1243 | } | ||
1244 | (clkp->enable)(clkp, 0); | ||
1245 | } | ||
1246 | 1235 | ||
1247 | s3c_pwmclk_init(); | 1236 | s3c_pwmclk_init(); |
1248 | } | 1237 | } |