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authorThomas Abraham <thomas.ab@samsung.com>2010-05-16 20:39:03 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-16 21:37:39 -0400
commitf64cacc3194f49c7371e2ce61c22de62b8652dc7 (patch)
treed5e7c78797343c80bdd3b64c97f5b98c4fd89c0b /arch/arm/mach-s5pv210/clock.c
parent4583487c43358070ef1bd43dd1cbaf2dd42e4db7 (diff)
ARM: S5PV210: Add sclk clocks of type 'struct clksrc_clk' clock
Add sclk clocks of type 'struct clksrc_clk' clock. The 'group2' of clock clock sources is also added. This patch also changes the the 'id' member value of the uclk1 clock for instance instance 0 since there are 4 instances of the uclk1 clock. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5pv210/clock.c')
-rw-r--r--arch/arm/mach-s5pv210/clock.c230
1 files changed, 229 insertions, 1 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 015471040f56..154bca4abc09 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -173,6 +173,11 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); 173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
174} 174}
175 175
176static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
177{
178 return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
179}
180
176static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) 181static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
177{ 182{
178 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); 183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
@@ -637,6 +642,23 @@ static struct clksrc_sources clkset_sclk_spdif = {
637 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), 642 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
638}; 643};
639 644
645static struct clk *clkset_group2_list[] = {
646 [0] = &clk_ext_xtal_mux,
647 [1] = &clk_xusbxti,
648 [2] = &clk_sclk_hdmi27m,
649 [3] = &clk_sclk_usbphy0,
650 [4] = &clk_sclk_usbphy1,
651 [5] = &clk_sclk_hdmiphy,
652 [6] = &clk_mout_mpll.clk,
653 [7] = &clk_mout_epll.clk,
654 [8] = &clk_sclk_vpll.clk,
655};
656
657static struct clksrc_sources clkset_group2 = {
658 .sources = clkset_group2_list,
659 .nr_sources = ARRAY_SIZE(clkset_group2_list),
660};
661
640static struct clksrc_clk clksrcs[] = { 662static struct clksrc_clk clksrcs[] = {
641 { 663 {
642 .clk = { 664 .clk = {
@@ -657,7 +679,7 @@ static struct clksrc_clk clksrcs[] = {
657 }, { 679 }, {
658 .clk = { 680 .clk = {
659 .name = "uclk1", 681 .name = "uclk1",
660 .id = -1, 682 .id = 0,
661 .ctrlbit = (1<<17), 683 .ctrlbit = (1<<17),
662 .enable = s5pv210_clk_ip3_ctrl, 684 .enable = s5pv210_clk_ip3_ctrl,
663 }, 685 },
@@ -665,6 +687,36 @@ static struct clksrc_clk clksrcs[] = {
665 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, 687 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
666 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, 688 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
667 }, { 689 }, {
690 .clk = {
691 .name = "uclk1",
692 .id = 1,
693 .enable = s5pv210_clk_ip3_ctrl,
694 .ctrlbit = (1 << 18),
695 },
696 .sources = &clkset_uart,
697 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
698 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
699 }, {
700 .clk = {
701 .name = "uclk1",
702 .id = 2,
703 .enable = s5pv210_clk_ip3_ctrl,
704 .ctrlbit = (1 << 19),
705 },
706 .sources = &clkset_uart,
707 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
708 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
709 }, {
710 .clk = {
711 .name = "uclk1",
712 .id = 3,
713 .enable = s5pv210_clk_ip3_ctrl,
714 .ctrlbit = (1 << 20),
715 },
716 .sources = &clkset_uart,
717 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
718 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
719 }, {
668 .clk = { 720 .clk = {
669 .name = "sclk_mixer", 721 .name = "sclk_mixer",
670 .id = -1, 722 .id = -1,
@@ -682,6 +734,182 @@ static struct clksrc_clk clksrcs[] = {
682 }, 734 },
683 .sources = &clkset_sclk_spdif, 735 .sources = &clkset_sclk_spdif,
684 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, 736 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
737 }, {
738 .clk = {
739 .name = "sclk_fimc",
740 .id = 0,
741 .enable = s5pv210_clk_ip0_ctrl,
742 .ctrlbit = (1 << 24),
743 },
744 .sources = &clkset_group2,
745 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
746 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
747 }, {
748 .clk = {
749 .name = "sclk_fimc",
750 .id = 1,
751 .enable = s5pv210_clk_ip0_ctrl,
752 .ctrlbit = (1 << 25),
753 },
754 .sources = &clkset_group2,
755 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
756 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
757 }, {
758 .clk = {
759 .name = "sclk_fimc",
760 .id = 2,
761 .enable = s5pv210_clk_ip0_ctrl,
762 .ctrlbit = (1 << 26),
763 },
764 .sources = &clkset_group2,
765 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
766 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
767 }, {
768 .clk = {
769 .name = "sclk_cam",
770 .id = 0,
771 },
772 .sources = &clkset_group2,
773 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
774 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
775 }, {
776 .clk = {
777 .name = "sclk_cam",
778 .id = 1,
779 },
780 .sources = &clkset_group2,
781 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
782 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
783 }, {
784 .clk = {
785 .name = "sclk_fimd",
786 .id = -1,
787 .enable = s5pv210_clk_ip1_ctrl,
788 .ctrlbit = (1 << 0),
789 },
790 .sources = &clkset_group2,
791 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
792 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
793 }, {
794 .clk = {
795 .name = "sclk_mmc",
796 .id = 0,
797 .enable = s5pv210_clk_ip2_ctrl,
798 .ctrlbit = (1 << 16),
799 },
800 .sources = &clkset_group2,
801 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
802 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
803 }, {
804 .clk = {
805 .name = "sclk_mmc",
806 .id = 1,
807 .enable = s5pv210_clk_ip2_ctrl,
808 .ctrlbit = (1 << 17),
809 },
810 .sources = &clkset_group2,
811 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
812 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
813 }, {
814 .clk = {
815 .name = "sclk_mmc",
816 .id = 2,
817 .enable = s5pv210_clk_ip2_ctrl,
818 .ctrlbit = (1 << 18),
819 },
820 .sources = &clkset_group2,
821 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
822 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
823 }, {
824 .clk = {
825 .name = "sclk_mmc",
826 .id = 3,
827 .enable = s5pv210_clk_ip2_ctrl,
828 .ctrlbit = (1 << 19),
829 },
830 .sources = &clkset_group2,
831 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
832 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
833 }, {
834 .clk = {
835 .name = "sclk_mfc",
836 .id = -1,
837 .enable = s5pv210_clk_ip0_ctrl,
838 .ctrlbit = (1 << 16),
839 },
840 .sources = &clkset_group1,
841 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
842 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
843 }, {
844 .clk = {
845 .name = "sclk_g2d",
846 .id = -1,
847 .enable = s5pv210_clk_ip0_ctrl,
848 .ctrlbit = (1 << 12),
849 },
850 .sources = &clkset_group1,
851 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
852 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
853 }, {
854 .clk = {
855 .name = "sclk_g3d",
856 .id = -1,
857 .enable = s5pv210_clk_ip0_ctrl,
858 .ctrlbit = (1 << 8),
859 },
860 .sources = &clkset_group1,
861 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
862 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
863 }, {
864 .clk = {
865 .name = "sclk_csis",
866 .id = -1,
867 .enable = s5pv210_clk_ip0_ctrl,
868 .ctrlbit = (1 << 31),
869 },
870 .sources = &clkset_group2,
871 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
872 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
873 }, {
874 .clk = {
875 .name = "sclk_spi",
876 .id = 0,
877 .enable = s5pv210_clk_ip3_ctrl,
878 .ctrlbit = (1 << 12),
879 },
880 .sources = &clkset_group2,
881 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
882 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
883 }, {
884 .clk = {
885 .name = "sclk_spi",
886 .id = 1,
887 .enable = s5pv210_clk_ip3_ctrl,
888 .ctrlbit = (1 << 13),
889 },
890 .sources = &clkset_group2,
891 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
892 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
893 }, {
894 .clk = {
895 .name = "sclk_pwi",
896 .id = -1,
897 .enable = &s5pv210_clk_ip4_ctrl,
898 .ctrlbit = (1 << 2),
899 },
900 .sources = &clkset_group2,
901 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
902 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
903 }, {
904 .clk = {
905 .name = "sclk_pwm",
906 .id = -1,
907 .enable = s5pv210_clk_ip3_ctrl,
908 .ctrlbit = (1 << 23),
909 },
910 .sources = &clkset_group2,
911 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
912 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
685 }, 913 },
686}; 914};
687 915