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authorJoonyoung Shim <jy0922.shim@samsung.com>2010-09-30 22:24:39 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-20 18:54:57 -0400
commit8ce14a221efe8ef9019e2c5b1e06fcd329e66d78 (patch)
tree1fab3fd0c7e73ec9da6d84a47e4471bd0919ea73 /arch/arm/mach-s5pc100
parent02c38497d668f46467e8ec57a243be0be5bd7f85 (diff)
ARM: SAMSUNG: Add common samsung_gpiolib_to_irq function
This patch adds a common callback for gpio_to_irq() for external and gpio interrupts for Samsung SoCs. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org> [kgene.kim@samsung.com: moved samsung_gpiolib_to_irq() for s3c24xx build] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100')
-rw-r--r--arch/arm/mach-s5pc100/gpiolib.c31
1 files changed, 8 insertions, 23 deletions
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 5811578ad4e4..def4ff83e051 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -61,25 +61,6 @@
61 * L3 8 4Bit None 61 * L3 8 4Bit None
62 */ 62 */
63 63
64static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
65{
66 int base;
67
68 base = chip->base - S5PC100_GPH0(0);
69 if (base == 0)
70 return IRQ_EINT(offset);
71 base = chip->base - S5PC100_GPH1(0);
72 if (base == 0)
73 return IRQ_EINT(8 + offset);
74 base = chip->base - S5PC100_GPH2(0);
75 if (base == 0)
76 return IRQ_EINT(16 + offset);
77 base = chip->base - S5PC100_GPH3(0);
78 if (base == 0)
79 return IRQ_EINT(24 + offset);
80 return -EINVAL;
81}
82
83static struct s3c_gpio_cfg gpio_cfg = { 64static struct s3c_gpio_cfg gpio_cfg = {
84 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 65 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
85 .set_pull = s3c_gpio_setpull_updown, 66 .set_pull = s3c_gpio_setpull_updown,
@@ -223,38 +204,42 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
223 }, { 204 }, {
224 .base = S5PC100_GPH0_BASE, 205 .base = S5PC100_GPH0_BASE,
225 .config = &gpio_cfg_eint, 206 .config = &gpio_cfg_eint,
207 .irq_base = IRQ_EINT(0),
226 .chip = { 208 .chip = {
227 .base = S5PC100_GPH0(0), 209 .base = S5PC100_GPH0(0),
228 .ngpio = S5PC100_GPIO_H0_NR, 210 .ngpio = S5PC100_GPIO_H0_NR,
229 .label = "GPH0", 211 .label = "GPH0",
230 .to_irq = s5pc100_gpiolib_to_eint, 212 .to_irq = samsung_gpiolib_to_irq,
231 }, 213 },
232 }, { 214 }, {
233 .base = S5PC100_GPH1_BASE, 215 .base = S5PC100_GPH1_BASE,
234 .config = &gpio_cfg_eint, 216 .config = &gpio_cfg_eint,
217 .irq_base = IRQ_EINT(8),
235 .chip = { 218 .chip = {
236 .base = S5PC100_GPH1(0), 219 .base = S5PC100_GPH1(0),
237 .ngpio = S5PC100_GPIO_H1_NR, 220 .ngpio = S5PC100_GPIO_H1_NR,
238 .label = "GPH1", 221 .label = "GPH1",
239 .to_irq = s5pc100_gpiolib_to_eint, 222 .to_irq = samsung_gpiolib_to_irq,
240 }, 223 },
241 }, { 224 }, {
242 .base = S5PC100_GPH2_BASE, 225 .base = S5PC100_GPH2_BASE,
243 .config = &gpio_cfg_eint, 226 .config = &gpio_cfg_eint,
227 .irq_base = IRQ_EINT(16),
244 .chip = { 228 .chip = {
245 .base = S5PC100_GPH2(0), 229 .base = S5PC100_GPH2(0),
246 .ngpio = S5PC100_GPIO_H2_NR, 230 .ngpio = S5PC100_GPIO_H2_NR,
247 .label = "GPH2", 231 .label = "GPH2",
248 .to_irq = s5pc100_gpiolib_to_eint, 232 .to_irq = samsung_gpiolib_to_irq,
249 }, 233 },
250 }, { 234 }, {
251 .base = S5PC100_GPH3_BASE, 235 .base = S5PC100_GPH3_BASE,
252 .config = &gpio_cfg_eint, 236 .config = &gpio_cfg_eint,
237 .irq_base = IRQ_EINT(24),
253 .chip = { 238 .chip = {
254 .base = S5PC100_GPH3(0), 239 .base = S5PC100_GPH3(0),
255 .ngpio = S5PC100_GPIO_H3_NR, 240 .ngpio = S5PC100_GPIO_H3_NR,
256 .label = "GPH3", 241 .label = "GPH3",
257 .to_irq = s5pc100_gpiolib_to_eint, 242 .to_irq = samsung_gpiolib_to_irq,
258 }, 243 },
259 }, { 244 }, {
260 .base = S5PC100_GPI_BASE, 245 .base = S5PC100_GPI_BASE,