diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2010-05-18 05:30:49 -0400 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-20 01:36:59 -0400 |
| commit | 13e51fad8f54fdab55099ea4ebe548372c06f7f7 (patch) | |
| tree | 62b6c09ccbb6b90e8546c32251e68ae43c822cf1 /arch/arm/mach-s5pc100/mach-smdkc100.c | |
| parent | 08d08fadde4549c7b857fa34f3696c882ed20864 (diff) | |
ARM: SMDKC100: remove magic values from uart setup structures
This patch introduces nice defines for the initial values for UART devices
on SMDKC100.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5pc100/mach-smdkc100.c')
| -rw-r--r-- | arch/arm/mach-s5pc100/mach-smdkc100.c | 40 |
1 files changed, 25 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index f2bce11cf287..b6f8a58cf94c 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
| @@ -43,38 +43,48 @@ | |||
| 43 | #include <plat/fb.h> | 43 | #include <plat/fb.h> |
| 44 | #include <plat/iic.h> | 44 | #include <plat/iic.h> |
| 45 | 45 | ||
| 46 | #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) | 46 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
| 47 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) | 47 | #define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 48 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | 48 | S3C2410_UCON_RXILEVEL | \ |
| 49 | S3C2410_UCON_TXIRQMODE | \ | ||
| 50 | S3C2410_UCON_RXIRQMODE | \ | ||
| 51 | S3C2410_UCON_RXFIFO_TOI | \ | ||
| 52 | S3C2443_UCON_RXERR_IRQEN) | ||
| 53 | |||
| 54 | #define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
| 55 | |||
| 56 | #define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
| 57 | S3C2440_UFCON_RXTRIG8 | \ | ||
| 58 | S3C2440_UFCON_TXTRIG16) | ||
| 49 | 59 | ||
| 50 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | 60 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { |
| 51 | [0] = { | 61 | [0] = { |
| 52 | .hwport = 0, | 62 | .hwport = 0, |
| 53 | .flags = 0, | 63 | .flags = 0, |
| 54 | .ucon = 0x3c5, | 64 | .ucon = S5PC100_UCON_DEFAULT, |
| 55 | .ulcon = 0x03, | 65 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 56 | .ufcon = 0x51, | 66 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 57 | }, | 67 | }, |
| 58 | [1] = { | 68 | [1] = { |
| 59 | .hwport = 1, | 69 | .hwport = 1, |
| 60 | .flags = 0, | 70 | .flags = 0, |
| 61 | .ucon = 0x3c5, | 71 | .ucon = S5PC100_UCON_DEFAULT, |
| 62 | .ulcon = 0x03, | 72 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 63 | .ufcon = 0x51, | 73 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 64 | }, | 74 | }, |
| 65 | [2] = { | 75 | [2] = { |
| 66 | .hwport = 2, | 76 | .hwport = 2, |
| 67 | .flags = 0, | 77 | .flags = 0, |
| 68 | .ucon = 0x3c5, | 78 | .ucon = S5PC100_UCON_DEFAULT, |
| 69 | .ulcon = 0x03, | 79 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 70 | .ufcon = 0x51, | 80 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 71 | }, | 81 | }, |
| 72 | [3] = { | 82 | [3] = { |
| 73 | .hwport = 3, | 83 | .hwport = 3, |
| 74 | .flags = 0, | 84 | .flags = 0, |
| 75 | .ucon = 0x3c5, | 85 | .ucon = S5PC100_UCON_DEFAULT, |
| 76 | .ulcon = 0x03, | 86 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 77 | .ufcon = 0x51, | 87 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 78 | }, | 88 | }, |
| 79 | }; | 89 | }; |
| 80 | 90 | ||