aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pc100/include/mach
diff options
context:
space:
mode:
authorJiri Kosina <jkosina@suse.cz>2010-06-16 12:08:13 -0400
committerJiri Kosina <jkosina@suse.cz>2010-06-16 12:08:13 -0400
commitf1bbbb6912662b9f6070c5bfc4ca9eb1f06a9d5b (patch)
treec2c130a74be25b0b2dff992e1a195e2728bdaadd /arch/arm/mach-s5pc100/include/mach
parentfd0961ff67727482bb20ca7e8ea97b83e9de2ddb (diff)
parent7e27d6e778cd87b6f2415515d7127eba53fe5d02 (diff)
Merge branch 'master' into for-next
Diffstat (limited to 'arch/arm/mach-s5pc100/include/mach')
-rw-r--r--arch/arm/mach-s5pc100/include/mach/debug-macro.S6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pc100/include/mach/entry-macro.S8
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h99
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h124
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-clock.h6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h37
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-irq.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/spi-clocks.h18
-rw-r--r--arch/arm/mach-s5pc100/include/mach/system.h9
-rw-r--r--arch/arm/mach-s5pc100/include/mach/tick.h4
12 files changed, 245 insertions, 106 deletions
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index e181f5789482..70e02e91ee3c 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,12 +22,14 @@
22 * aligned and add in the offset when we load the value here. 22 * aligned and add in the offset when we load the value here.
23 */ 23 */
24 24
25 .macro addruart, rx, tmp 25 .macro addruart, rx, rtmp
26 mrc p15, 0, \rx, c1, c0 26 mrc p15, 0, \rx, c1, c0
27 tst \rx, #1 27 tst \rx, #1
28 ldreq \rx, = S3C_PA_UART 28 ldreq \rx, = S3C_PA_UART
29 ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) 29 ldrne \rx, = S3C_VA_UART
30#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 31 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
32#endif
31 .endm 33 .endm
32 34
33/* include the reset of the code which will do the work, we're only 35/* include the reset of the code which will do the work, we're only
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index 67131939e626..ba76af052c81 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -20,7 +20,7 @@
20 .endm 20 .endm
21 21
22 .macro get_irqnr_preamble, base, tmp 22 .macro get_irqnr_preamble, base, tmp
23 ldr \base, =S3C_VA_VIC0 23 ldr \base, =VA_VIC0
24 .endm 24 .endm
25 25
26 .macro arch_ret_to_user, tmp1, tmp2 26 .macro arch_ret_to_user, tmp1, tmp2
@@ -29,18 +29,18 @@
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30 30
31 @ check the vic0 31 @ check the vic0
32 mov \irqnr, # S3C_IRQ_OFFSET + 31 32 mov \irqnr, # S5P_IRQ_OFFSET + 31
33 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] 33 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
34 teq \irqstat, #0 34 teq \irqstat, #0
35 35
36 @ otherwise try vic1 36 @ otherwise try vic1
37 addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) 37 addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
38 addeq \irqnr, \irqnr, #32 38 addeq \irqnr, \irqnr, #32
39 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] 39 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
40 teqeq \irqstat, #0 40 teqeq \irqstat, #0
41 41
42 @ otherwise try vic2 42 @ otherwise try vic2
43 addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) 43 addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
44 addeq \irqnr, \irqnr, #32 44 addeq \irqnr, \irqnr, #32
45 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] 45 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
46 teqeq \irqstat, #0 46 teqeq \irqstat, #0
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 29a8a12d9b4f..71ae1f52df1d 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,6 +146,13 @@ enum s5p_gpio_number {
146/* define the number of gpios we need to the one after the MP04() range */ 146/* define the number of gpios we need to the one after the MP04() range */
147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) 147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
148 148
149#define EINT_MODE S3C_GPIO_SFN(0x2)
150
151#define EINT_GPIO_0(x) S5PC100_GPH0(x)
152#define EINT_GPIO_1(x) S5PC100_GPH1(x)
153#define EINT_GPIO_2(x) S5PC100_GPH2(x)
154#define EINT_GPIO_3(x) S5PC100_GPH3(x)
155
149#include <asm-generic/gpio.h> 156#include <asm-generic/gpio.h>
150 157
151#endif /* __ASM_ARCH_GPIO_H */ 158#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index b53fa48a52c6..28aa551dc3a8 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,9 +11,104 @@
11 11
12#include <plat/irqs.h> 12#include <plat/irqs.h>
13 13
14/* LCD */ 14/* VIC0: system, DMA, timer */
15#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
16#define IRQ_BATF S5P_IRQ_VIC0(17)
17#define IRQ_MDMA S5P_IRQ_VIC0(18)
18#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
19#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
20#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
21#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
22#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
23#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
24#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
25#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
26#define IRQ_WDT S5P_IRQ_VIC0(27)
27#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
28#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
29#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
30
31/* VIC1: ARM, power, memory, connectivity */
32#define IRQ_CORTEX0 S5P_IRQ_VIC1(0)
33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
36#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
37#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
38#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
39#define IRQ_ONENAND S5P_IRQ_VIC1(7)
40#define IRQ_NFC S5P_IRQ_VIC1(8)
41#define IRQ_CFC S5P_IRQ_VIC1(9)
42#define IRQ_UART0 S5P_IRQ_VIC1(10)
43#define IRQ_UART1 S5P_IRQ_VIC1(11)
44#define IRQ_UART2 S5P_IRQ_VIC1(12)
45#define IRQ_UART3 S5P_IRQ_VIC1(13)
46#define IRQ_IIC S5P_IRQ_VIC1(14)
47#define IRQ_SPI0 S5P_IRQ_VIC1(15)
48#define IRQ_SPI1 S5P_IRQ_VIC1(16)
49#define IRQ_SPI2 S5P_IRQ_VIC1(17)
50#define IRQ_IRDA S5P_IRQ_VIC1(18)
51#define IRQ_CAN0 S5P_IRQ_VIC1(19)
52#define IRQ_CAN1 S5P_IRQ_VIC1(20)
53#define IRQ_HSIRX S5P_IRQ_VIC1(21)
54#define IRQ_HSITX S5P_IRQ_VIC1(22)
55#define IRQ_UHOST S5P_IRQ_VIC1(23)
56#define IRQ_OTG S5P_IRQ_VIC1(24)
57#define IRQ_MSM S5P_IRQ_VIC1(25)
58#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
59#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
60#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
61#define IRQ_MIPICSI S5P_IRQ_VIC1(29)
62#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
63
64/* VIC2: multimedia, audio, security */
65#define IRQ_LCD0 S5P_IRQ_VIC2(0)
66#define IRQ_LCD1 S5P_IRQ_VIC2(1)
67#define IRQ_LCD2 S5P_IRQ_VIC2(2)
68#define IRQ_LCD3 S5P_IRQ_VIC2(3)
69#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
70#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
71#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
72#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
73#define IRQ_JPEG S5P_IRQ_VIC2(8)
74#define IRQ_2D S5P_IRQ_VIC2(9)
75#define IRQ_3D S5P_IRQ_VIC2(10)
76#define IRQ_MIXER S5P_IRQ_VIC2(11)
77#define IRQ_HDMI S5P_IRQ_VIC2(12)
78#define IRQ_IIC1 S5P_IRQ_VIC2(13)
79#define IRQ_MFC S5P_IRQ_VIC2(14)
80#define IRQ_TVENC S5P_IRQ_VIC2(15)
81#define IRQ_I2S0 S5P_IRQ_VIC2(16)
82#define IRQ_I2S1 S5P_IRQ_VIC2(17)
83#define IRQ_I2S2 S5P_IRQ_VIC2(18)
84#define IRQ_AC97 S5P_IRQ_VIC2(19)
85#define IRQ_PCM0 S5P_IRQ_VIC2(20)
86#define IRQ_PCM1 S5P_IRQ_VIC2(21)
87#define IRQ_SPDIF S5P_IRQ_VIC2(22)
88#define IRQ_ADC S5P_IRQ_VIC2(23)
89#define IRQ_PENDN S5P_IRQ_VIC2(24)
90#define IRQ_TC IRQ_PENDN
91#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
92#define IRQ_CG S5P_IRQ_VIC2(26)
93#define IRQ_SEC S5P_IRQ_VIC2(27)
94#define IRQ_SECRX S5P_IRQ_VIC2(28)
95#define IRQ_SECTX S5P_IRQ_VIC2(29)
96#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102
103#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
104#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
105
106/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
107#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
108
109/* Compatibility */
15#define IRQ_LCD_FIFO IRQ_LCD0 110#define IRQ_LCD_FIFO IRQ_LCD0
16#define IRQ_LCD_VSYNC IRQ_LCD1 111#define IRQ_LCD_VSYNC IRQ_LCD1
17#define IRQ_LCD_SYSTEM IRQ_LCD2 112#define IRQ_LCD_SYSTEM IRQ_LCD2
18 113
19#endif /* __ASM_ARCH_IRQ_H */ 114#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe8bef6..cadae4305688 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -3,9 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * Based on mach-s3c6400/include/mach/map.h 6 * S5PC100 - Memory map definitions
7 *
8 * S5PC1XX - Memory map definitions
9 * 7 *
10 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -16,6 +14,7 @@
16#define __ASM_ARCH_MAP_H __FILE__ 14#define __ASM_ARCH_MAP_H __FILE__
17 15
18#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
19 18
20/* 19/*
21 * map-base.h has already defined virtual memory address 20 * map-base.h has already defined virtual memory address
@@ -31,25 +30,21 @@
31 * 30 *
32 */ 31 */
33 32
33#define S5PC100_PA_ONENAND_BUF (0xB0000000)
34#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
35
34/* Chip ID */ 36/* Chip ID */
37
35#define S5PC100_PA_CHIPID (0xE0000000) 38#define S5PC100_PA_CHIPID (0xE0000000)
36#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID 39#define S5P_PA_CHIPID S5PC100_PA_CHIPID
37#define S5PC1XX_VA_CHIPID S3C_VA_SYS 40
38 41#define S5PC100_PA_SYSCON (0xE0100000)
39/* System */ 42#define S5P_PA_SYSCON S5PC100_PA_SYSCON
40#define S5PC100_PA_CLK (0xE0100000) 43
41#define S5PC100_PA_CLK_OTHER (0xE0200000) 44#define S5PC100_PA_OTHERS (0xE0200000)
42#define S5PC100_PA_PWR (0xE0108000) 45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
43#define S5PC1XX_PA_CLK S5PC100_PA_CLK 46
44#define S5PC1XX_PA_PWR S5PC100_PA_PWR 47#define S5P_PA_GPIO (0xE0300000)
45#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER
46#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
47#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
48#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000)
49
50/* GPIO */
51#define S5PC100_PA_GPIO (0xE0300000)
52#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO
53#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) 48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
54 49
55/* Interrupt */ 50/* Interrupt */
@@ -59,6 +54,12 @@
59#define S5PC100_VA_VIC_OFFSET 0x10000 54#define S5PC100_VA_VIC_OFFSET 0x10000
60#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) 55#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
61#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0)
58#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1)
59#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2)
60
61
62#define S5PC100_PA_ONENAND (0xE7100000)
62 63
63/* DMA */ 64/* DMA */
64#define S5PC100_PA_MDMA (0xE8100000) 65#define S5PC100_PA_MDMA (0xE8100000)
@@ -67,84 +68,71 @@
67 68
68/* Timer */ 69/* Timer */
69#define S5PC100_PA_TIMER (0xEA000000) 70#define S5PC100_PA_TIMER (0xEA000000)
70#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER 71#define S5P_PA_TIMER S5PC100_PA_TIMER
71#define S5PC1XX_VA_TIMER S3C_VA_TIMER
72 72
73/* RTC */ 73#define S5PC100_PA_SYSTIMER (0xEA100000)
74#define S5PC100_PA_RTC (0xEA300000)
75 74
76/* UART */
77#define S5PC100_PA_UART (0xEC000000) 75#define S5PC100_PA_UART (0xEC000000)
78#define S5PC1XX_PA_UART S5PC100_PA_UART
79#define S5PC1XX_VA_UART S3C_VA_UART
80 76
81/* I2C */ 77#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
82#define S5PC100_PA_I2C (0xEC100000) 78#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
83#define S5PC100_PA_I2C1 (0xEC200000) 79#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
80#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
81#define S5P_SZ_UART SZ_256
82
83#define S5PC100_PA_IIC0 (0xEC100000)
84#define S5PC100_PA_IIC1 (0xEC200000)
85
86/* SPI */
87#define S5PC100_PA_SPI0 0xEC300000
88#define S5PC100_PA_SPI1 0xEC400000
89#define S5PC100_PA_SPI2 0xEC500000
84 90
85/* USB HS OTG */ 91/* USB HS OTG */
86#define S5PC100_PA_USB_HSOTG (0xED200000) 92#define S5PC100_PA_USB_HSOTG (0xED200000)
87#define S5PC100_PA_USB_HSPHY (0xED300000) 93#define S5PC100_PA_USB_HSPHY (0xED300000)
88 94
89/* SD/MMC */
90#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
91#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0)
92#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1)
93#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2)
94
95/* LCD */
96#define S5PC100_PA_FB (0xEE000000) 95#define S5PC100_PA_FB (0xEE000000)
97 96
98/* Multimedia */
99#define S5PC100_PA_G2D (0xEE800000)
100#define S5PC100_PA_JPEG (0xEE500000)
101#define S5PC100_PA_ROTATOR (0xEE100000)
102#define S5PC100_PA_G3D (0xEF000000)
103
104/* I2S */
105#define S5PC100_PA_I2S0 (0xF2000000) 97#define S5PC100_PA_I2S0 (0xF2000000)
106#define S5PC100_PA_I2S1 (0xF2100000) 98#define S5PC100_PA_I2S1 (0xF2100000)
107#define S5PC100_PA_I2S2 (0xF2200000) 99#define S5PC100_PA_I2S2 (0xF2200000)
108 100
101#define S5PC100_PA_AC97 0xF2300000
102
103/* PCM */
104#define S5PC100_PA_PCM0 0xF2400000
105#define S5PC100_PA_PCM1 0xF2500000
106
109/* KEYPAD */ 107/* KEYPAD */
110#define S5PC100_PA_KEYPAD (0xF3100000) 108#define S5PC100_PA_KEYPAD (0xF3100000)
111 109
112/* ADC & TouchScreen */ 110#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
113#define S5PC100_PA_TSADC (0xF3000000)
114 111
115/* ETC */
116#define S5PC100_PA_SDRAM (0x20000000) 112#define S5PC100_PA_SDRAM (0x20000000)
117#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM 113#define S5P_PA_SDRAM S5PC100_PA_SDRAM
118 114
119/* compatibility defines. */ 115/* compatibiltiy defines. */
120#define S3C_PA_RTC S5PC100_PA_RTC
121#define S3C_PA_UART S5PC100_PA_UART 116#define S3C_PA_UART S5PC100_PA_UART
122#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) 117#define S3C_PA_IIC S5PC100_PA_IIC0
123#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) 118#define S3C_PA_IIC1 S5PC100_PA_IIC1
124#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800)
125#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00)
126#define S3C_VA_UART0 (S3C_VA_UART + 0x0)
127#define S3C_VA_UART1 (S3C_VA_UART + 0x400)
128#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
129#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
130#define S3C_UART_OFFSET 0x400
131#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
132#define S3C_PA_FB S5PC100_PA_FB 119#define S3C_PA_FB S5PC100_PA_FB
133#define S3C_PA_G2D S5PC100_PA_G2D 120#define S3C_PA_G2D S5PC100_PA_G2D
134#define S3C_PA_G3D S5PC100_PA_G3D 121#define S3C_PA_G3D S5PC100_PA_G3D
135#define S3C_PA_JPEG S5PC100_PA_JPEG 122#define S3C_PA_JPEG S5PC100_PA_JPEG
136#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR 123#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
137#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) 124#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
138#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 125#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
139#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) 126#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
140#define S3C_PA_IIC S5PC100_PA_I2C
141#define S3C_PA_IIC1 S5PC100_PA_I2C1
142#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 127#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
143#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 128#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
144#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 129#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
145#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 130#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
146#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 131#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
147#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 132#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
148#define S3C_PA_TSADC S5PC100_PA_TSADC 133#define S3C_PA_TSADC S5PC100_PA_TSADC
134#define S3C_PA_ONENAND S5PC100_PA_ONENAND
135#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
136#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
149 137
150#endif /* __ASM_ARCH_C100_MAP_H */ 138#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
index f2283bdc941e..5d27d286d504 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -17,6 +17,8 @@
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19 19
20#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x))
21
20#define S5P_APLL_LOCK S5P_CLKREG(0x00) 22#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x04) 23#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x08) 24#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
@@ -68,4 +70,8 @@
68#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) 70#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
69#define S5P_CLKDIV1_PCLKD1_SHIFT (16) 71#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
70 72
73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
74
75#define S5PC100_SWRESET_RESETVAL 0xc100
76
71#endif /* __ASM_ARCH_REGS_CLOCK_H */ 77#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index 68666913354c..dd6295e1251d 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h 1/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
@@ -12,7 +12,7 @@
12#include <mach/map.h> 12#include <mach/map.h>
13 13
14/* S5PC100 */ 14/* S5PC100 */
15#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO 15#define S5PC100_GPIO_BASE S5P_VA_GPIO
16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) 16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) 17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) 18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
@@ -47,24 +47,29 @@
47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) 47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) 48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) 49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
50#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
51 50
52#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) 51#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
53#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) 52#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
54 53
55/* PDNEN */ 54#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
56#define S5PC100_PDNEN_CFG_PDNEN (1 << 1) 55#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
57#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
58#define S5PC100_PDNEN_POWERDOWN (1 << 0)
59#define S5PC100_PDNEN_NORMAL (0 << 0)
60 56
61/* Common part */ 57#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
62/* External interrupt base is same at both s5pc100 and s5pc110 */ 58#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
63#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE)
64 59
65#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 60#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
66#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 61#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
67#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 62
63#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
64
65#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
66
67/* values for S5P_EXTINT0 */
68#define S5P_EXTINT_LOWLEV (0x00)
69#define S5P_EXTINT_HILEV (0x01)
70#define S5P_EXTINT_FALLEDGE (0x02)
71#define S5P_EXTINT_RISEEDGE (0x03)
72#define S5P_EXTINT_BOTHEDGE (0x04)
68 73
69#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ 74#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
70 75
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
index 751ac15438c8..4d9036d0f288 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -3,7 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC1XX - IRQ register definitions 6 * S5PC100 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -16,9 +16,4 @@
16#include <mach/map.h> 16#include <mach/map.h>
17#include <asm/hardware/vic.h> 17#include <asm/hardware/vic.h>
18 18
19/* interrupt controller */
20#define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0))
21#define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1))
22#define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2))
23
24#endif /* __ASM_ARCH_REGS_IRQ_H */ 19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..65e426370bb2
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5PC100_PLAT_SPI_CLKS_H
12#define __S5PC100_PLAT_SPI_CLKS_H __FILE__
13
14#define S5PC100_SPI_SRCCLK_PCLK 0
15#define S5PC100_SPI_SRCCLK_48M 1
16#define S5PC100_SPI_SRCCLK_SPIBUS 2
17
18#endif /* __S5PC100_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index f0d31a2a598c..681f626a9ae1 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -3,7 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC1XX - system implementation 6 * S5PC100 - system implementation
7 * 7 *
8 * Based on mach-s3c6400/include/mach/system.h 8 * Based on mach-s3c6400/include/mach/system.h
9 */ 9 */
@@ -13,14 +13,11 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/map.h> 15#include <mach/map.h>
16#include <plat/regs-clock.h> 16#include <mach/regs-clock.h>
17
18void (*s5pc1xx_idle)(void);
19 17
20static void arch_idle(void) 18static void arch_idle(void)
21{ 19{
22 if (s5pc1xx_idle) 20 /* nothing here yet */
23 s5pc1xx_idle();
24} 21}
25 22
26static void arch_reset(char mode, const char *cmd) 23static void arch_reset(char mode, const char *cmd)
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index f338c9eec717..20f68730ed18 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -20,8 +20,8 @@
20 */ 20 */
21static inline u32 s3c24xx_ostimer_pending(void) 21static inline u32 s3c24xx_ostimer_pending(void)
22{ 22{
23 u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); 23 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
24 return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); 24 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
25} 25}
26 26
27#define TICK_MAX (0xffffffff) 27#define TICK_MAX (0xffffffff)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 10:17:20 -0500