diff options
author | Joonyoung Shim <jy0922.shim@samsung.com> | 2010-09-30 22:18:05 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-20 18:54:57 -0400 |
commit | 7e47935bb7190cd4bbc6fa4023b64b4785a2bcdc (patch) | |
tree | 47a8137ef0a4eb06835b9a6a9d01e84adc3d4470 /arch/arm/mach-s5pc100/gpiolib.c | |
parent | 5fdc97b5d95aa8175c085545a4c37bccd45dd950 (diff) |
ARM: S5PC100: Use generic S5P GPIO Interrupt interface
S5PC100 SoC can use common S5P GPIO interrupt code. This patch
removes specific S5PC100 gpio interrupts code and adds required
defines and code to make use of common S5P code.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100/gpiolib.c')
-rw-r--r-- | arch/arm/mach-s5pc100/gpiolib.c | 45 |
1 files changed, 11 insertions, 34 deletions
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 0fab7f2cd8bf..5811578ad4e4 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c | |||
@@ -61,11 +61,6 @@ | |||
61 | * L3 8 4Bit None | 61 | * L3 8 4Bit None |
62 | */ | 62 | */ |
63 | 63 | ||
64 | static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) | ||
65 | { | ||
66 | return S3C_IRQ_GPIO(chip->base + offset); | ||
67 | } | ||
68 | |||
69 | static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) | 64 | static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) |
70 | { | 65 | { |
71 | int base; | 66 | int base; |
@@ -232,6 +227,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
232 | .base = S5PC100_GPH0(0), | 227 | .base = S5PC100_GPH0(0), |
233 | .ngpio = S5PC100_GPIO_H0_NR, | 228 | .ngpio = S5PC100_GPIO_H0_NR, |
234 | .label = "GPH0", | 229 | .label = "GPH0", |
230 | .to_irq = s5pc100_gpiolib_to_eint, | ||
235 | }, | 231 | }, |
236 | }, { | 232 | }, { |
237 | .base = S5PC100_GPH1_BASE, | 233 | .base = S5PC100_GPH1_BASE, |
@@ -240,6 +236,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
240 | .base = S5PC100_GPH1(0), | 236 | .base = S5PC100_GPH1(0), |
241 | .ngpio = S5PC100_GPIO_H1_NR, | 237 | .ngpio = S5PC100_GPIO_H1_NR, |
242 | .label = "GPH1", | 238 | .label = "GPH1", |
239 | .to_irq = s5pc100_gpiolib_to_eint, | ||
243 | }, | 240 | }, |
244 | }, { | 241 | }, { |
245 | .base = S5PC100_GPH2_BASE, | 242 | .base = S5PC100_GPH2_BASE, |
@@ -248,6 +245,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
248 | .base = S5PC100_GPH2(0), | 245 | .base = S5PC100_GPH2(0), |
249 | .ngpio = S5PC100_GPIO_H2_NR, | 246 | .ngpio = S5PC100_GPIO_H2_NR, |
250 | .label = "GPH2", | 247 | .label = "GPH2", |
248 | .to_irq = s5pc100_gpiolib_to_eint, | ||
251 | }, | 249 | }, |
252 | }, { | 250 | }, { |
253 | .base = S5PC100_GPH3_BASE, | 251 | .base = S5PC100_GPH3_BASE, |
@@ -256,6 +254,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
256 | .base = S5PC100_GPH3(0), | 254 | .base = S5PC100_GPH3(0), |
257 | .ngpio = S5PC100_GPIO_H3_NR, | 255 | .ngpio = S5PC100_GPIO_H3_NR, |
258 | .label = "GPH3", | 256 | .label = "GPH3", |
257 | .to_irq = s5pc100_gpiolib_to_eint, | ||
259 | }, | 258 | }, |
260 | }, { | 259 | }, { |
261 | .base = S5PC100_GPI_BASE, | 260 | .base = S5PC100_GPI_BASE, |
@@ -380,47 +379,25 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
380 | }, | 379 | }, |
381 | }; | 380 | }; |
382 | 381 | ||
383 | /* FIXME move from irq-gpio.c */ | ||
384 | extern struct irq_chip s5pc100_gpioint; | ||
385 | extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); | ||
386 | |||
387 | static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) | ||
388 | { | ||
389 | /* Interrupt */ | ||
390 | if (chip->config == &gpio_cfg) { | ||
391 | int i, irq; | ||
392 | |||
393 | chip->chip.to_irq = s5pc100_gpiolib_to_irq; | ||
394 | |||
395 | for (i = 0; i < chip->chip.ngpio; i++) { | ||
396 | irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; | ||
397 | set_irq_chip(irq, &s5pc100_gpioint); | ||
398 | set_irq_data(irq, &chip->chip); | ||
399 | set_irq_handler(irq, handle_level_irq); | ||
400 | set_irq_flags(irq, IRQF_VALID); | ||
401 | } | ||
402 | } else if (chip->config == &gpio_cfg_eint) { | ||
403 | chip->chip.to_irq = s5pc100_gpiolib_to_eint; | ||
404 | } | ||
405 | } | ||
406 | |||
407 | static __init int s5pc100_gpiolib_init(void) | 382 | static __init int s5pc100_gpiolib_init(void) |
408 | { | 383 | { |
409 | struct s3c_gpio_chip *chip; | 384 | struct s3c_gpio_chip *chip; |
410 | int nr_chips; | 385 | int nr_chips; |
386 | int gpioint_group = 0; | ||
411 | 387 | ||
412 | chip = s5pc100_gpio_chips; | 388 | chip = s5pc100_gpio_chips; |
413 | nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); | 389 | nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); |
414 | 390 | ||
415 | for (; nr_chips > 0; nr_chips--, chip++) | 391 | for (; nr_chips > 0; nr_chips--, chip++) { |
416 | s5pc100_gpiolib_link(chip); | 392 | if (chip->config == &gpio_cfg) { |
393 | /* gpio interrupts */ | ||
394 | chip->group = gpioint_group++; | ||
395 | } | ||
396 | } | ||
417 | 397 | ||
418 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, | 398 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, |
419 | ARRAY_SIZE(s5pc100_gpio_chips)); | 399 | ARRAY_SIZE(s5pc100_gpio_chips)); |
420 | 400 | ||
421 | /* Interrupt */ | ||
422 | set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); | ||
423 | |||
424 | return 0; | 401 | return 0; |
425 | } | 402 | } |
426 | core_initcall(s5pc100_gpiolib_init); | 403 | core_initcall(s5pc100_gpiolib_init); |