diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-02-27 12:22:36 -0500 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-02-29 07:03:08 -0500 |
commit | 7eca30aef7961e68ad74c0ef920546c2be7f6579 (patch) | |
tree | d7161459a86134bee58b8a0980a15b66839467aa /arch/arm/mach-s5pc100/dma.c | |
parent | d65b4e98d7ea3038b767b70fe8be959b2913f16d (diff) | |
parent | d5e5a7f987458f42f24a557a0f4e35f94c43fc09 (diff) |
Merge branch 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91 into at91/staging/base2+cleanup
* 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91: (20 commits)
ARM: at91: properly sort dtb files in Makefile.boot
ARM: at91: add at91sam9g25ek.dts in Makefile.boot
ARM: at91/board-dt: drop default console
Atmel: move console default platform_device to serial driver
ARM: at91: merge SRAM Memory banks thanks to mirroring
ARM: at91: finally drop at91_sys_read/write
ARM: at91/rtc-at91sam9: pass the GPBR to use via resources
ARM: at91:rtc/rtc-at91sam9: ioremap register bank
ARM: at91/rtc-at91sam9: each SoC can select the RTT device to use
ARM: at91/PMC: make register base soc independent
ARM: at91/PMC: move assignment out of printf
ARM: at91/pm_slowclock: add runtime detection of memory contoller
ARM: at91: make sdram/ddr register base soc independent
ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h
ARM: at91/pm_slowclock: function slow_clock() accepts parameters
ARM: at91/pm_slowclock: rename register to named define
ARM: at91/ST: remove not needed casts
ARM: at91: make ST (System Timer) soc independent
ARM: at91: make matrix register base soc independent
ARM: at91/at91x40: remove use of at91_sys_read/write
Based on top of the at91/9x5, rmk/for-armsoc, at91/device-board,
at91/pm_cleanup and at91/base.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-s5pc100/dma.c')
-rw-r--r-- | arch/arm/mach-s5pc100/dma.c | 38 |
1 files changed, 6 insertions, 32 deletions
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index c841f4d313f2..96b1ab3dcd48 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c | |||
@@ -73,21 +73,8 @@ struct dma_pl330_platdata s5pc100_pdma0_pdata = { | |||
73 | .peri_id = pdma0_peri, | 73 | .peri_id = pdma0_peri, |
74 | }; | 74 | }; |
75 | 75 | ||
76 | struct amba_device s5pc100_device_pdma0 = { | 76 | AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0, |
77 | .dev = { | 77 | {IRQ_PDMA0}, &s5pc100_pdma0_pdata); |
78 | .init_name = "dma-pl330.0", | ||
79 | .dma_mask = &dma_dmamask, | ||
80 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
81 | .platform_data = &s5pc100_pdma0_pdata, | ||
82 | }, | ||
83 | .res = { | ||
84 | .start = S5PC100_PA_PDMA0, | ||
85 | .end = S5PC100_PA_PDMA0 + SZ_4K, | ||
86 | .flags = IORESOURCE_MEM, | ||
87 | }, | ||
88 | .irq = {IRQ_PDMA0, NO_IRQ}, | ||
89 | .periphid = 0x00041330, | ||
90 | }; | ||
91 | 78 | ||
92 | u8 pdma1_peri[] = { | 79 | u8 pdma1_peri[] = { |
93 | DMACH_UART0_RX, | 80 | DMACH_UART0_RX, |
@@ -127,31 +114,18 @@ struct dma_pl330_platdata s5pc100_pdma1_pdata = { | |||
127 | .peri_id = pdma1_peri, | 114 | .peri_id = pdma1_peri, |
128 | }; | 115 | }; |
129 | 116 | ||
130 | struct amba_device s5pc100_device_pdma1 = { | 117 | AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1, |
131 | .dev = { | 118 | {IRQ_PDMA1}, &s5pc100_pdma1_pdata); |
132 | .init_name = "dma-pl330.1", | ||
133 | .dma_mask = &dma_dmamask, | ||
134 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
135 | .platform_data = &s5pc100_pdma1_pdata, | ||
136 | }, | ||
137 | .res = { | ||
138 | .start = S5PC100_PA_PDMA1, | ||
139 | .end = S5PC100_PA_PDMA1 + SZ_4K, | ||
140 | .flags = IORESOURCE_MEM, | ||
141 | }, | ||
142 | .irq = {IRQ_PDMA1, NO_IRQ}, | ||
143 | .periphid = 0x00041330, | ||
144 | }; | ||
145 | 119 | ||
146 | static int __init s5pc100_dma_init(void) | 120 | static int __init s5pc100_dma_init(void) |
147 | { | 121 | { |
148 | dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); | 122 | dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); |
149 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); | 123 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); |
150 | amba_device_register(&s5pc100_device_pdma0, &iomem_resource); | 124 | amba_device_register(&s5pc100_pdma0_device, &iomem_resource); |
151 | 125 | ||
152 | dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); | 126 | dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); |
153 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); | 127 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); |
154 | amba_device_register(&s5pc100_device_pdma1, &iomem_resource); | 128 | amba_device_register(&s5pc100_pdma1_device, &iomem_resource); |
155 | 129 | ||
156 | return 0; | 130 | return 0; |
157 | } | 131 | } |