diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-01 07:50:20 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-22 22:50:59 -0400 |
commit | e27ecd7306992fbe58ab03f20aa3452a8b40499a (patch) | |
tree | 8823d4aa7e17f9f1741a1673d20b919be590700a /arch/arm/mach-s5pc100/dev-spi.c | |
parent | 54bce6c73dcd6d150d917e954154521de116e17b (diff) |
ARM: S5PC100: 2nd Change to using s3c_gpio_cfgall_range()
This patch changes the code setting range of GPIO pins' configuration and
pull state to use the recently introduced s3c_gpio_cfgpin_range().
NOTE: This is for missed things from the previous patch.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100/dev-spi.c')
-rw-r--r-- | arch/arm/mach-s5pc100/dev-spi.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c index c1c5aed07910..57b19794d9bb 100644 --- a/arch/arm/mach-s5pc100/dev-spi.c +++ b/arch/arm/mach-s5pc100/dev-spi.c | |||
@@ -38,25 +38,20 @@ static int s5pc100_spi_cfg_gpio(struct platform_device *pdev) | |||
38 | { | 38 | { |
39 | switch (pdev->id) { | 39 | switch (pdev->id) { |
40 | case 0: | 40 | case 0: |
41 | s3c_gpio_cfgpin_range(S5PC100_GPB(0), 3, S3C_GPIO_SFN(2)); | 41 | s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, |
42 | s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP); | 42 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
43 | s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP); | ||
44 | s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP); | ||
45 | break; | 43 | break; |
46 | 44 | ||
47 | case 1: | 45 | case 1: |
48 | s3c_gpio_cfgpin_range(S5PC100_GPB(4), 3, S3C_GPIO_SFN(2)); | 46 | s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, |
49 | s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP); | 47 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
50 | s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP); | ||
51 | s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP); | ||
52 | break; | 48 | break; |
53 | 49 | ||
54 | case 2: | 50 | case 2: |
55 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); | 51 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); |
56 | s3c_gpio_cfgpin_range(S5PC100_GPB(2), 2, S3C_GPIO_SFN(3)); | ||
57 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); | 52 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); |
58 | s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP); | 53 | s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, |
59 | s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP); | 54 | S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); |
60 | break; | 55 | break; |
61 | 56 | ||
62 | default: | 57 | default: |