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authorPadmavathi Venna <padma.v@samsung.com>2011-12-22 20:14:31 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-12-22 20:49:53 -0500
commit875a59374cd10200ac24f03877ccd8f73af590cc (patch)
treea7a933bd6a567fd2daa51439bcb17597aa337814 /arch/arm/mach-s5pc100/dev-spi.c
parenta153e31abb01484d0088ac28425dc98204848ad4 (diff)
ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung
SPI platform device definitions consolidated from respective machine folder to plat-samsung Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100/dev-spi.c')
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c220
1 files changed, 0 insertions, 220 deletions
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index 155f50da2d78..000000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/spi-clocks.h>
18#include <mach/irqs.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22#include <plat/irqs.h>
23
24/* SPI Controller platform_devices */
25
26/* Since we emulate multi-cs capability, we do not touch the CS.
27 * The emulated CS is toggled by board specific mechanism, as it can
28 * be either some immediate GPIO or some signal out of some other
29 * chip in between ... or some yet another way.
30 * We simply do not assume anything about CS.
31 */
32static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
33{
34 switch (pdev->id) {
35 case 0:
36 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
37 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
38 break;
39
40 case 1:
41 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 break;
44
45 case 2:
46 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
47 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
48 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
49 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
50 break;
51
52 default:
53 dev_err(&pdev->dev, "Invalid SPI Controller number!");
54 return -EINVAL;
55 }
56
57 return 0;
58}
59
60static struct resource s5pc100_spi0_resource[] = {
61 [0] = {
62 .start = S5PC100_PA_SPI0,
63 .end = S5PC100_PA_SPI0 + 0x100 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = DMACH_SPI0_TX,
68 .end = DMACH_SPI0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 [2] = {
72 .start = DMACH_SPI0_RX,
73 .end = DMACH_SPI0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76 [3] = {
77 .start = IRQ_SPI0,
78 .end = IRQ_SPI0,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
84 .cfg_gpio = s5pc100_spi_cfg_gpio,
85 .fifo_lvl_mask = 0x7f,
86 .rx_lvl_offset = 13,
87 .high_speed = 1,
88 .tx_st_done = 21,
89};
90
91static u64 spi_dmamask = DMA_BIT_MASK(32);
92
93struct platform_device s5pc100_device_spi0 = {
94 .name = "s3c64xx-spi",
95 .id = 0,
96 .num_resources = ARRAY_SIZE(s5pc100_spi0_resource),
97 .resource = s5pc100_spi0_resource,
98 .dev = {
99 .dma_mask = &spi_dmamask,
100 .coherent_dma_mask = DMA_BIT_MASK(32),
101 .platform_data = &s5pc100_spi0_pdata,
102 },
103};
104
105static struct resource s5pc100_spi1_resource[] = {
106 [0] = {
107 .start = S5PC100_PA_SPI1,
108 .end = S5PC100_PA_SPI1 + 0x100 - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = DMACH_SPI1_TX,
113 .end = DMACH_SPI1_TX,
114 .flags = IORESOURCE_DMA,
115 },
116 [2] = {
117 .start = DMACH_SPI1_RX,
118 .end = DMACH_SPI1_RX,
119 .flags = IORESOURCE_DMA,
120 },
121 [3] = {
122 .start = IRQ_SPI1,
123 .end = IRQ_SPI1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
129 .cfg_gpio = s5pc100_spi_cfg_gpio,
130 .fifo_lvl_mask = 0x7f,
131 .rx_lvl_offset = 13,
132 .high_speed = 1,
133 .tx_st_done = 21,
134};
135
136struct platform_device s5pc100_device_spi1 = {
137 .name = "s3c64xx-spi",
138 .id = 1,
139 .num_resources = ARRAY_SIZE(s5pc100_spi1_resource),
140 .resource = s5pc100_spi1_resource,
141 .dev = {
142 .dma_mask = &spi_dmamask,
143 .coherent_dma_mask = DMA_BIT_MASK(32),
144 .platform_data = &s5pc100_spi1_pdata,
145 },
146};
147
148static struct resource s5pc100_spi2_resource[] = {
149 [0] = {
150 .start = S5PC100_PA_SPI2,
151 .end = S5PC100_PA_SPI2 + 0x100 - 1,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = DMACH_SPI2_TX,
156 .end = DMACH_SPI2_TX,
157 .flags = IORESOURCE_DMA,
158 },
159 [2] = {
160 .start = DMACH_SPI2_RX,
161 .end = DMACH_SPI2_RX,
162 .flags = IORESOURCE_DMA,
163 },
164 [3] = {
165 .start = IRQ_SPI2,
166 .end = IRQ_SPI2,
167 .flags = IORESOURCE_IRQ,
168 },
169};
170
171static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
172 .cfg_gpio = s5pc100_spi_cfg_gpio,
173 .fifo_lvl_mask = 0x7f,
174 .rx_lvl_offset = 13,
175 .high_speed = 1,
176 .tx_st_done = 21,
177};
178
179struct platform_device s5pc100_device_spi2 = {
180 .name = "s3c64xx-spi",
181 .id = 2,
182 .num_resources = ARRAY_SIZE(s5pc100_spi2_resource),
183 .resource = s5pc100_spi2_resource,
184 .dev = {
185 .dma_mask = &spi_dmamask,
186 .coherent_dma_mask = DMA_BIT_MASK(32),
187 .platform_data = &s5pc100_spi2_pdata,
188 },
189};
190
191void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
192{
193 struct s3c64xx_spi_info *pd;
194
195 /* Reject invalid configuration */
196 if (!num_cs || src_clk_nr < 0
197 || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
198 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
199 return;
200 }
201
202 switch (cntrlr) {
203 case 0:
204 pd = &s5pc100_spi0_pdata;
205 break;
206 case 1:
207 pd = &s5pc100_spi1_pdata;
208 break;
209 case 2:
210 pd = &s5pc100_spi2_pdata;
211 break;
212 default:
213 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
214 __func__, cntrlr);
215 return;
216 }
217
218 pd->num_cs = num_cs;
219 pd->src_clk_nr = src_clk_nr;
220}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 14:29:42 -0400