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authorKukjin Kim <kgene.kim@samsung.com>2010-09-08 03:23:05 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-18 05:33:03 -0400
commit5dd33d89f4700990e00731a971754ecb08ab7022 (patch)
tree29ce0642e6af90d92477db7c276c99e0956b41d8 /arch/arm/mach-s5p64x0
parent2853a0efc3031dec88b47bbc50b8a6b3fe9e3cac (diff)
ARM: S5P64X0: Move GPIO support files for merge S5P64X0
This patch moves S5P6440 GPIO support files from mach-s5p6440 into the new mach-s5p64x0 for merge S5P6440 and S5P6450 SocS. NOTE: Not supported S5P6450 GPIO yet. Will be supported soon. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0')
-rw-r--r--arch/arm/mach-s5p64x0/gpio.c347
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/gpio.h139
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h62
3 files changed, 548 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
new file mode 100644
index 000000000000..131eefe0c9f2
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -0,0 +1,347 @@
1/* linux/arch/arm/mach-s5p64x0/gpio.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <mach/regs-gpio.h>
20
21#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h>
24
25/* To be implemented S5P6450 GPIO */
26
27/*
28 * S5P6440 GPIO bank summary:
29 *
30 * Bank GPIOs Style SlpCon ExtInt Group
31 * A 6 4Bit Yes 1
32 * B 7 4Bit Yes 1
33 * C 8 4Bit Yes 2
34 * F 2 2Bit Yes 4 [1]
35 * G 7 4Bit Yes 5
36 * H 10 4Bit[2] Yes 6
37 * I 16 2Bit Yes None
38 * J 12 2Bit Yes None
39 * N 16 2Bit No IRQ_EINT
40 * P 8 2Bit Yes 8
41 * R 15 4Bit[2] Yes 8
42 *
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1
45 */
46
47static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
48 unsigned int offset)
49{
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 void __iomem *regcon = base;
53 unsigned long con;
54 unsigned long flags;
55
56 switch (offset) {
57 case 6:
58 offset += 1;
59 case 0:
60 case 1:
61 case 2:
62 case 3:
63 case 4:
64 case 5:
65 regcon -= 4;
66 break;
67 default:
68 offset -= 7;
69 break;
70 }
71
72 s3c_gpio_lock(ourchip, flags);
73
74 con = __raw_readl(regcon);
75 con &= ~(0xf << con_4bit_shift(offset));
76 __raw_writel(con, regcon);
77
78 s3c_gpio_unlock(ourchip, flags);
79
80 return 0;
81}
82
83static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
84 unsigned int offset, int value)
85{
86 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
87 void __iomem *base = ourchip->base;
88 void __iomem *regcon = base;
89 unsigned long con;
90 unsigned long dat;
91 unsigned long flags;
92 unsigned con_offset = offset;
93
94 switch (con_offset) {
95 case 6:
96 con_offset += 1;
97 case 0:
98 case 1:
99 case 2:
100 case 3:
101 case 4:
102 case 5:
103 regcon -= 4;
104 break;
105 default:
106 con_offset -= 7;
107 break;
108 }
109
110 s3c_gpio_lock(ourchip, flags);
111
112 con = __raw_readl(regcon);
113 con &= ~(0xf << con_4bit_shift(con_offset));
114 con |= 0x1 << con_4bit_shift(con_offset);
115
116 dat = __raw_readl(base + GPIODAT_OFF);
117 if (value)
118 dat |= 1 << offset;
119 else
120 dat &= ~(1 << offset);
121
122 __raw_writel(con, regcon);
123 __raw_writel(dat, base + GPIODAT_OFF);
124
125 s3c_gpio_unlock(ourchip, flags);
126
127 return 0;
128}
129
130int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
131 unsigned int off, unsigned int cfg)
132{
133 void __iomem *reg = chip->base;
134 unsigned int shift;
135 unsigned long flags;
136 u32 con;
137
138 switch (off) {
139 case 0:
140 case 1:
141 case 2:
142 case 3:
143 case 4:
144 case 5:
145 shift = (off & 7) * 4;
146 reg -= 4;
147 break;
148 case 6:
149 shift = ((off + 1) & 7) * 4;
150 reg -= 4;
151 default:
152 shift = ((off + 1) & 7) * 4;
153 break;
154 }
155
156 if (s3c_gpio_is_cfg_special(cfg)) {
157 cfg &= 0xf;
158 cfg <<= shift;
159 }
160
161 s3c_gpio_lock(chip, flags);
162
163 con = __raw_readl(reg);
164 con &= ~(0xf << shift);
165 con |= cfg;
166 __raw_writel(con, reg);
167
168 s3c_gpio_unlock(chip, flags);
169
170 return 0;
171}
172
173static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
174 {
175 .cfg_eint = 0,
176 }, {
177 .cfg_eint = 7,
178 }, {
179 .cfg_eint = 3,
180 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
181 }, {
182 .cfg_eint = 0,
183 .set_config = s3c_gpio_setcfg_s3c24xx,
184 .get_config = s3c_gpio_getcfg_s3c24xx,
185 }, {
186 .cfg_eint = 2,
187 .set_config = s3c_gpio_setcfg_s3c24xx,
188 .get_config = s3c_gpio_getcfg_s3c24xx,
189 }, {
190 .cfg_eint = 3,
191 .set_config = s3c_gpio_setcfg_s3c24xx,
192 .get_config = s3c_gpio_getcfg_s3c24xx,
193 },
194};
195
196static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
197 {
198 .base = S5P6440_GPA_BASE,
199 .config = &s5p64x0_gpio_cfgs[1],
200 .chip = {
201 .base = S5P6440_GPA(0),
202 .ngpio = S5P6440_GPIO_A_NR,
203 .label = "GPA",
204 },
205 }, {
206 .base = S5P6440_GPB_BASE,
207 .config = &s5p64x0_gpio_cfgs[1],
208 .chip = {
209 .base = S5P6440_GPB(0),
210 .ngpio = S5P6440_GPIO_B_NR,
211 .label = "GPB",
212 },
213 }, {
214 .base = S5P6440_GPC_BASE,
215 .config = &s5p64x0_gpio_cfgs[1],
216 .chip = {
217 .base = S5P6440_GPC(0),
218 .ngpio = S5P6440_GPIO_C_NR,
219 .label = "GPC",
220 },
221 }, {
222 .base = S5P6440_GPG_BASE,
223 .config = &s5p64x0_gpio_cfgs[1],
224 .chip = {
225 .base = S5P6440_GPG(0),
226 .ngpio = S5P6440_GPIO_G_NR,
227 .label = "GPG",
228 },
229 },
230};
231
232static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
233 {
234 .base = S5P6440_GPH_BASE + 0x4,
235 .config = &s5p64x0_gpio_cfgs[1],
236 .chip = {
237 .base = S5P6440_GPH(0),
238 .ngpio = S5P6440_GPIO_H_NR,
239 .label = "GPH",
240 },
241 },
242};
243
244static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
245 {
246 .base = S5P6440_GPR_BASE + 0x4,
247 .config = &s5p64x0_gpio_cfgs[2],
248 .chip = {
249 .base = S5P6440_GPR(0),
250 .ngpio = S5P6440_GPIO_R_NR,
251 .label = "GPR",
252 },
253 },
254};
255
256static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
257 {
258 .base = S5P6440_GPF_BASE,
259 .config = &s5p64x0_gpio_cfgs[5],
260 .chip = {
261 .base = S5P6440_GPF(0),
262 .ngpio = S5P6440_GPIO_F_NR,
263 .label = "GPF",
264 },
265 }, {
266 .base = S5P6440_GPI_BASE,
267 .config = &s5p64x0_gpio_cfgs[3],
268 .chip = {
269 .base = S5P6440_GPI(0),
270 .ngpio = S5P6440_GPIO_I_NR,
271 .label = "GPI",
272 },
273 }, {
274 .base = S5P6440_GPJ_BASE,
275 .config = &s5p64x0_gpio_cfgs[3],
276 .chip = {
277 .base = S5P6440_GPJ(0),
278 .ngpio = S5P6440_GPIO_J_NR,
279 .label = "GPJ",
280 },
281 }, {
282 .base = S5P6440_GPN_BASE,
283 .config = &s5p64x0_gpio_cfgs[4],
284 .chip = {
285 .base = S5P6440_GPN(0),
286 .ngpio = S5P6440_GPIO_N_NR,
287 .label = "GPN",
288 },
289 }, {
290 .base = S5P6440_GPP_BASE,
291 .config = &s5p64x0_gpio_cfgs[5],
292 .chip = {
293 .base = S5P6440_GPP(0),
294 .ngpio = S5P6440_GPIO_P_NR,
295 .label = "GPP",
296 },
297 },
298};
299
300void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
301{
302 for (; nr_chips > 0; nr_chips--, chipcfg++) {
303 if (!chipcfg->set_config)
304 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
305 if (!chipcfg->get_config)
306 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
307 if (!chipcfg->set_pull)
308 chipcfg->set_pull = s3c_gpio_setpull_updown;
309 if (!chipcfg->get_pull)
310 chipcfg->get_pull = s3c_gpio_getpull_updown;
311 }
312}
313
314static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
315 int nr_chips)
316{
317 for (; nr_chips > 0; nr_chips--, chip++) {
318 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
319 chip->chip.direction_output =
320 s5p64x0_gpiolib_rbank_4bit2_output;
321 s3c_gpiolib_add(chip);
322 }
323}
324
325static int __init s5p6440_gpiolib_init(void)
326{
327 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
328 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
329
330 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
331 ARRAY_SIZE(s5p64x0_gpio_cfgs));
332
333 for (; nr_chips > 0; nr_chips--, chips++)
334 s3c_gpiolib_add(chips);
335
336 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
337 ARRAY_SIZE(s5p6440_gpio_4bit));
338
339 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
340 ARRAY_SIZE(s5p6440_gpio_4bit2));
341
342 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
343 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
344
345 return 0;
346}
347arch_initcall(s5p6440_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 000000000000..5486c8f01f1d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22
23#define S5P6440_GPIO_A_NR (6)
24#define S5P6440_GPIO_B_NR (7)
25#define S5P6440_GPIO_C_NR (8)
26#define S5P6440_GPIO_F_NR (2)
27#define S5P6440_GPIO_G_NR (7)
28#define S5P6440_GPIO_H_NR (10)
29#define S5P6440_GPIO_I_NR (16)
30#define S5P6440_GPIO_J_NR (12)
31#define S5P6440_GPIO_N_NR (16)
32#define S5P6440_GPIO_P_NR (8)
33#define S5P6440_GPIO_R_NR (15)
34
35#define S5P6450_GPIO_A_NR (6)
36#define S5P6450_GPIO_B_NR (7)
37#define S5P6450_GPIO_C_NR (8)
38#define S5P6450_GPIO_D_NR (8)
39#define S5P6450_GPIO_F_NR (2)
40#define S5P6450_GPIO_G_NR (14)
41#define S5P6450_GPIO_H_NR (10)
42#define S5P6450_GPIO_I_NR (16)
43#define S5P6450_GPIO_J_NR (12)
44#define S5P6450_GPIO_K_NR (5)
45#define S5P6450_GPIO_N_NR (16)
46#define S5P6450_GPIO_P_NR (11)
47#define S5P6450_GPIO_Q_NR (14)
48#define S5P6450_GPIO_R_NR (15)
49#define S5P6450_GPIO_S_NR (8)
50
51/* GPIO bank numbers */
52
53/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
54 * space for debugging purposes so that any accidental
55 * change from one gpio bank to another can be caught.
56*/
57
58#define S5P64X0_GPIO_NEXT(__gpio) \
59 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
60
61enum s5p6440_gpio_number {
62 S5P6440_GPIO_A_START = 0,
63 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
64 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
65 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
66 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
67 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
68 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
69 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
70 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
71 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
72 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
73};
74
75enum s5p6450_gpio_number {
76 S5P6450_GPIO_A_START = 0,
77 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
78 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
79 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
80 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
81 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
82 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
83 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
84 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
85 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
86 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
87 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
88 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
89 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
90 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
91};
92
93/* GPIO number definitions */
94
95#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
96#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
97#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
98#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
99#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
100#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
101#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
102#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
103#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
104#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
105#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
106
107#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
108#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
109#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
110#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
111#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
112#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
113#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
114#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
115#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
116#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
117#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
118#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
119#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
120#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
121#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
122
123/* the end of the S5P64X0 specific gpios */
124
125#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
126#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
127
128#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
129 S5P6440_GPIO_END : S5P6450_GPIO_END)
130
131#define S3C_GPIO_END S5P64X0_GPIO_END
132
133/* define the number of gpios we need to the one after the last GPIO range */
134
135#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
136
137#include <asm-generic/gpio.h>
138
139#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..85f448e20a8b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -0,0 +1,62 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18/* Will be implemented S5P6442 GPIOlib */
19
20/* Base addresses for each of the banks */
21
22#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000)
23#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020)
24#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040)
25#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0)
26#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0)
27#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0)
28#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100)
29#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120)
30#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830)
31#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160)
32#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290)
33
34#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900)
35#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910)
36#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914)
37#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920)
38#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
39
40/* for LCD */
41
42#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
43#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
44
45/*
46 * These set of macros are not really useful for the
47 * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
48 */
49
50#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
51#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
52#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
53
54/*
55 * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
56 */
57
58#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
59#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
60#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
61
62#endif /* __ASM_ARCH_REGS_GPIO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 16:34:22 -0500