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authorRajeshwari Shinde <rajeshwari.s@samsung.com>2011-12-26 02:31:02 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-12-26 02:31:02 -0500
commit0818c52756f46ab8f3e7d14a3a9e6e0a7d87b98f (patch)
tree7bbcdcb29b5c783261a4871676743a68b6c407d1 /arch/arm/mach-s5p64x0
parentebc433c2890f8ecad2da39fe2dbf2b6e7b309afa (diff)
ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names
Add support for lookup of sdhci-s3c controller clocks using generic names for S5P64X0 SoCs. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0')
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c72
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c72
2 files changed, 84 insertions, 60 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 73c7cc9ef0dd..c041ad7fbd60 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -379,36 +379,6 @@ static struct clksrc_sources clkset_audio = {
379static struct clksrc_clk clksrcs[] = { 379static struct clksrc_clk clksrcs[] = {
380 { 380 {
381 .clk = { 381 .clk = {
382 .name = "sclk_mmc",
383 .devname = "s3c-sdhci.0",
384 .ctrlbit = (1 << 24),
385 .enable = s5p64x0_sclk_ctrl,
386 },
387 .sources = &clkset_group1,
388 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
389 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
390 }, {
391 .clk = {
392 .name = "sclk_mmc",
393 .devname = "s3c-sdhci.1",
394 .ctrlbit = (1 << 25),
395 .enable = s5p64x0_sclk_ctrl,
396 },
397 .sources = &clkset_group1,
398 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
399 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
400 }, {
401 .clk = {
402 .name = "sclk_mmc",
403 .devname = "s3c-sdhci.2",
404 .ctrlbit = (1 << 26),
405 .enable = s5p64x0_sclk_ctrl,
406 },
407 .sources = &clkset_group1,
408 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
409 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
410 }, {
411 .clk = {
412 .name = "sclk_post", 382 .name = "sclk_post",
413 .ctrlbit = (1 << 10), 383 .ctrlbit = (1 << 10),
414 .enable = s5p64x0_sclk_ctrl, 384 .enable = s5p64x0_sclk_ctrl,
@@ -446,6 +416,42 @@ static struct clksrc_clk clksrcs[] = {
446 }, 416 },
447}; 417};
448 418
419static struct clksrc_clk clk_sclk_mmc0 = {
420 .clk = {
421 .name = "sclk_mmc",
422 .devname = "s3c-sdhci.0",
423 .ctrlbit = (1 << 24),
424 .enable = s5p64x0_sclk_ctrl,
425 },
426 .sources = &clkset_group1,
427 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
428 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
429};
430
431static struct clksrc_clk clk_sclk_mmc1 = {
432 .clk = {
433 .name = "sclk_mmc",
434 .devname = "s3c-sdhci.1",
435 .ctrlbit = (1 << 25),
436 .enable = s5p64x0_sclk_ctrl,
437 },
438 .sources = &clkset_group1,
439 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
440 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
441};
442
443static struct clksrc_clk clk_sclk_mmc2 = {
444 .clk = {
445 .name = "sclk_mmc",
446 .devname = "s3c-sdhci.2",
447 .ctrlbit = (1 << 26),
448 .enable = s5p64x0_sclk_ctrl,
449 },
450 .sources = &clkset_group1,
451 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
452 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
453};
454
449static struct clksrc_clk clk_sclk_uclk = { 455static struct clksrc_clk clk_sclk_uclk = {
450 .clk = { 456 .clk = {
451 .name = "uclk1", 457 .name = "uclk1",
@@ -503,6 +509,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
503 &clk_sclk_uclk, 509 &clk_sclk_uclk,
504 &clk_sclk_spi0, 510 &clk_sclk_spi0,
505 &clk_sclk_spi1, 511 &clk_sclk_spi1,
512 &clk_sclk_mmc0,
513 &clk_sclk_mmc1,
514 &clk_sclk_mmc2
506}; 515};
507 516
508static struct clk_lookup s5p6440_clk_lookup[] = { 517static struct clk_lookup s5p6440_clk_lookup[] = {
@@ -511,6 +520,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
511 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 520 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
512 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 521 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
513 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 522 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
523 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
524 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
525 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
514}; 526};
515 527
516void __init_or_cpufreq s5p6440_setup_clocks(void) 528void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 50f90cbf7798..b5087cb6e818 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -413,36 +413,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
413static struct clksrc_clk clksrcs[] = { 413static struct clksrc_clk clksrcs[] = {
414 { 414 {
415 .clk = { 415 .clk = {
416 .name = "sclk_mmc",
417 .devname = "s3c-sdhci.0",
418 .ctrlbit = (1 << 24),
419 .enable = s5p64x0_sclk_ctrl,
420 },
421 .sources = &clkset_group2,
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
424 }, {
425 .clk = {
426 .name = "sclk_mmc",
427 .devname = "s3c-sdhci.1",
428 .ctrlbit = (1 << 25),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_mmc",
437 .devname = "s3c-sdhci.2",
438 .ctrlbit = (1 << 26),
439 .enable = s5p64x0_sclk_ctrl,
440 },
441 .sources = &clkset_group2,
442 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, {
445 .clk = {
446 .name = "sclk_fimc", 416 .name = "sclk_fimc",
447 .ctrlbit = (1 << 10), 417 .ctrlbit = (1 << 10),
448 .enable = s5p64x0_sclk_ctrl, 418 .enable = s5p64x0_sclk_ctrl,
@@ -507,6 +477,42 @@ static struct clksrc_clk clksrcs[] = {
507 }, 477 },
508}; 478};
509 479
480static struct clksrc_clk clk_sclk_mmc0 = {
481 .clk = {
482 .name = "sclk_mmc",
483 .devname = "s3c-sdhci.0",
484 .ctrlbit = (1 << 24),
485 .enable = s5p64x0_sclk_ctrl,
486 },
487 .sources = &clkset_group2,
488 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
489 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
490};
491
492static struct clksrc_clk clk_sclk_mmc1 = {
493 .clk = {
494 .name = "sclk_mmc",
495 .devname = "s3c-sdhci.1",
496 .ctrlbit = (1 << 25),
497 .enable = s5p64x0_sclk_ctrl,
498 },
499 .sources = &clkset_group2,
500 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
501 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
502};
503
504static struct clksrc_clk clk_sclk_mmc2 = {
505 .clk = {
506 .name = "sclk_mmc",
507 .devname = "s3c-sdhci.2",
508 .ctrlbit = (1 << 26),
509 .enable = s5p64x0_sclk_ctrl,
510 },
511 .sources = &clkset_group2,
512 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
513 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
514};
515
510static struct clksrc_clk clk_sclk_uclk = { 516static struct clksrc_clk clk_sclk_uclk = {
511 .clk = { 517 .clk = {
512 .name = "uclk1", 518 .name = "uclk1",
@@ -546,6 +552,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
546 &clk_sclk_uclk, 552 &clk_sclk_uclk,
547 &clk_sclk_spi0, 553 &clk_sclk_spi0,
548 &clk_sclk_spi1, 554 &clk_sclk_spi1,
555 &clk_sclk_mmc0,
556 &clk_sclk_mmc1,
557 &clk_sclk_mmc2,
549}; 558};
550 559
551static struct clk_lookup s5p6450_clk_lookup[] = { 560static struct clk_lookup s5p6450_clk_lookup[] = {
@@ -554,6 +563,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 563 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 564 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 565 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
566 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
567 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
568 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
557}; 569};
558 570
559/* Clock initialization code */ 571/* Clock initialization code */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 09:03:16 -0500