Merge branch 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc

* 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc: (79 commits)
  ARM: SAMSUNG: Move fimc plat. device from board files to plat-samsung
  ARM: SAMSUNG: Cleanup resources by using macro
  ARM: SAMSUNG: Cleanup plat-samsung/devs.c and devs.h
  ARM: S5P: To merge devs.c files to one devs.c
  ARM: S3C64XX: To merge devs.c files to one devs.c
  ARM: S3C24XX: To merge s3c24xx devs.c files to one devs.c
  ARM: S5P64X0: Add Power Management support
  ARM: S5P: Make the sleep code common for S5P series SoCs
  ARM: S5P: Make the common S5P PM code conditionally compile
  ARM: SAMSUNG: Move S5P header files to plat-samsung
  ARM: SAMSUNG: Move S3C24XX header files to plat-samsung
  ARM: SAMSUNG: Moving each SoC support header files
  ARM: SAMSUNG: Consolidate plat/pll.h
  ARM: SAMSUNG: Consolidate plat/pwm-clock.h
  ARM: SAMSUNG: Cleanup mach/clkdev.h
  ARM: SAMSUNG: remove sdhci default configuration setup platform helper
  ARM: EXYNOS4: Add FIMC device on SMDKV310 board
  ARM: EXYNOS4: Add header file protection macros
  ARM: EXYNOS4: Add usb ehci device to the SMDKV310
  ARM: S3C2443: Add hsspi-clock from pclk and rename S3C2443 hsspi sclk
  ...

Fix up conflicts in
 - arch/arm/mach-exynos4/{Kconfig,clock.c}
	ARM_CPU_SUSPEND, various random device tables (gah!)
 - drivers/gpio/Makefile
	sa1100 gpio added, samsung gpio drivers merged

18 files changed, 677 insertions, 76 deletions

diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 9527ed24dbff..18690c5f99e6 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -11,6 +11,8 @@ config CPU_S5P6440
         bool
         select SAMSUNG_DMADEV
         select S5P_HRT
+        select S5P_SLEEP if PM
+        select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
@@ -18,9 +20,17 @@ config CPU_S5P6450
         bool
         select SAMSUNG_DMADEV
         select S5P_HRT
+        select S5P_SLEEP if PM
+        select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6450 CPU support
 
+config S5P64X0_SETUP_FB_24BPP
+        bool
+        help
+          Common setup code for S5P64X0 based boards with a LCD display
+          through RGB interface.
+
 config S5P64X0_SETUP_I2C1
         bool
         help
@@ -31,6 +41,7 @@ config S5P64X0_SETUP_I2C1
 config MACH_SMDK6440
         bool "SMDK6440"
         select CPU_S5P6440
+        select S3C_DEV_FB
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
@@ -39,6 +50,7 @@ config MACH_SMDK6440
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
         help
           Machine support for the Samsung SMDK6440
@@ -46,6 +58,7 @@ config MACH_SMDK6440
 config MACH_SMDK6450
         bool "SMDK6450"
         select CPU_S5P6450
+        select S3C_DEV_FB
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
@@ -54,6 +67,7 @@ config MACH_SMDK6450
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
         help
           Machine support for the Samsung SMDK6450
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 5f6afdf067ed..a1324d8dc4e0 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -12,10 +12,11 @@ obj-				:=
 
 # Core support for S5P64X0 system
 
-obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o gpiolib.o
+obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
 obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o irq-eint.o
 obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o
 obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
+obj-$(CONFIG_PM)                += pm.o irq-pm.o
 
 # machine support
 
@@ -28,3 +29,4 @@ obj-y				+= dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP)    += setup-fb-24bpp.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c1f548f69a0d..c54c65d511f0 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -147,6 +147,7 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 8),
         }, {
                 .name           = "dma",
+                .devname        = "dma-pl330",
                 .parent         = &clk_hclk_low.clk,
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 12),
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 3d9b60975570..2d04abfba12e 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -180,6 +180,7 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "dma",
+                .devname        = "dma-pl330",
                 .parent         = &clk_hclk_low.clk,
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 12),
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index 8a938542c54d..ecab40cf19ab 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -39,6 +39,7 @@
 #include <plat/s5p6440.h>
 #include <plat/s5p6450.h>
 #include <plat/adc-core.h>
+#include <plat/fb-core.h>
 
 /* Initial IO mappings */
 
@@ -109,6 +110,7 @@ void __init s5p6440_map_io(void)
 {
         /* initialize any device information early */
         s3c_adc_setname("s3c64xx-adc");
+        s3c_fb_setname("s5p64x0-fb");
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
@@ -119,6 +121,7 @@ void __init s5p6450_map_io(void)
 {
         /* initialize any device information early */
         s3c_adc_setname("s3c64xx-adc");
+        s3c_fb_setname("s5p64x0-fb");
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 5837a36ece8d..53982db9d259 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -87,6 +87,10 @@
 
 #define IRQ_I2S0                IRQ_I2SV40
 
+#define IRQ_LCD_FIFO            IRQ_DISPCON0
+#define IRQ_LCD_VSYNC           IRQ_DISPCON1
+#define IRQ_LCD_SYSTEM          IRQ_DISPCON2
+
 /* S5P6450 EINT feature will be added */
 
 /*
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c91257c7ca..4d3ac8a3709d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -47,6 +47,8 @@
 
 #define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
+#define S5P64X0_PA_FB           0xEE000000
+
 #define S5P64X0_PA_I2S          0xF2000000
 #define S5P6450_PA_I2S1         0xF2800000
 #define S5P6450_PA_I2S2         0xF2900000
@@ -64,6 +66,7 @@
 #define S3C_PA_IIC1             S5P6440_PA_IIC1
 #define S3C_PA_RTC              S5P64X0_PA_RTC
 #define S3C_PA_WDT              S5P64X0_PA_WDT
+#define S3C_PA_FB               S5P64X0_PA_FB
 
 #define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
 #define S5P_PA_SROMC            S5P64X0_PA_SROMC
@@ -85,5 +88,6 @@
 #define S5P_PA_UART5            S5P6450_PA_UART(5)
 
 #define S5P_SZ_UART             SZ_256
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
new file mode 100644
index 000000000000..e52f7545d3aa
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
+ *
+ * Based on PM core support for S3C64XX by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
+
+        /*
+         * As a note, since the S5P64X0 UARTs generally have multiple
+         * clock sources, we simply enable PCLK at the moment and hope
+         * that the resume settings for the UART are suitable for the
+         * use with PCLK.
+         */
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
+
+        __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
+        udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        /* VIC should have already been taken care of */
+
+        /* clear any pending EINT0 interrupts */
+        __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void) { }
+static inline void s3c_pm_arch_show_resume_irqs(void) { }
+
+/*
+ * make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on
+ */
+#define s3c_irqwake_eintallow   ((1 << 16) - 1)
+#define s3c_irqwake_intallow    (~0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                        struct pm_uart_save *save)
+{
+        u32 ucon = __raw_readl(regs + S3C2410_UCON);
+        u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+        u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+        u32 new_ucon;
+        u32 delta;
+
+        /*
+         * S5P64X0 UART blocks only support level interrupts, so ensure that
+         * when we restore unused UART blocks we force the level interrupt
+         * settings.
+         */
+        save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+        /*
+         * We have a constraint on changing the clock type of the UART
+         * between UCLKx and PCLK, so ensure that when we restore UCON
+         * that the CLK field is correctly modified if the bootloader
+         * has changed anything.
+         */
+        if (ucon_clk != save_clk) {
+                new_ucon = save->ucon;
+                delta = ucon_clk ^ save_clk;
+
+                /*
+                 * change from UCLKx => wrong PCLK,
+                 * either UCLK can be tested for by a bit-test
+                 * with UCLK0
+                 */
+                if (ucon_clk & S3C6400_UCON_UCLK0 &&
+                !(save_clk & S3C6400_UCON_UCLK0) &&
+                delta & S3C6400_UCON_PCLK2) {
+                        new_ucon &= ~S3C6400_UCON_UCLK0;
+                } else if (delta == S3C6400_UCON_PCLK2) {
+                        /*
+                         * as a precaution, don't change from
+                         * PCLK2 => PCLK or vice-versa
+                         */
+                        new_ucon ^= S3C6400_UCON_PCLK2;
+                }
+
+                S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+                        ucon, new_ucon, save->ucon);
+                save->ucon = new_ucon;
+        }
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+        /* ensure sleep mode has been cleared from the system */
+        __raw_writel(0, S5P64X0_SLPEN);
+}
+
+static inline void samsung_pm_saved_gpios(void)
+{
+        /*
+         * turn on the sleep mode and keep it there, as it seems that during
+         * suspend the xCON registers get re-set and thus you can end up with
+         * problems between going to sleep and resuming.
+         */
+        __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
+}
diff --git a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
deleted file mode 100644
index 19fff8b701c0..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S5P64X0 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return 0;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK 0
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index a133f22fa155..bd91112c813c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -41,17 +41,50 @@
 #define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
 #define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
 
+#define S5P64X0_AHB_CON0                S5P_CLKREG(0x100)
 #define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
 
 #define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
 #define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
 
 #define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_EINT_WAKEUP_MASK        S5P_CLKREG(0x808)
+#define S5P64X0_SLEEP_CFG               S5P_CLKREG(0x818)
+#define S5P64X0_PWR_STABLE              S5P_CLKREG(0x828)
+
 #define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+#define S5P64X0_WAKEUP_STAT             S5P_CLKREG(0x908)
+
+#define S5P64X0_INFORM0                 S5P_CLKREG(0xA00)
 
 #define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
 #define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
 
+/* HCLK GATE Registers */
+#define S5P64X0_CLK_GATE_HCLK1_FIMGVG   (1 << 2)
+#define S5P64X0_CLK_GATE_SCLK1_FIMGVG   (1 << 2)
+
+/* PCLK GATE Registers */
+#define S5P64X0_CLK_GATE_PCLK_UART3     (1 << 4)
+#define S5P64X0_CLK_GATE_PCLK_UART2     (1 << 3)
+#define S5P64X0_CLK_GATE_PCLK_UART1     (1 << 2)
+#define S5P64X0_CLK_GATE_PCLK_UART0     (1 << 1)
+
+#define S5P64X0_PWR_CFG_MMC1_DISABLE            (1 << 15)
+#define S5P64X0_PWR_CFG_MMC0_DISABLE            (1 << 14)
+#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE        (1 << 11)
+#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE        (1 << 10)
+#define S5P64X0_PWR_CFG_WFI_MASK                (3 << 5)
+#define S5P64X0_PWR_CFG_WFI_SLEEP               (3 << 5)
+
+#define S5P64X0_SLEEP_CFG_OSC_EN        (1 << 0)
+
+#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
+
+#define S5P6450_OTHERS_DISABLE_INT      (1 << 31)
+#define S5P64X0_OTHERS_RET_UART         (1 << 26)
+#define S5P64X0_OTHERS_RET_MMC1         (1 << 25)
+#define S5P64X0_OTHERS_RET_MMC0         (1 << 24)
 #define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
 
 /* Compatibility defines */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 6ce254729f3b..cfdfa4fdadf2 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,14 +34,35 @@
 #define S5P6450_GPQ_BASE                (S5P_VA_GPIO + 0x0180)
 #define S5P6450_GPS_BASE                (S5P_VA_GPIO + 0x0300)
 
+#define S5P64X0_SPCON0                  (S5P_VA_GPIO + 0x1A0)
+#define S5P64X0_SPCON0_LCD_SEL_MASK     (0x3 << 0)
+#define S5P64X0_SPCON0_LCD_SEL_RGB      (0x1 << 0)
+#define S5P64X0_SPCON1                  (S5P_VA_GPIO + 0x2B0)
+
+#define S5P64X0_MEM0CONSLP0             (S5P_VA_GPIO + 0x1C0)
+#define S5P64X0_MEM0CONSLP1             (S5P_VA_GPIO + 0x1C4)
+#define S5P64X0_MEM0DRVCON              (S5P_VA_GPIO + 0x1D0)
+#define S5P64X0_MEM1DRVCON              (S5P_VA_GPIO + 0x1D4)
+
+#define S5P64X0_EINT12CON               (S5P_VA_GPIO + 0x200)
+#define S5P64X0_EINT12FLTCON            (S5P_VA_GPIO + 0x220)
+#define S5P64X0_EINT12MASK              (S5P_VA_GPIO + 0x240)
+
 /* External interrupt control registers for group0 */
 
 #define EINT0CON0_OFFSET                (0x900)
+#define EINT0FLTCON0_OFFSET             (0x910)
+#define EINT0FLTCON1_OFFSET             (0x914)
 #define EINT0MASK_OFFSET                (0x920)
 #define EINT0PEND_OFFSET                (0x924)
 
 #define S5P64X0_EINT0CON0               (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0FLTCON0            (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
+#define S5P64X0_EINT0FLTCON1            (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
 #define S5P64X0_EINT0MASK               (S5P_VA_GPIO + EINT0MASK_OFFSET)
 #define S5P64X0_EINT0PEND               (S5P_VA_GPIO + EINT0PEND_OFFSET)
 
+#define S5P64X0_SLPEN                   (S5P_VA_GPIO + 0x930)
+#define S5P64X0_SLPEN_USE_xSLP          (1 << 0)
+
 #endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index 494e1a8f6f6d..275dc74f4a7b 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -20,6 +20,7 @@
 #include <plat/cpu.h>
 #include <plat/regs-irqtype.h>
 #include <plat/gpio-cfg.h>
+#include <plat/pm.h>
 
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
@@ -134,6 +135,7 @@ static int s5p64x0_alloc_gc(void)
         ct->chip.irq_mask = irq_gc_mask_set_bit;
         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+        ct->chip.irq_set_wake = s3c_irqext_wake;
         ct->regs.ack = EINT0PEND_OFFSET;
         ct->regs.mask = EINT0MASK_OFFSET;
         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
new file mode 100644
index 000000000000..3e6f2456ee9d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-pm.c
@@ -0,0 +1,92 @@
+/* linux/arch/arm/mach-s5p64x0/irq-pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Interrupt handling Power Management
+ *
+ * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/syscore_ops.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <plat/regs-serial.h>
+#include <plat/pm.h>
+
+#include <mach/regs-gpio.h>
+
+static struct sleep_save irq_save[] = {
+        SAVE_ITEM(S5P64X0_EINT0CON0),
+        SAVE_ITEM(S5P64X0_EINT0FLTCON0),
+        SAVE_ITEM(S5P64X0_EINT0FLTCON1),
+        SAVE_ITEM(S5P64X0_EINT0MASK),
+};
+
+static struct irq_grp_save {
+        u32     con;
+        u32     fltcon;
+        u32     mask;
+} eint_grp_save[4];
+
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static int s5p64x0_irq_pm_suspend(void)
+{
+        struct irq_grp_save *grp = eint_grp_save;
+        int i;
+
+        S3C_PMDBG("%s: suspending IRQs\n", __func__);
+
+        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+                irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+                grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
+                grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
+                grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
+        }
+
+        return 0;
+}
+
+static void s5p64x0_irq_pm_resume(void)
+{
+        struct irq_grp_save *grp = eint_grp_save;
+        int i;
+
+        S3C_PMDBG("%s: resuming IRQs\n", __func__);
+
+        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+                __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+                __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
+                __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
+                __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
+        }
+
+        S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+}
+
+static struct syscore_ops s5p64x0_irq_syscore_ops = {
+        .suspend = s5p64x0_irq_pm_suspend,
+        .resume  = s5p64x0_irq_pm_resume,
+};
+
+static int __init s5p64x0_syscore_init(void)
+{
+        register_syscore_ops(&s5p64x0_irq_syscore_ops);
+
+        return 0;
+}
+core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 88857f5a49f7..4a1250cd1356 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -23,6 +23,9 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
+#include <linux/fb.h>
+
+#include <video/platform_lcd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,6 +50,8 @@
 #include <plat/ts.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
+#include <plat/fb.h>
+#include <plat/regs-fb.h>
 
 #define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -92,6 +97,59 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
         },
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win smdk6440_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 24,
+};
+
+static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
+        .win[0]         = &smdk6440_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5p64x0_fb_gpio_setup_24bpp,
+};
+
+/* LCD power controller */
+static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
+                                         unsigned int power)
+{
+        int err;
+
+        if (power) {
+                err = gpio_request(S5P6440_GPN(5), "GPN");
+                if (err) {
+                        printk(KERN_ERR "failed to request GPN for lcd reset\n");
+                        return;
+                }
+
+                gpio_direction_output(S5P6440_GPN(5), 1);
+                gpio_set_value(S5P6440_GPN(5), 0);
+                gpio_set_value(S5P6440_GPN(5), 1);
+                gpio_free(S5P6440_GPN(5));
+        }
+}
+
+static struct plat_lcd_data smdk6440_lcd_power_data = {
+        .set_power      = smdk6440_lte480_reset_power,
+};
+
+static struct platform_device smdk6440_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdk6440_lcd_power_data,
+};
+
 static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_rtc,
@@ -101,6 +159,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_wdt,
         &samsung_asoc_dma,
         &s5p6440_device_iis,
+        &s3c_device_fb,
+        &smdk6440_lcd_lte480wv,
 };
 
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -147,6 +207,17 @@ static void __init smdk6440_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void s5p6440_set_lcd_interface(void)
+{
+        unsigned int cfg;
+
+        /* select TFT LCD type (RGB I/F) */
+        cfg = __raw_readl(S5P64X0_SPCON0);
+        cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
+        cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
+        __raw_writel(cfg, S5P64X0_SPCON0);
+}
+
 static void __init smdk6440_machine_init(void)
 {
         s3c24xx_ts_set_platdata(NULL);
@@ -160,6 +231,9 @@ static void __init smdk6440_machine_init(void)
 
         samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
 
+        s5p6440_set_lcd_interface();
+        s3c_fb_set_platdata(&smdk6440_lcd_pdata);
+
         platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index e1b277b94610..0ab129ecf009 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -23,6 +23,9 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
+#include <linux/fb.h>
+
+#include <video/platform_lcd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,6 +50,8 @@
 #include <plat/ts.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
+#include <plat/fb.h>
+#include <plat/regs-fb.h>
 
 #define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -110,6 +115,59 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
 #endif
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win smdk6450_fb_win0 = {
+        .win_mode       = {
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 24,
+};
+
+static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
+        .win[0]         = &smdk6450_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5p64x0_fb_gpio_setup_24bpp,
+};
+
+/* LCD power controller */
+static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
+                                         unsigned int power)
+{
+        int err;
+
+        if (power) {
+                err = gpio_request(S5P6450_GPN(5), "GPN");
+                if (err) {
+                        printk(KERN_ERR "failed to request GPN for lcd reset\n");
+                        return;
+                }
+
+                gpio_direction_output(S5P6450_GPN(5), 1);
+                gpio_set_value(S5P6450_GPN(5), 0);
+                gpio_set_value(S5P6450_GPN(5), 1);
+                gpio_free(S5P6450_GPN(5));
+        }
+}
+
+static struct plat_lcd_data smdk6450_lcd_power_data = {
+        .set_power      = smdk6450_lte480_reset_power,
+};
+
+static struct platform_device smdk6450_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdk6450_lcd_power_data,
+};
+
 static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_rtc,
@@ -119,6 +177,9 @@ static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_wdt,
         &samsung_asoc_dma,
         &s5p6450_device_iis0,
+        &s3c_device_fb,
+        &smdk6450_lcd_lte480wv,
+
         /* s5p6450_device_spi0 will be added */
 };
 
@@ -166,6 +227,17 @@ static void __init smdk6450_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void s5p6450_set_lcd_interface(void)
+{
+        unsigned int cfg;
+
+        /* select TFT LCD type (RGB I/F) */
+        cfg = __raw_readl(S5P64X0_SPCON0);
+        cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
+        cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
+        __raw_writel(cfg, S5P64X0_SPCON0);
+}
+
 static void __init smdk6450_machine_init(void)
 {
         s3c24xx_ts_set_platdata(NULL);
@@ -179,6 +251,9 @@ static void __init smdk6450_machine_init(void)
 
         samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
 
+        s5p6450_set_lcd_interface();
+        s3c_fb_set_platdata(&smdk6450_lcd_pdata);
+
         platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
new file mode 100644
index 000000000000..69927243d25f
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -0,0 +1,204 @@
+/* linux/arch/arm/mach-s5p64x0/pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 Power Management Support
+ *
+ * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-timer.h>
+#include <plat/wakeup-mask.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+static struct sleep_save s5p64x0_core_save[] = {
+        SAVE_ITEM(S5P64X0_APLL_CON),
+        SAVE_ITEM(S5P64X0_MPLL_CON),
+        SAVE_ITEM(S5P64X0_EPLL_CON),
+        SAVE_ITEM(S5P64X0_EPLL_CON_K),
+        SAVE_ITEM(S5P64X0_CLK_SRC0),
+        SAVE_ITEM(S5P64X0_CLK_SRC1),
+        SAVE_ITEM(S5P64X0_CLK_DIV0),
+        SAVE_ITEM(S5P64X0_CLK_DIV1),
+        SAVE_ITEM(S5P64X0_CLK_DIV2),
+        SAVE_ITEM(S5P64X0_CLK_DIV3),
+        SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
+        SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
+        SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
+};
+
+static struct sleep_save s5p64x0_misc_save[] = {
+        SAVE_ITEM(S5P64X0_AHB_CON0),
+        SAVE_ITEM(S5P64X0_SPCON0),
+        SAVE_ITEM(S5P64X0_SPCON1),
+        SAVE_ITEM(S5P64X0_MEM0CONSLP0),
+        SAVE_ITEM(S5P64X0_MEM0CONSLP1),
+        SAVE_ITEM(S5P64X0_MEM0DRVCON),
+        SAVE_ITEM(S5P64X0_MEM1DRVCON),
+
+        SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+
+/* DPLL is present only in S5P6450 */
+static struct sleep_save s5p6450_core_save[] = {
+        SAVE_ITEM(S5P6450_DPLL_CON),
+        SAVE_ITEM(S5P6450_DPLL_CON_K),
+};
+
+void s3c_pm_configure_extint(void)
+{
+        __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
+}
+
+void s3c_pm_restore_core(void)
+{
+        __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
+
+        s3c_pm_do_restore_core(s5p64x0_core_save,
+                                ARRAY_SIZE(s5p64x0_core_save));
+
+        if (soc_is_s5p6450())
+                s3c_pm_do_restore_core(s5p6450_core_save,
+                                ARRAY_SIZE(s5p6450_core_save));
+
+        s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+}
+
+void s3c_pm_save_core(void)
+{
+        s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+
+        if (soc_is_s5p6450())
+                s3c_pm_do_save(s5p6450_core_save,
+                                ARRAY_SIZE(s5p6450_core_save));
+
+        s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
+}
+
+static int s5p64x0_cpu_suspend(unsigned long arg)
+{
+        unsigned long tmp = 0;
+
+        /*
+         * Issue the standby signal into the pm unit. Note, we
+         * issue a write-buffer drain just in case.
+         */
+        asm("b 1f\n\t"
+            ".align 5\n\t"
+            "1:\n\t"
+            "mcr p15, 0, %0, c7, c10, 5\n\t"
+            "mcr p15, 0, %0, c7, c10, 4\n\t"
+            "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
+
+        /* we should never get past here */
+        panic("sleep resumed to originator?");
+}
+
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
+        { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
+        { .irq = IRQ_RTC_TIC,   .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
+        { .irq = IRQ_HSMMC0,    .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
+        { .irq = IRQ_HSMMC1,    .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
+};
+
+static void s5p64x0_pm_prepare(void)
+{
+        u32 tmp;
+
+        samsung_sync_wakemask(S5P64X0_PWR_CFG,
+                        s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
+
+        /* store the resume address in INFORM0 register */
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
+
+        /* setup clock gating for FIMGVG block */
+        __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
+                (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
+        __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
+                (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
+
+        /* Configure the stabilization counter with wait time required */
+        __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
+
+        /* set WFI to SLEEP mode configuration */
+        tmp = __raw_readl(S5P64X0_SLEEP_CFG);
+        tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
+        __raw_writel(tmp, S5P64X0_SLEEP_CFG);
+
+        tmp = __raw_readl(S5P64X0_PWR_CFG);
+        tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
+        tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
+        __raw_writel(tmp, S5P64X0_PWR_CFG);
+
+        /*
+         * set OTHERS register to disable interrupt before going to
+         * sleep. This bit is present only in S5P6450, it is reserved
+         * in S5P6440.
+         */
+        if (soc_is_s5p6450()) {
+                tmp = __raw_readl(S5P64X0_OTHERS);
+                tmp |= S5P6450_OTHERS_DISABLE_INT;
+                __raw_writel(tmp, S5P64X0_OTHERS);
+        }
+
+        /* ensure previous wakeup state is cleared before sleeping */
+        __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
+
+}
+
+static int s5p64x0_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = s5p64x0_pm_prepare;
+        pm_cpu_sleep = s5p64x0_cpu_suspend;
+        pm_uart_udivslot = 1;
+
+        return 0;
+}
+
+static struct sysdev_driver s5p64x0_pm_driver = {
+        .add            = s5p64x0_pm_add,
+};
+
+static __init int s5p64x0_pm_drvinit(void)
+{
+        s3c_pm_init();
+
+        return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver);
+}
+arch_initcall(s5p64x0_pm_drvinit);
+
+static void s5p64x0_pm_resume(void)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(S5P64X0_OTHERS);
+        tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
+                        S5P64X0_OTHERS_RET_UART);
+        __raw_writel(tmp , S5P64X0_OTHERS);
+}
+
+static struct syscore_ops s5p64x0_pm_syscore_ops = {
+        .resume         = s5p64x0_pm_resume,
+};
+
+static __init int s5p64x0_pm_syscore_init(void)
+{
+        register_syscore_ops(&s5p64x0_pm_syscore_ops);
+
+        return 0;
+}
+arch_initcall(s5p64x0_pm_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
new file mode 100644
index 000000000000..f346ee4af54d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * Base S5P64X0 GPIO setup information for LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <plat/cpu.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+void s5p64x0_fb_gpio_setup_24bpp(void)
+{
+        if (soc_is_s5p6440()) {
+                s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
+        } else if (soc_is_s5p6450()) {
+                s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
+        }
+}