Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Driver specific changes

Again, a lot of platforms have changes in here: pxa, samsung, omap,
at91, imx, ...

* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
  ARM: sa1100: clean up of the clock support
  ARM: pxa: add dummy clock for sa1100-rtc
  RTC: sa1100: support sa1100, pxa and mmp soc families
  RTC: sa1100: remove redundant code of setting alarm
  RTC: sa1100: Clean out ost register
  Input: zylonite-wm97xx - replace IRQ_GPIO() with gpio_to_irq()
  pcmcia: pxa: replace IRQ_GPIO() with gpio_to_irq()
  ARM: EXYNOS: Modified files for SPI consolidation work
  ARM: S5P64X0: Enable SDHCI support
  ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names
  ARM: S5P64X0: Add HSMMC setup for host Controller
  ARM: EXYNOS: Add USB OHCI support to ORIGEN board
  USB: Add Samsung Exynos OHCI diver
  ARM: EXYNOS: Add USB OHCI support to SMDKV310 board
  ARM: EXYNOS: Add USB OHCI device
  net: macb: fix build break with !CONFIG_OF
  i2c: tegra: Support DVC controller in device tree
  i2c: tegra: Add __devinit/exit to probe/remove
  net/at91_ether: use gpio_is_valid for phy IRQ line
  ARM: at91/net: add macb ethernet controller in 9g45/9g20 DT
  ...

8 files changed, 272 insertions, 61 deletions

diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index dd8c85ef6dab..c87f6108eeb1 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -41,6 +41,11 @@ config S5P64X0_SETUP_SPI
         help
           Common setup code for SPI GPIO configurations
 
+config S5P64X0_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
 # machine support
 
 config MACH_SMDK6440
@@ -50,12 +55,16 @@ config MACH_SMDK6440
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
+        select S5P64X0_SETUP_SDHCI_GPIO
         help
           Machine support for the Samsung SMDK6440
 
@@ -66,13 +75,28 @@ config MACH_SMDK6450
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
+        select S5P64X0_SETUP_SDHCI_GPIO
         help
           Machine support for the Samsung SMDK6450
 
+menu "Use 8-bit SDHCI bus width"
+
+config S5P64X0_SD_CH1_8BIT
+        bool "SDHCI Channel 1 (Slot 1)"
+        depends on MACH_SMDK6450 || MACH_SMDK6440
+        help
+          Support SDHCI Channel 1 8-bit bus.
+          If selected, Channel 2 is disabled.
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index e167ca136f5d..12bb951187a4 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -33,3 +33,4 @@ obj-y					+= setup-i2c0.o
 obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP)    += setup-fb-24bpp.o
 obj-$(CONFIG_S5P64X0_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 925d2daa60c7..ee1e8e7f5631 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -380,36 +380,6 @@ static struct clksrc_sources clkset_audio = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 24),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 25),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 26),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_post",
                         .ctrlbit        = (1 << 10),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -447,6 +417,42 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 24),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 25),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 26),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
 static struct clksrc_clk clk_sclk_uclk = {
         .clk    = {
                 .name           = "uclk1",
@@ -504,6 +510,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
         &clk_sclk_uclk,
         &clk_sclk_spi0,
         &clk_sclk_spi1,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2
 };
 
 static struct clk_lookup s5p6440_clk_lookup[] = {
@@ -512,6 +521,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index c390a59f68ac..dae6a13f43bb 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -414,36 +414,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 24),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 25),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 26),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_fimc",
                         .ctrlbit        = (1 << 10),
                         .enable         = s5p64x0_sclk_ctrl,
@@ -508,6 +478,42 @@ static struct clksrc_clk clksrcs[] = {
         },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 24),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 25),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 26),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
 static struct clksrc_clk clk_sclk_uclk = {
         .clk    = {
                 .name           = "uclk1",
@@ -547,6 +553,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
         &clk_sclk_uclk,
         &clk_sclk_spi0,
         &clk_sclk_spi1,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
 };
 
 static struct clk_lookup s5p6450_clk_lookup[] = {
@@ -555,6 +564,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 /* Clock initialization code */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 0d50e79fb9fc..52b89a376447 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -40,6 +40,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
+#include <plat/sdhci.h>
 #include <plat/adc-core.h>
 #include <plat/fb-core.h>
 #include <plat/gpio-cfg.h>
@@ -181,6 +182,10 @@ void __init s5p6440_map_io(void)
         s3c_adc_setname("s3c64xx-adc");
         s3c_fb_setname("s5p64x0-fb");
 
+        s5p64x0_default_sdhci0();
+        s5p64x0_default_sdhci1();
+        s5p6440_default_sdhci2();
+
         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
         init_consistent_dma_size(SZ_8M);
 }
@@ -191,6 +196,10 @@ void __init s5p6450_map_io(void)
         s3c_adc_setname("s3c64xx-adc");
         s3c_fb_setname("s5p64x0-fb");
 
+        s5p64x0_default_sdhci0();
+        s5p64x0_default_sdhci1();
+        s5p6450_default_sdhci2();
+
         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
         init_consistent_dma_size(SZ_8M);
 }
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 34d98a1dae57..a40e325d62c8 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -24,6 +24,7 @@
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/fb.h>
+#include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
 
@@ -52,6 +53,7 @@
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/regs-fb.h>
+#include <plat/sdhci.h>
 
 #include "common.h"
 
@@ -163,6 +165,25 @@ static struct platform_device *smdk6440_devices[] __initdata = {
         &s5p6440_device_iis,
         &s3c_device_fb,
         &smdk6440_lcd_lte480wv,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_INTERNAL,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+        .max_width      = 8,
+        .host_caps      = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
 };
 
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -236,6 +257,10 @@ static void __init smdk6440_machine_init(void)
         s5p6440_set_lcd_interface();
         s3c_fb_set_platdata(&smdk6440_lcd_pdata);
 
+        s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
+
         platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 135cf5d84737..efb69e2f2afe 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -24,6 +24,7 @@
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/fb.h>
+#include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
 
@@ -52,6 +53,7 @@
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/regs-fb.h>
+#include <plat/sdhci.h>
 
 #include "common.h"
 
@@ -181,10 +183,28 @@ static struct platform_device *smdk6450_devices[] __initdata = {
         &s5p6450_device_iis0,
         &s3c_device_fb,
         &smdk6450_lcd_lte480wv,
-
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
         /* s5p6450_device_spi0 will be added */
 };
 
+static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+        .max_width      = 8,
+        .host_caps      = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+
 static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
         .flags          = 0,
         .slave_addr     = 0x10,
@@ -256,6 +276,10 @@ static void __init smdk6450_machine_init(void)
         s5p6450_set_lcd_interface();
         s3c_fb_set_platdata(&smdk6450_lcd_pdata);
 
+        s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
+
         platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..8410af0d12bf
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
+/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/sdhci.h>
+#include <plat/cpu.h>
+
+void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+
+        /* Set all the necessary GPG pins to special-function 2 */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
+                                         S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
+                                         S3C_GPIO_SFN(2));
+
+        /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                if (soc_is_s5p6450()) {
+                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
+                } else {
+                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
+                }
+        }
+}
+
+void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+
+        /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
+
+        switch (width) {
+        case 8:
+                /* Set data pins GPH[6:9] special-function 2 */
+                if (soc_is_s5p6450())
+                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
+                                                 S3C_GPIO_SFN(2));
+                else
+                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
+                                                 S3C_GPIO_SFN(2));
+        case 4:
+                /* set data pins GPH[2:5] special-function 2 */
+                if (soc_is_s5p6450())
+                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
+                                                 S3C_GPIO_SFN(2));
+                else
+                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
+                                                 S3C_GPIO_SFN(2));
+        default:
+                break;
+        }
+
+        /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                if (soc_is_s5p6450()) {
+                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
+                } else {
+                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
+                }
+        }
+}
+
+void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
+        s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
+
+        /* Set data pins GPH[6:9] pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
+}
+
+void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        /* Set all the necessary GPG pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
+}