diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2010-09-01 00:22:17 -0400 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-18 05:33:03 -0400 |
commit | 96f2c00799f9e3c94ac5879d0289376da69bc4a5 (patch) | |
tree | bab1a2da6298812374cc9be4c9304803456a4158 /arch/arm/mach-s5p64x0 | |
parent | 3109e55099cb013f9e1b63d39606dc5d7ecf25bd (diff) |
ARM: S5P64X0: Update IRQ support
This patch updates IRQ support for S5P6440 and S5P6450 SoCs.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0')
-rw-r--r-- | arch/arm/mach-s5p64x0/include/mach/irqs.h | 142 | ||||
-rw-r--r-- | arch/arm/mach-s5p64x0/include/mach/regs-irq.h | 19 |
2 files changed, 161 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h new file mode 100644 index 000000000000..513abffc7604 --- /dev/null +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h | |||
@@ -0,0 +1,142 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - IRQ definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_IRQS_H | ||
14 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
15 | |||
16 | #include <plat/irqs.h> | ||
17 | |||
18 | /* VIC0 */ | ||
19 | |||
20 | #define IRQ_EINT0_3 S5P_IRQ_VIC0(0) | ||
21 | #define IRQ_EINT4_11 S5P_IRQ_VIC0(1) | ||
22 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(2) | ||
23 | #define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */ | ||
24 | #define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */ | ||
25 | #define IRQ_IIC1 S5P_IRQ_VIC0(5) | ||
26 | #define IRQ_I2SV40 S5P_IRQ_VIC0(6) | ||
27 | #define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */ | ||
28 | |||
29 | #define IRQ_2D S5P_IRQ_VIC0(11) | ||
30 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) | ||
31 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) | ||
32 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25) | ||
33 | #define IRQ_WDT S5P_IRQ_VIC0(26) | ||
34 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27) | ||
35 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28) | ||
36 | #define IRQ_DISPCON0 S5P_IRQ_VIC0(29) | ||
37 | #define IRQ_DISPCON1 S5P_IRQ_VIC0(30) | ||
38 | #define IRQ_DISPCON2 S5P_IRQ_VIC0(31) | ||
39 | |||
40 | /* VIC1 */ | ||
41 | |||
42 | #define IRQ_EINT12_15 S5P_IRQ_VIC1(0) | ||
43 | #define IRQ_PCM0 S5P_IRQ_VIC1(2) | ||
44 | #define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */ | ||
45 | #define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */ | ||
46 | #define IRQ_UART0 S5P_IRQ_VIC1(5) | ||
47 | #define IRQ_UART1 S5P_IRQ_VIC1(6) | ||
48 | #define IRQ_UART2 S5P_IRQ_VIC1(7) | ||
49 | #define IRQ_UART3 S5P_IRQ_VIC1(8) | ||
50 | #define IRQ_DMA0 S5P_IRQ_VIC1(9) | ||
51 | #define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */ | ||
52 | #define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */ | ||
53 | #define IRQ_NFC S5P_IRQ_VIC1(13) | ||
54 | #define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */ | ||
55 | #define IRQ_SPI0 S5P_IRQ_VIC1(16) | ||
56 | #define IRQ_SPI1 S5P_IRQ_VIC1(17) | ||
57 | #define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */ | ||
58 | #define IRQ_IIC S5P_IRQ_VIC1(18) | ||
59 | #define IRQ_DISPCON3 S5P_IRQ_VIC1(19) | ||
60 | #define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) | ||
61 | #define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */ | ||
62 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(24) | ||
63 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(25) | ||
64 | #define IRQ_OTG S5P_IRQ_VIC1(26) | ||
65 | #define IRQ_DSI S5P_IRQ_VIC1(27) | ||
66 | #define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) | ||
67 | #define IRQ_TSI S5P_IRQ_VIC1(29) | ||
68 | #define IRQ_PENDN S5P_IRQ_VIC1(30) | ||
69 | #define IRQ_TC IRQ_PENDN | ||
70 | #define IRQ_ADC S5P_IRQ_VIC1(31) | ||
71 | |||
72 | /* UART interrupts, S5P6450 has 5 UARTs */ | ||
73 | #define IRQ_S5P_UART_BASE4 (96) | ||
74 | #define IRQ_S5P_UART_BASE5 (100) | ||
75 | |||
76 | #define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD) | ||
77 | #define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD) | ||
78 | #define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR) | ||
79 | |||
80 | #define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD) | ||
81 | #define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD) | ||
82 | #define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR) | ||
83 | |||
84 | /* S3C compatibilty defines */ | ||
85 | #define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4 | ||
86 | #define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5 | ||
87 | |||
88 | /* S5P6450 EINT feature will be added */ | ||
89 | |||
90 | /* | ||
91 | * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined | ||
92 | * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place | ||
93 | * after the pair of VICs. | ||
94 | */ | ||
95 | |||
96 | #define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) | ||
97 | |||
98 | #define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) | ||
99 | |||
100 | #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE) | ||
101 | /* | ||
102 | * S5P6440 has 0-15 external interrupts in group 0. Only these can be used | ||
103 | * to wake up from sleep. If request is beyond this range, by mistake, a large | ||
104 | * return value for an irq number should be indication of something amiss. | ||
105 | */ | ||
106 | #define S5P_EINT_BASE2 (0xf0000000) | ||
107 | |||
108 | /* | ||
109 | * Next the external interrupt groups. These are similar to the IRQ_EINT(x) | ||
110 | * that they are sourced from the GPIO pins but with a different scheme for | ||
111 | * priority and source indication. | ||
112 | * | ||
113 | * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO | ||
114 | * interrupts, but for historical reasons they are kept apart from these | ||
115 | * next interrupts. | ||
116 | * | ||
117 | * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the | ||
118 | * machine specific support files. | ||
119 | */ | ||
120 | |||
121 | /* Actually, #6 and #7 are missing in the EINT_GROUP1 */ | ||
122 | #define IRQ_EINT_GROUP1_NR (15) | ||
123 | #define IRQ_EINT_GROUP2_NR (8) | ||
124 | #define IRQ_EINT_GROUP5_NR (7) | ||
125 | #define IRQ_EINT_GROUP6_NR (10) | ||
126 | /* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */ | ||
127 | #define IRQ_EINT_GROUP8_NR (11) | ||
128 | |||
129 | #define IRQ_EINT_GROUP_BASE S5P_EINT(16) | ||
130 | #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0) | ||
131 | #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) | ||
132 | #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) | ||
133 | #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) | ||
134 | #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) | ||
135 | |||
136 | #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) | ||
137 | |||
138 | /* Set the default NR_IRQS */ | ||
139 | |||
140 | #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) | ||
141 | |||
142 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h new file mode 100644 index 000000000000..4aaebdace55f --- /dev/null +++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - IRQ register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IRQ_H | ||
14 | #define __ASM_ARCH_REGS_IRQ_H __FILE__ | ||
15 | |||
16 | #include <asm/hardware/vic.h> | ||
17 | #include <mach/map.h> | ||
18 | |||
19 | #endif /* __ASM_ARCH_REGS_IRQ_H */ | ||